CN1976024A - 电路模块 - Google Patents
电路模块 Download PDFInfo
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- CN1976024A CN1976024A CNA2006101219844A CN200610121984A CN1976024A CN 1976024 A CN1976024 A CN 1976024A CN A2006101219844 A CNA2006101219844 A CN A2006101219844A CN 200610121984 A CN200610121984 A CN 200610121984A CN 1976024 A CN1976024 A CN 1976024A
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- 229920005989 resin Polymers 0.000 claims abstract description 83
- 239000011347 resin Substances 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 238000004382 potting Methods 0.000 claims description 57
- 238000007789 sealing Methods 0.000 abstract 5
- 238000001721 transfer moulding Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005476 soldering Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000007767 bonding agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229910001416 lithium ion Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 230000003442 weekly effect Effects 0.000 description 1
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Abstract
本发明涉及通过封装树脂将安装在基板上的裸芯片及表面安装元件进行封装的电路模块,以提高封装树脂的高度上的精度并抑制静区产生为课题。将裸芯片(12)和表面安装元件(13)安装在电路基板11的基板上面17上,同时,在由封装树脂(15)封装了该裸芯片(12)及表面安装元件(13)的电路模块上,通过传递模塑使封装树脂(15)在电路基板(11)的基板上面17的整面上成形。
Description
技术领域
本发明涉及一种电路模块,特别是涉及由封装树脂封装了安装在基板上的裸芯片及表面安装元件的电路模块。
背景技术
例如,周知电池保护模块是具备由封装树脂封装了安装在基板上的裸芯片及表面安装元件的构造的电路模块。在手机等上使用的可再充电的电池组是将锂离子电池内装在绝缘性的组件中,在该电池组中设置具有防止对锂离子电池过度放电或过度充电的功能的电池保护模块。
图5至图7是用于说明作为现有例的电路模块100的图。在以下的说明中,以电路模块100为例说明了电池保护模块。图5是电路模块100的主视图,图6是去除了电路模块100的封装树脂115的状态的俯视图,另外,图7表示组装了电路模块100的电池组120。
电路模块100是COB(芯片内装)型的模块,如图6所示,是将裸芯片112及表面安装元件113安装在电路基板111上的结构。在裸芯片112与电路基板111的表面形成的接合焊片(无图示)之间配设有引线114。另外,表面安装元件113是通过软锡焊被表面安装在电路基板111的表面形成的电极上的结构。
安装在该电路基板111上的裸芯片112、表面安装元件113以及引线114由于在露出在外部的状态下有耐腐蚀性及机械强度等问题,不能得到充分的可靠性,所以,一般是用封装树脂115进行封装。以往,作为在电路基板111上形成该封装树脂115的方法,一般是使用液状树脂,通过灌封使其滴落在电路基板111上,其后进行加热硬化(例如参照专利文献1-特开2002-190564号公报)。
周知的通过灌封形成封装树脂115的方法是使用分配器将液状树脂滴落在电路基板111上。由此,滴落的液状树脂基于所具有的粘性等在电路基板111上扩展,裸芯片112、表面安装元件113及引线114成为埋设在液状树脂内的状态。然后,在该状态下实施热硬化处理,形成封装树脂115。
这样,在使用了灌封法的场合,将液体树脂在电路基板111上扩展的状态控制为一致是很困难的,形成的封装树脂115的高度(图5中由箭头H2表示)无论怎样都会发生偏差。因此,如图7所示,在将电路模块100组装进电池组120的场合,不能使封装树脂115与电池本体122贴紧配置,需要设置封装树脂115的高度误差部分的余隙(在图7中由箭头ΔH表示)。因此,在使用了具备由灌封法形成的封装树脂115的电路模块100的场合,电池组120特别是在图7中由箭头Z所示方向上有大型化的问题。
另外,在使用了灌封法的场合,为了防止液状树脂从电路基板111的外周滴落,将电路基板111设定得比封装树脂115的形成区域更大。因此,如图5所示,在形成了封装树脂115时,在电路基板111的外周会产生没有形成封装树脂115的区域(在图5中由箭头A所示的区域)。该区域A成为所谓的静区(デツトスペ一ス),电路模块100会大型化。因此,在将该电路模块100组装进电池组120的场合,收装电池本体122的电池盒121也会大型化,电池组120特别是在箭头X所示方向上有大型化的问题。
发明内容
本发明是鉴于上述的问题而提出的方案,目的在于提供可实现提高封装树脂的高度上的精度并可抑制静区的产生的电路模块。
为了解决上述问题,本发明的特征在于采取了下述各措施。
方案1所述的发明是电路模块,将裸芯片和表面安装元件安装在基板的表面,同时,通过封装树脂将该裸芯片及表面安装元件进行封装,其特征在于:通过传递模塑使上述封装树脂在上述基板的表面的整面上成形。
根据上述发明,通过传递模塑使在基板上封装裸芯片及表面安装元件的封装树脂成形,由此,与现有的使用液状树脂通过灌封形成封装树脂的结构相比,能够实现封装树脂的高度上的精度,能够实现电路模块的薄型化。
另外,方案2所述的发明是方案1所述的电路模块,其特征在于:上述裸芯片被引线搭接在上述基板上,同时,该引线的架设方向为向上述基板的长度方向延伸。
根据上述发明,由于引线的架设方向为向基板的长度方向延伸,所以,在传递模塑时以树脂的注入方向为基板的长度方向的场合,能够抑制传递模塑时引线的变位,能够防止邻接的引线间产生干扰。
另外,方案3所述的发明是方案1或2所述的电路模块,其特征在于:上述表面安装元件具备俯视为矩形的形状,其各长度方向与上述基板的长度方向平行。
根据上述发明,由于矩形状的表面安装元件的长度方向与基板的长度方向平行,所以在传递模塑时树脂的注入方向为基板的长度方向的场合,能够使树脂的流动顺利进行,能够抑制内部产生空隙。
另外,方案4所述的发明是方案1至3中的任一项所述的电路模块,其特征在于:与上述封装树脂的上述基板一侧相反一侧的面是与上述基板大致平行的平面。
根据上述发明,通过将与封装树脂的基板一侧相反一侧的面做成与基板大致平行的平面,能够使该平面直接接触其他的元件(例如电池组等),能够抑制安装了电路模块时的静区的产生。
根据本发明,与使用现有的液状树脂通过灌封形成封装树脂的结构相比,能够实现封装树脂的高度上的精度,能够实现电路模块的薄型化。
附图说明
图1是用于说明作为本发明的一个实施例的电路模块的图,(A)是剖视图,(B)是主视图。
图2是表示将作为本发明的一个实施例的电路模块安装在电池组上的状态的图。
图3是去除了作为本发明的一个实施例的电路模块的封装树脂的状态的俯视图。
图4是用于说明电路模块的制造方法的图。
图5是作为现有的一例的电路模块的封装树脂的主视图。
图6是去除了作为现有的一例的电路模块的封装树脂的状态的俯视图。
图7是表示将作为现有的一例的电路模块安装在电池组上的状态的图。
图中:
10-电路模块;11-电路基板;12-裸芯片;13-表面安装元件;14-引线;15-封装树脂;16-终端电极;19-树脂上面;20-电池组;21-电池盒;22-电池本体;23-端面;25-焊接膏。
具体实施方式
下面与附图一起说明用于实施本发明的最佳方式。
图1及图2是用于说明作为本发明的一个实施例的电路模块10的图。另外,在以下的说明中,以电路模块10为例说明了电池保护模块。
图1(A)是电路模块10的剖视图,图1(B)是电路模块10的主视图,另外,图2是表示组装进了电路模块10的电池组20。电路模块10是COB(芯片内装)型的模块,大致结构为在电路基板11上安装了裸芯片12及表面安装元件13等的同时,由封装树脂15封装了该裸芯片12及表面安装元件13等。
电路基板11是例如多层的树脂基板,在基板上面17上形成无图示的接合焊片和电极,在基板下面18上形成终端电极16。在基板上面17上形成的接合焊片等与在基板下面18上形成的终端电极16是通过在电路基板11内形成的内部配线连接的结构。
裸芯片12是IC或FET,正面朝上被固定在电路基板11上。裸芯片12向电路基板11的固定能够使用粘接剂,该裸芯片12与电路基板11的电连接是使用引线14进行的。即:在裸芯片12的上部形成的电极焊片(電極パツド)和电路基板11的基板上面17上形成的接合焊片之间实施引线接合处理,由此电路基板11和裸芯片12成为通过引线14而电连接的结构。
表面安装元件13是例如电容器和电阻。该表面安装元件13是通过软铅焊被表面安装在电路基板11的基板上面17上形成的电极(无图示)上的结构。在图1所示的例中,表面安装元件13距离基板上面17的高度高于引线14的环道(ル一プ)高度,但根据表面安装元件13的种类也有引线14的环道高度比表面安装元件13高的情况。如后所述,以起始于该基板上面17的高度最高的零件为基准设定封装树脂15的高度(在图1(B)中由箭头H1表示)。
终端电极16是用于将电路模块10进行外部连接的电极。如图2所示,在将电路模块10安装在电池组20上的场合,终端电极16露出在电池盒21的外部,由此成为可与外部的电路(例如手机的通信电路)连接的结构。
接着,说明作为本发明的要部的封装树脂15。
如前所述,由于安装在电路基板11上的裸芯片12、表面安装元件13及引线14等在露出在外部的状态下很难得到充分的可靠性,所以,一般是由封装树脂15进行封装。本实施例的特征在于通过传递模塑使该封装树脂15成形。另外,在本实施例中是通过在基板上面17的整面上形成封装树脂15,来封装裸芯片12、表面安装元件13及引线14的结构。作为该封装树脂15的材料能够使用环氧树脂等的热硬化性树脂。
如本实施例,通过传递模塑使在电路基板11上封装裸芯片12及表面安装元件13的封装树脂15成形,由此,与现有的灌封液状树脂形成封装树脂15的结构(参照图5)相比,能够实现封装树脂15的高度上的精度。即:在现有的灌封形成封装树脂115的场合,在其高度H2上会产生很大的偏差。与此不同,在由传递模塑形成封装树脂15的场合,由于是使用金属模具(无图示)形成封装树脂15,所以能够高精度地形成其高度H1(参照图1(B))。
另外,在使用了灌封法的场合,为了防止上述的树脂滴落,需要将电路基板111的大小设定得比封装树脂115的形成区域大(参照由图5的箭头A所示的区域)。但是,在用传递模塑形成封装树脂15的场合,不需要在封装树脂15上设置灌封法所需的防止树脂滴落区域。
因此,能够抑制在封装树脂15上产生所谓的静区,能够实现电路模块10的小型化。具体地说,能够缩短封装树脂15的图中箭头X方向(长度方向)的长度,随之能够缩短电路模块10的长度方向的长度(图1(B)中箭头L1所示长度)。另外,如图1(A)所示,由于封装树脂15的侧面15a与电路基板11的侧面11a成为同一平面,所以即便在将电路模块10安装在电池组20上的场合,如图2所示,也能够防止在电池组20上形成不需要的空间。
进而,在传递模塑时,封装树脂15的树脂上面19(与封装树脂15的电路基板一侧相反一侧的面)形成与电路基板11大致平行的平面。通过该结构,如图2所示,在将电路模块10安装在电池组20上时,能够使树脂上面19直接接触电池本体22的端面23。
由此,在将电路模块10安装在电池组20上时,能够抑制电池盒21上产生静区,能够实现电池组20特别是在图2中箭头Z方向上的小型化。如上所述,通过在电池组20上使用本实施例的电路模块10,能够实现电池组20在图中箭头X方向及Z方向双方上的小型化。
下面,说明电路模块10的制造方法。图4是用于说明电路模块10的制造方法的图。
在制造电路模块10时,首先在电路基板11(没有被单片化的状态的基板)上形成的电极上涂敷焊接膏25。作为该焊接膏25的涂敷方法能够使用丝网印刷法。而且,如图4(A)所示,在该涂敷的焊接膏25上安装表面安装元件13。另外,裸芯片12是用粘接剂26粘接在规定位置。
在通过焊接膏25将表面安装元件13临时固定在所有的电极上后,将该电路基板11放入回流炉中进行加热处理。由此,通过使焊接膏25内的焊料熔融,将表面安装元件13焊接在电路基板11上。
接着,通过粘接剂26将裸芯片12临时固定,通过烘箱进行热硬化将裸芯片12粘接在电路基板11上。图4(B)表示将裸芯片12及表面安装元件13安装在电路基板11上的状态。
接着,将引线14引线接合在裸芯片12的上部形成的电极焊片(无图示)与电路基板11的基板上面17上形成的接合焊片(无图示)之间。由此,如图4(C)所示,电路基板11和裸芯片12成为由引线14电连接的状态。
接着如上所述,将安装了裸芯片12及表面安装元件13的电路基板11安装在无图示的金属模具内,实施传递模塑。在实施该传递模塑时,例如图3所示,使引线14的架设方向向电路基板11的长度方向(箭头X所示方向)延伸,同时,成为封装树脂15的树脂注入金属模具的方向也成为如图3中箭头所示的电路基板11的长度方向(箭头X所示方向),这是有效的。根据该结构,能够抑制传递模塑时引线14的变位,能够防止在邻接的引线之间产生干扰。
另外,在将表面安装元件13安装在电路基板11上时,如图3所示,矩形状的表面安装元件13的各长度方向与电路基板11的长度方向平行,且成为封装树脂15的树脂注入金属模具的方向也为如图3中箭头所示的电路基板11的长度方向(箭头X所示方向),这是有效的。根据该结构,在传递模塑时,能够使成为金属模具内的封装树脂15的树脂的流动顺利,能够抑制在封装树脂15的内部产生空隙。
如上所述,形成封装树脂15后,在图4(E)中箭头D所示的规定的单片化位置上进行切片处理,由此制造电路模块10。
以上详述了本发明的最佳实施例,但本发明并不限定于涉及的特定的实施例,可以在技术方案的范围内记载的本发明的要旨的范围内进行各种变形、变更。
本发明适用于能够实现小型化并可防止破损的电路模块、电池组及电路模块的制造方法。
Claims (4)
1.一种电路模块,在基板的表面安装有裸芯片和表面安装元件,同时,通过封装树脂将该裸芯片和表面安装元件进行封装,其特征在于:通过传递模塑使上述封装树脂在上述基板的表面的整面上成形。
2.根据权利要求1所述的电路模块,其特征在于:上述裸芯片被引线接合在上述基板上,同时,该引线的架设方向为向上述基板的长度方向延伸。
3.根据权利要求1或2所述的电路模块,其特征在于:上述表面安装元件具有俯视为矩形的形状,其各长度方向与上述基板的长度方向平行。
4.根据权利要求1至3任一项所述的电路模块,其特征在于:与上述封装树脂的上述基板一侧相反一侧的面为与上述基板大致平行的平面。
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CN101728281A (zh) * | 2008-10-15 | 2010-06-09 | 三美电机株式会社 | 电路模块的制造工序 |
CN101577346B (zh) * | 2008-05-09 | 2011-09-28 | 三星Sdi株式会社 | 电池组 |
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JP2011096865A (ja) * | 2009-10-30 | 2011-05-12 | Sharp Corp | 基板部材、モジュール、電気機器、およびモジュールの製造方法 |
JP5949667B2 (ja) | 2013-06-03 | 2016-07-13 | 株式会社デンソー | モールドパッケージおよびその製造方法 |
DE102019216720A1 (de) * | 2019-10-30 | 2021-05-06 | Robert Bosch Gmbh | Verfahren und Vorrichtung zum Erzeugen eines Elektronikmoduls |
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JPH01192146A (ja) * | 1988-01-27 | 1989-08-02 | Mitsubishi Electric Corp | 半導体装置用基板 |
JP2602343B2 (ja) * | 1990-05-07 | 1997-04-23 | 三菱電機株式会社 | Icカード |
JP2774906B2 (ja) * | 1992-09-17 | 1998-07-09 | 三菱電機株式会社 | 薄形半導体装置及びその製造方法 |
JP2565300B2 (ja) * | 1994-05-31 | 1996-12-18 | 日本電気株式会社 | 半導体装置 |
JP3541491B2 (ja) * | 1994-06-22 | 2004-07-14 | セイコーエプソン株式会社 | 電子部品 |
JPH1117099A (ja) * | 1996-11-12 | 1999-01-22 | T I F:Kk | メモリモジュール |
JPH10150290A (ja) * | 1996-11-19 | 1998-06-02 | Hitachi Ltd | 樹脂封止材およびそれを使用した半導体装置並びにその製造方法 |
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JP3558595B2 (ja) * | 2000-12-22 | 2004-08-25 | 松下電器産業株式会社 | 半導体チップ,半導体チップ群及びマルチチップモジュール |
TW503538B (en) * | 2000-12-30 | 2002-09-21 | Siliconware Precision Industries Co Ltd | BGA semiconductor package piece with vertically integrated passive elements |
JP3718131B2 (ja) * | 2001-03-16 | 2005-11-16 | 松下電器産業株式会社 | 高周波モジュールおよびその製造方法 |
JP2002280402A (ja) * | 2001-03-22 | 2002-09-27 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR100555495B1 (ko) * | 2003-02-08 | 2006-03-03 | 삼성전자주식회사 | 칩 어레이 몰딩용 몰드 다이, 그것을 포함하는 몰딩 장치및 칩 어레이 몰딩 방법 |
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TWI249772B (en) * | 2005-06-07 | 2006-02-21 | Siliconware Precision Industries Co Ltd | Semiconductor device for accommodating large chip, fabrication method thereof, and carrier used in the semiconductor device |
-
2005
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-
2006
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CN101577346B (zh) * | 2008-05-09 | 2011-09-28 | 三星Sdi株式会社 | 电池组 |
US8956749B2 (en) | 2008-05-09 | 2015-02-17 | Samsung Sdi Co., Ltd. | Battery pack |
CN101728281A (zh) * | 2008-10-15 | 2010-06-09 | 三美电机株式会社 | 电路模块的制造工序 |
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