CN1943031A - 集成电路、制造该集成电路的方法与组件以及具有该集成电路的移动电话 - Google Patents
集成电路、制造该集成电路的方法与组件以及具有该集成电路的移动电话 Download PDFInfo
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Abstract
本发明公开了一种集成电路,其包含:芯片上电子元件(32),具有位于气密性密封腔(64)内的有源表面(58)以及气密性密封该腔的覆盖物(66);以及附加电子元件(74),其中附加电子元件固定在覆盖物上。
Description
技术领域
本发明涉及集成电路,制造该集成电路的方法与组件以及具有该集成电路的移动电话。
背景技术
已知集成电路包括:
芯片上电子元件,具有气密性密封腔内的有源表面以及气密性密封该腔的覆盖物,以及
附加的电子元件。
下文中,术语“芯片上电子元件”理解成指一种电子元件,该电子元件形成于集成电路的管芯或芯片上。
这种集成电路例如用于移动电话。在移动电话中,芯片上电子元件具有位于气密性密封腔内的有源表面,且可以是例如表面声波(SAW)滤波器。
芯片上电子元件连接到其他电子元件以形成电子电路。下文中,电子元件理解成指执行特定功能并影响电子电路行为的电子元件。典型地,电子元件分类成有源元件与无源元件。
有源元件包含至少两个用于接收能量的输入。这些输入之一所接收的能量被用于控制由另一个输入接收的能量。这种有源元件例如能够控制电压或电流,从而在该电子元件内产生增益或开关动作。有源元件的示例包括晶体管等。
另一方面,无源元件包含用于接收能量以及调整接收的能量的唯一输入。这种无源元件为例如线圈、电阻器、电容器、传输线、结构线等。
理想地,将尽可能多的电子元件集成到单个集成电路中而不增加其尺寸。
发明内容
因此,本发明的目标是微型化包含具有气密性密封腔内有源表面的芯片上电子元件的集成电路。
本发明提供了一种集成电路,其中附加的电子元件固定在覆盖物上。
在上述集成电路中,覆盖物用作有源表面的气密性密封盖,并用作固定附加电子元件的基板。因此,用于制造该集成电路的芯片的尺寸可以减小,因为在集成电路芯片的表面上没有任何附加的电子元件。
一种集成电路,其中在覆盖物的表面上制造附加电子元件,该覆盖物包含用于制造附加电子元件的基板,提供了减小集成电路制造成本的优点。
一种集成电路,其中覆盖物的表面包含外表面和内表面,内表面与所述腔接触且外表面与内表面相对,并在该覆盖物的外表面上制造附加电子元件,具有简化覆盖物制造工艺的进一步优点。
一种集成电路,其中:
该芯片上电子元件包含具有有源表面的顶面,以及邻近该有源表面用于将芯片上电子元件连接到附加电子元件的连接焊盘,
该覆盖物调整成适于覆盖有源表面而不覆盖连接焊盘,并且
该集成电路进一步包含将附加电子元件直接连接到连接焊盘的导线,
具有降低集成电路对噪声的灵敏度的进一步优点。
一种集成电路,其中该集成电路进一步包含适于接收或发送射频信号的芯片上收发器,具有使该集成电路适用于射频收发器的优点。
本发明还涉及在上述集成电路中使用的组件。
本发明进一步涉及包含上述集成电路的移动电话。
本发明还涉及包含下述步骤的方法:
制造一种集成电路,其中该集成电路包含芯片上电子元件,该电子元件具有在气密性密封腔内的有源表面以及气密性密封该腔的覆盖物;以及
其中该方法包含步骤:
将附加电子元件固定在覆盖物上。
在独立权利要求中论述了所主张的本发明的其他特征。
本发明的这些与其他方面通过下述描述、图示及权利要求将变得显而易见。
附图说明
图1为结合了根据本发明的集成电路的移动电话的示意图;
图2为根据本发明的集成电路的剖面图;
图3为图2中集成电路使用的覆盖物的顶视图;
图4为图2的集成电路的制造方法的流程图。
具体实施方式
图1示出了射频通信电话的一部分。作为示例,该射频通信设备为全球移动通信系统(GSM)蜂窝移动射频电话4。电话4能够使用射频信号与蜂窝射频电话网络的基站进行通信。
图1仅示出了理解本发明所需的细节。
为了接收或发射射频信号,电话4包含可调谐射频收发器14(下文中称为“集成电路14”)以及基带处理器18。
集成电路14连接到天线20以接收和发射射频信号。
集成电路14能够将射频信号转化成基带信号或者将基带信号转化成射频信号。换而言之,集成电路14的主要任务是从射频信号除去载波或将载波添加到基带信号。
通过总线22在处理器18与集成电路14之间交换基带信号,该总线22将集成电路14连接到处理器18。
处理器18按照传统方式处理基带信号。
集成电路14为包含三个芯片上电子元件的集成电路,即包含两个SAW滤波器30与32以及收发电路34。
滤波器30与32连接到天线20与收发电路34。更精确地,滤波器30适于过滤接收到的射频信号,滤波器32适于过滤发射的射频信号。
图2示出了沿线36(图1)的集成电路14的剖面图,且仅示出了理解本发明所需的细节。
集成电路14包含位于封装组件42内的水平半导体管芯或芯片40。
半导体管芯40通过键合、导线46连接到封装引线44。各个键合导线一端连接到封装引线44,在另一端连接到键合焊盘48。
管芯40为用于制造诸如收发器电路34与滤波器32的芯片上电子元件的基板。例如,管芯40为硅基板。
电路34包含将电路34连接到键合焊盘48和滤波器32的键合焊盘50。使用键合导线52制成电路34与键合焊盘48之间的连接,通过另一个键合导线52制成电路34与滤波器32之间的连接。
滤波器32包含制造在管芯40顶上的水平压电元件56。元件56的上表面是被键合焊盘60环绕的有源表面58。
例如,有源表面58位于元件56的上表面的中心处。对于SAW滤波器的情形,有源表面58包含传统梳状电极。这些梳状电极连接到对应的键合焊盘60。
有源表面58安置于腔64内,该腔64与诸如空气的清洁惰性气体接触。
覆盖物66气密性密封腔64。覆盖物66由垂直壁68制成,该垂直壁68围绕有源表面58并支撑水平矩形平顶板70。优选地,覆盖物66由硅片制成。
例如,顶板70具有1.5mm2方形顶部外表面,该顶部外表面位于有源表面58上方150微米处。腔64的高度在有源表面58上方20至30微米。
附加电子元件74(下文中称为“线圈74”)制造在顶板70的外部顶面上。线圈74被示成阻抗匹配线圈,其使得滤波器32的阻抗与电路34的阻抗相匹配。覆盖物66与固定在其上的线圈74形成了组件。
图3示出了线圈74的顶视图。线圈74由线圈形状的带状线76以及两个连接焊盘78与80制成。焊盘78连接到线76的一端,焊盘80连接到线76的另一端。线76的匝数决定预定阻抗值。优选地,线圈74的阻抗值范围为0.5至5nH。
使用下键合导线82将焊盘78与80连接到各个焊盘60(图2)。因此,线圈74平行地连接在滤波器32的两个输出之间。
将参考图4解释覆盖物66的制造工艺200。
在步骤100中,使用传统方法制造覆盖物66。
之后,覆盖物66被用作基板,以便使用例如传统金属化工艺在顶板70顶面上制造线圈74。
更精确地,在步骤102中,在顶板70的顶面上执行第一金属的沉积。该第一金属为例如铝。
接着,在步骤104,对第一金属层执行干法或蚀法蚀刻以形成线76的第一阶段。
随后,在步骤106,产生第一绝缘层以覆盖第一金属层。
在步骤108,将第二金属层沉积在第一绝缘层顶上。
随后,在步骤110,对第二金属层执行干法或蚀法蚀刻以形成线76的第二阶段以及焊盘78与80。
最后,在步骤112,在第二金属层顶上产生第二绝缘层。
由于在覆盖物66顶上制造线圈74这一事实,管芯40的表面减小了1.5mm2。用于封装管芯40的封装组件也得到减小。
由于焊盘60位于元件56的顶面上,导线82缩短。因此,导线82对电磁噪声的灵敏度降低,集成电路14更加可靠。
许多附加实施方案是可能的。例如,可以在覆盖物66内制造其他无源或有源元件。其他无源元件的示例为电容器或电阻器。还可以在覆盖物66中制造诸如晶体管的有源元件。
此外,可以在顶板70的内表面上制造附加电子元件,其与腔64接触。这种实施方案使得附件电子元件与SAW滤波器之间的电学连接更短。
本发明适用于包含诸如覆盖物66的用于气密性密封腔的覆盖物的所有元件。例如,本发明还适用于体声波(BAW)滤波器、例如微断续器的微电机系统(MEMS)等。
可以独立于覆盖物制造附加电子元件,并随后将其添加或粘附到覆盖物。
可以在单个覆盖物上固定(例如粘附)或制造一个或多个附加电子元件。
Claims (10)
1.一种集成电路,包括:
芯片上电子元件(32),具有位于气密性密封腔(64)内的有源表面(58)以及气密性密封该腔的覆盖物(66),以及
附加的电子元件(74),
其中该附加的电子元件固定在该覆盖物上。
2.权利要求1的集成电路,其中在该覆盖物的表面上制造附加的电子元件(74),该覆盖物包含用于制造所述附加电子元件的基板。
3.根据权利要求2的集成电路,其中该覆盖物的表面包含外表面和内表面,该内表面与所述腔接触且该外表面与内表面相对,在该覆盖物的外表面上制造所述附加电子元件。
4.根据权利要求3的集成电路,其中:
该芯片上电子元件(32)包含具有有源表面的顶面,以及紧邻该有源表面的、将芯片上电子元件连接到附加电子元件的连接焊盘(60),
该覆盖物被调整成适于覆盖所述有源表面而不覆盖连接焊盘,以及
该集成电路进一步包含将所述附加电子元件直接连接到连接焊盘的导线。
5.根据任一前述权利要求的集成电路,其中该集成电路进一步包含适于接收或发射射频信号的芯片上收发器。
6.根据任一前述权利要求的集成电路,其中所述附加电子元件(74)为具有平坦线圈形导线(76)的线圈,所述平坦线圈形导线(76)具有阻抗值。
7.适于用在根据任一前述权利要求的集成电路中的组件,该组件包括所述附加电子元件(74)以及气密性密封所述腔的覆盖物(66),其中所述附加电子元件固定在所述覆盖物上。
8.包含根据权利要求5的集成电路的移动电话。
9.一种方法,其包括步骤:
制造一种集成电路,该集成电路包含芯片上电子元件,该芯片上电子元件具有在气密性密封腔内的有源表面以及气密性密封该腔的覆盖物;且
其中该方法包括如下步骤:
将附加电子元件固定在该覆盖物上。
10.根据权利要求9的方法,进一步包含蚀刻该覆盖物表面上的附加电子元件。
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EP (1) | EP1741138B1 (zh) |
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US20060211233A1 (en) * | 2005-03-21 | 2006-09-21 | Skyworks Solutions, Inc. | Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure |
US7576426B2 (en) * | 2005-04-01 | 2009-08-18 | Skyworks Solutions, Inc. | Wafer level package including a device wafer integrated with a passive component |
US7635606B2 (en) * | 2006-08-02 | 2009-12-22 | Skyworks Solutions, Inc. | Wafer level package with cavities for active devices |
US8320102B2 (en) * | 2006-09-27 | 2012-11-27 | Kyocera Corporation | Capacitor, capacitor device, electronic component, filter device, communication apparatus, and method of manufacturing capacitor device |
US20080217708A1 (en) * | 2007-03-09 | 2008-09-11 | Skyworks Solutions, Inc. | Integrated passive cap in a system-in-package |
JP2009010121A (ja) * | 2007-06-27 | 2009-01-15 | Hitachi Media Electoronics Co Ltd | 中空封止素子、その製造方法ならびに中空封止素子を用いた移動通信機器 |
CN101878527B (zh) * | 2007-11-30 | 2012-09-26 | 斯盖沃克斯瑟路申斯公司 | 使用倒装芯片安装的晶片级封装 |
US8900931B2 (en) | 2007-12-26 | 2014-12-02 | Skyworks Solutions, Inc. | In-situ cavity integrated circuit package |
US8068003B2 (en) * | 2010-03-10 | 2011-11-29 | Altera Corporation | Integrated circuits with series-connected inductors |
JP5241909B2 (ja) | 2011-12-22 | 2013-07-17 | 太陽誘電株式会社 | 回路基板 |
JP5241910B2 (ja) * | 2011-12-22 | 2013-07-17 | 太陽誘電株式会社 | 回路基板 |
US9219483B1 (en) | 2014-03-05 | 2015-12-22 | Altera Corporation | Integrated circuit floorplans |
CN106357294A (zh) * | 2016-08-31 | 2017-01-25 | 安徽赛福电子有限公司 | 一种双收发器和滤波组件的无线通讯装置 |
DE112017007845T5 (de) * | 2017-08-09 | 2020-04-23 | Intel Corporation | Integrierte schaltungskomponenten mit substrathohlräumen |
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US6329739B1 (en) * | 1998-06-16 | 2001-12-11 | Oki Electric Industry Co., Ltd. | Surface-acoustic-wave device package and method for fabricating the same |
JP4049239B2 (ja) * | 2000-08-30 | 2008-02-20 | Tdk株式会社 | 表面弾性波素子を含む高周波モジュール部品の製造方法 |
KR100518616B1 (ko) * | 2001-01-18 | 2005-10-04 | 노키아 코포레이션 | 필터디바이스 및 필터디바이스를 제조하는 방법 |
JP3444420B2 (ja) * | 2001-03-26 | 2003-09-08 | セイコーエプソン株式会社 | 弾性表面波装置及びその製造方法 |
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US6873529B2 (en) * | 2002-02-26 | 2005-03-29 | Kyocera Corporation | High frequency module |
JP2004129223A (ja) * | 2002-07-31 | 2004-04-22 | Murata Mfg Co Ltd | 圧電部品およびその製造方法 |
US7064426B2 (en) * | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
KR20050074961A (ko) * | 2002-10-08 | 2005-07-19 | 치팩, 인코포레이티드 | 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈 |
US7242101B2 (en) * | 2004-07-19 | 2007-07-10 | St Assembly Test Services Ltd. | Integrated circuit die with pedestal |
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WO2005101502A1 (en) | 2005-10-27 |
DE602005025746D1 (de) | 2011-02-17 |
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