CN1875485A - 激光熔丝的结构及编程 - Google Patents

激光熔丝的结构及编程 Download PDF

Info

Publication number
CN1875485A
CN1875485A CNA2004800321736A CN200480032173A CN1875485A CN 1875485 A CN1875485 A CN 1875485A CN A2004800321736 A CNA2004800321736 A CN A2004800321736A CN 200480032173 A CN200480032173 A CN 200480032173A CN 1875485 A CN1875485 A CN 1875485A
Authority
CN
China
Prior art keywords
fuse link
layer
fuse
laser beam
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004800321736A
Other languages
English (en)
Other versions
CN100499130C (zh
Inventor
丹什·A·巴达米
汤姆·C·李
李保振
杰拉尔德·马图西维茨
威廉·T·莫特西夫
克里斯托弗·D·马齐
金博尔·M·沃森
琼·E·温
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1875485A publication Critical patent/CN1875485A/zh
Application granted granted Critical
Publication of CN100499130C publication Critical patent/CN100499130C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明涉及用于制造激光熔丝的方法和结构及编程该激光熔丝的方法。该激光熔丝包括第一电介质层,其具有填充以第一自钝化导电材料的两个通孔。熔丝链位于所述第一电介质层上。所述熔丝链电连接所述两个通孔且包括具有暴露于激光束之后改变其电阻这一特性的第二材料。两个台位于所述熔丝链之上且在所述两个通孔正上方。所述两个台每个包括第三自钝化导电材料。该激光熔丝通过将激光束导向所述熔丝链而被编程。控制该激光束使得所述熔丝链的电阻响应于所述激光束对所述熔丝链的影响而改变,但所述熔丝链不被熔断。这样的电阻改变被检测到且被转换成数字信号。

Description

激光熔丝的结构及编程
技术领域
本发明涉及激光熔丝的设计及编程该激光熔丝的方法。
背景技术
现有技术的普通激光熔丝通过将激光束导向该激光熔丝而被编程(program)。熔丝的加热和膨胀导致该熔丝之上的钝化开口且该熔丝蒸发。激光熔丝的切头(cut end)现在开放且易于氧化和腐蚀,这可通过电路延伸。另外,熔丝的膨胀可导致向下或横向裂开,这可引起对周围器件的损坏。
因此,需要一种激光熔丝的设计,其最小化由熔丝编程引起的对围绕该熔丝的器件的腐蚀和氧化。另外,需要一种编程该激光熔丝的方法,其减小围绕该熔丝的结构裂开的风险。
发明内容
本发明提供用于形成电子结构的方法,包括步骤:在第一电介质层中形成至少两个通孔;以第一自钝化导电材料填充所述两个通孔;在所述第一电介质层上形成熔丝链层,所述熔丝链层包括具有暴露于激光束之后改变其电阻这一特性的第二材料;在所述熔丝链层之上形成台层,所述台层包括第三自钝化导电材料;及由所述熔丝链层和所述台层分别形成熔丝链和两个台,其中所述熔丝链电连接所述两个通孔,且所述两个台位于所述两个通孔正上方。
本发明还提供一种电子结构,包括:第一电介质层,其具有填充以第一自钝化导电材料的至少两个通孔;熔丝链,其在所述第一电介质层上,所述熔丝链电连接所述两个通孔且包括具有暴露于激光束之后改变其电阻这一特性的第二材料;及两个台,其在所述熔丝链之上且在所述两个通孔正上方,所述两个台包括第三自钝化导电材料。
本发明还提供一种用于编程激光熔丝的方法,该激光熔丝具有熔丝链,该熔丝链包括具有暴露于激光束之后改变其电阻这一特性的材料,该方法包括步骤:将激光束导向所述熔丝链,所述激光束被控制从而所述熔丝链的电阻响应于所述激光束对所述熔丝链的影响而改变,但所述熔丝链不熔断。
本发明还提供一种电子结构,包括:第一电介质层,其具有至少第一通孔和第二通孔,两者都被填充以第一导电材料;第一吸氧剂屏蔽件和第二吸氧剂屏蔽件,其分别位于所述第一和第二通孔中的所述第一导电材料正上方且与其物理接触,所述第一和第二吸氧剂屏蔽件包括第二导电的吸氧剂材料;及熔丝链,其电连接所述第一和第二吸氧剂屏蔽件,所述熔丝链包括具有暴露于激光束之后改变其电阻这一特性的第三材料。
本发明提供一种用于制造激光熔丝的方法和结构,其最小化对该激光熔丝下面的器件的腐蚀和氧化。
本发明还提供一种用于编程激光熔丝的方法,其不引起围绕该激光熔丝的结构的破裂。
附图说明
图1示出根据本发明实施例在衬底上包括层间电介质(ILD)层的电子结构的正面剖视图,所述ILD层包括两个通孔;
图2示出TaN(钽氮化物)层及随后的W(钨)层沉积在ILD层上之后的图1;
图3示出除了两个通孔之上的台之外大部分W层被蚀刻掉之后的图2;
图4示出除了两个通孔上面及之间的区域以外大部分TaN层被蚀刻掉之后的图3,留下的TaN层作为熔丝链;
图5示出ILD材料钝化层沉积在图4的整个结构100上之后的图4;
图6示出熔丝链上面的部分钝化层被蚀刻掉从而产生开口之后的图5;
图7示出了熔丝链暴露于激光束之后图6的结构;
图8A-8E示出根据本发明实施例经过一系列制造步骤的电子结构的正面剖视图。
具体实施方式
图1示出根据本发明实施例用于构造激光熔丝的电子结构100的正面剖视图。在一个实施例中,电子结构100包括在硅衬底105顶部的层间电介质(ILD)层110。ILD层110包括填充以例如铝(Al)的两个通孔(via)120a和120b。在一个实施例中,ILD层110可以由低K或者硅氮化物或硅氧化物制成。
示例性地,ILD层110可沉积在硅衬底105上。然后,通过蚀刻工艺生成两个通孔120a和120b。在一个实施例中,该蚀刻工艺可包括数个步骤。首先,正光致抗蚀剂层(未示出)沉积在ILD层110上且对光致抗蚀剂层生成图案,该图案暴露ILD层110的两个通孔120a和120b将位于的两个区域。然后,ILD层110的两个暴露区域通过蚀刻工艺被蚀刻掉,产生两个通孔120a和120b。之后,光致抗蚀剂层被去除,铝可被沉积在整个ILD层110之上,用铝填充两个通孔120a和120b。然后,通孔120a和120b外的多余的铝通过CMP(化学机械抛光)被去除,得到图1中的电子结构100。为了简洁起见,包括ILD层110下的电连接到铝填充的通孔120a和120b的检测电路的器件未被示出。
图2示出TaN(钽氮化物)层210及随后的W(钨)层220沉积在ILD层110上之后的图1。在一个实施例中,TaN层210通过PVD(物理气相沉积)或CVD(化学气相沉积)工艺沉积在ILD层110上。然后,W层220通过CVD工艺沉积在TaN层210上。在一实施例中,TaN层210可为数百埃厚。
图3示出除了分别在两个通孔120a和120b之上的两个台(mesa)220a和220b之外大部分W层220被蚀刻掉之后的图2。在一个实施例中,蚀刻工艺可包括数个步骤。首先,正光致抗蚀剂层(未示出)可沉积在W层220上。然后,生成光致抗蚀剂层上的图案从而覆盖/保护W层220在两个通孔120a和120b正上方的两个区域。然后,可以进行(干或湿)蚀刻从而去除W层220的暴露的(未被光致抗蚀剂层保护的)区域。最后,去除光致抗蚀剂层。所得结构100示于图3中,两个W台220a和220b生成在两个通孔120a和120b正上方。
图4示出除了两个通孔120a和120b上方及之间的区域以外大部分TaN层120被蚀刻掉之后的图3。在一实施例中,该蚀刻工艺可包括数个步骤。首先,正光致抗蚀剂层(未示出)可沉积在TaN层210上,也覆盖两个W台220a和220b。然后,生成光致抗蚀剂层上的图案从而覆盖/保护TaN层210的仅在两个通孔120a和120b正上方及之间的区域。然后,可以进行(干或湿)蚀刻从而去除TaN层210的暴露的(未被光致抗蚀剂层保护的)区域。最后,去除光致抗蚀剂层。所得结构100示于图4中,TaN熔丝链(fuse link)210′生成在两个通孔120a和120b正上方及其之间。TaN熔丝链210′电连接两个铝填充的通孔120a和120b。
图5示出ILD材料钝化层510沉积在图4的整个结构100上之后的图4。ILD钝化层510的目的是保护晶片上包括结构100的器件免于受到污染物和湿气的影响。ILD钝化层510还充当划擦保护层。在一实施例中,ILD钝化层510可由硅氮化物(SixNy)制成。在一实施例中,ILD钝化层510通过CVD(化学气相沉积)工艺沉积在图4的结构100上。
图6示出熔丝链210′上面的部分ILD层510被蚀刻掉从而产生开口610之后的图5。在一实施例中,该蚀刻工艺可包括数个步骤。首先,正光致抗蚀剂层(未示出)可沉积在ILD层510上。然后,用掩模生成光致抗蚀剂层上的图案从而暴露ILD层510的仅TaN熔丝链210′正上方的区域。然后,可以进行(干或湿)蚀刻从而部分去除ILD层510的暴露的(未被光致抗蚀剂层保护的)区域。最后,去除光致抗蚀剂层。所得结构100示于图6中,两个W台220a和220b被部分暴露且熔丝链210′被覆盖以残留的ILD层510c。在一实施例中,可认为本发明的激光熔丝包括TaN熔丝链210′和两个Al填充的通孔120a和120b,因此,下面称为激光熔丝210′、120。因为熔丝链210′源自TaN层210,TaN层210可被称为熔丝链层210。类似地,两个台220a和220b源自W层220,层220可以被称为台层220。
在一实施例中,激光熔丝210′、120的编程(programing)包括将来自激光源620的激光束630通过开口610向下导向到激光熔丝210′、120的TaN熔丝链210′上。熔丝链210′吸收激光束630的一些能量。控制激光束630的能量水平低于会物理损伤或甚至熔断熔丝链210′导致周围结构的破裂的能量水平,但足够强从而改变构成熔丝链210′的材料(即TaN)的相。图7示出熔丝链210′暴露于激光束630之后图6的结构100。图7中可以看出,熔丝链210′没有几何改变。然而,图7中,熔丝链被赋予新的附图标记210″从而表示构成熔丝链210″的材料(即TaN)经历了相变,因此具有不同特性(即更高电阻)。由于TaN的相变,TaN熔丝链210″的电阻增加。换言之,两个通孔120a和120b之间通过熔丝链220″的导电路径的电阻增加。在一实施例中,该电阻增加被检测电路(未示出)检测到且被转换成数字信号(例如从对应于低电阻的逻辑1到对应于高电阻的逻辑0)。结果,激光熔丝210′、120被编程而没有象现有技术中那样被熔断从而产生断路。因此,破裂的可能性和程度被最小化。在TaN材料的情况下,显著增加TaN电阻所需的激光能量水平远低于熔断现有技术的普通激光熔丝所需的能量水平。因此,与现有技术相比,本发明的熔丝编程方法导致的破裂的可能性和程度低得多。因为ILD层510c的ILD材料对激光束透明,所以ILD层510c的厚度对本发明的熔丝编程方法不重要。激光束630的大部分能量可到达熔丝链220′并导致激光熔丝210′、120的电阻增加。结果,如果两个W台220a和220b不需要电连接到外界(例如焊盘),则去除激光熔丝210′、120正上方的部分ILD层510的步骤可被省略。如果两个W台220a和220b需要电连接到外界,则激光熔丝210′正上方的部分ILD层510可被去除从而暴露台220a和220b。ILD层510c(图6)是否留在熔丝链210′顶上对熔丝编程过程不重要。
在上述实施例中,两个通孔120a和120b被填充以铝,其是良好的电导体且也是良好的自钝化材料。铝是良好的自钝化材料,因为它与氧反应从而产生对氧不活泼的化合物,该化合物防止空气中的氧和水蒸汽引起的进一步氧化和腐蚀。使用铝来填充两个通孔120a和120b减小了激光熔丝210′、120下面的器件的氧化和腐蚀。供选地,导电且自钝化的其它材料可用来填充两个通孔120a和120b。使用导电且自钝化材料来填充两个通孔120a和120b有助于最小化激光熔丝210′、120下面的器件的氧化和腐蚀。
在上述实施例中,熔丝链210′由TaN制成,TaN是自钝化的且当激光束630照射在其上时改变其电阻。因为TaN熔丝链210′是自钝化的,即使当TaN熔丝链210′暴露(即IDL层510c被完全去除)时,激光熔丝210′、120下面的器件的氧化和腐蚀也被减小。在一供选实施例中,其它材料(例如钛氮化物TiN、或钨氮化物WN)可用于熔丝链210′,其是自钝化的且具有激光束630影响之后改变其电阻这一特性。在另一实施例中,所用的材料具有暴露于激光束后改变(增加或降低)其电阻的特性。
在上述实施例中,两个台220a和220b由W(钨)制成,其是导电且自钝化的。因为W是导电的,所以激光熔丝210′、120的部件与外界(例如焊盘)之间可进行电连接。因为W是自钝化的且两个台220a和220b位于两个通孔120a和120b正上方,所以激光熔丝210′、120下面的器件通过两个通孔120a和120b的氧化和腐蚀被最小化。在一供选实施例中,两个台220a和220b可以由导电且自钝化的其它材料(例如铝)构成。
在上述实施例中,熔丝链210′暴露于激光束630后具有更高电阻。在供选实施例中,熔丝链210′可以由暴露于激光束630后具有更低电阻的其它材料构成。于是,电阻降低可被检测并转换成数字信号(例如从逻辑0到逻辑1)。
图8A-E示出根据本发明实施例制造电子结构800的步骤。图8A示出根据本发明实施例用于构造激光熔丝的电子结构800的正面剖视图。在一实施例中,电子结构800包括硅(或任何其它半导体)衬底805顶上的ILD层807。ILD层807含有填充以铝(或任何其它良好导电材料)的两个通孔820a和820b。由TaN(或具有暴露于激光束后改变电阻这一特性的任何其它材料)制成的激光熔丝层810沉积在ILD层807上。由硅氮化物(或能够保护下面的层810的任何材料)构成的保护层815沉积在激光熔丝层810上。
图8B示出通过蚀刻掉两个层810和815的大部分,仅留下两个通孔820a和820b之间的台810′、815′而形成台810’、815’之后的图8A。台810′、815′包括TaN熔丝链810′和保护层815′。
图8C示出由钛(或任何其它良好导电的吸氧剂(oxygen-getter)材料)制成的吸氧层825沉积在图8B的整个结构800上之后的图8B(吸氧剂材料是能够容易地与氧反应且吸收氧从而防止氧从该吸氧剂逃脱的材料)。然后,由钨(或任何良好导电材料)制成的端接触层830沉积在吸氧层825上。
图8D示出通过蚀刻掉层825和830的大部分,仅留下分别在两个通孔820a和820b正上方的两个台825a、830a和825b、830b而形成两个台825a、830a和825b、830b之后的图8C。台825a、830a包括吸氧剂屏蔽件825a和端接触台830a。类似地,台825b、830b包括吸氧剂屏蔽件825b和端接触台830b。
图8E示出ILD层840沉积在除了两个端接触台830a和830b之外图8D的整个结构800上之后的图8D。因为Ti是良好的电导体,所以吸氧剂屏蔽件825a和825b将熔丝链810′分别电连接至通孔820a和820b。因为钛(Ti)也是良好的吸氧剂材料,所以吸氧剂屏蔽件825a和825b有效保护分别在两个通孔820a和820b下面的器件免于腐蚀和氧化。
总之,本发明的熔丝编程过程是非破坏性的。激光束630(见图6)仅改变TaN的相,且因此增加TaN熔丝链210′的电阻。另外,用于熔丝编程的激光能量被降低。结果,编程过程期间和之后电介质破裂的风险由于较低的编程激光能量和熔丝编程过程的非破坏性特性而减轻。电介质破裂的更低可能性产生两个优点。第一,产率和可靠性提高;第二,在全局布线层面使用低K电介质材料的可行性得到改善。
通过自钝化端连接(所述两个W台220a和220b)及自钝化熔丝元件(所述熔丝链210′和所述两个Al填充的通孔120a和120b)的结合使用,氧气和湿气通过熔丝元件和有缺陷的衬(liner)(如果有的话)的进入路径被消除。另外,由于TaN的扩散阻挡特性,氧和湿气从熔丝元件至端连接的横向进入路径被去除。
在通孔120a和120b中使用自钝化电导体(铝)作为TaN熔丝链210′与熔丝210′、120下面的检测电路(未示出)之间的接触连接的优点在于自钝化电导体用作氧和湿气吸收剂从而最小化氧和湿气在通孔120a和120b的底角穿透有缺陷的衬(如果有的话)的可能性。
最后的熔丝上钝化工艺(passivation-over-fuse process)具有较宽的灵活性,因为熔丝210′、120正上方的钝化ILD层510的厚度对于编程过程不重要。而且,一种类型的熔丝(例如熔丝210′、120)可用于不同技术,导致制造成本降低。
尽管这里用于说明目的描述了本发明的特定实施例,但很多修改和改变对本领域技术人员将是显然的。因此,所附权利要求意图包括所有这些落在本发明实质精神和范围内的修改和变化。

Claims (20)

1.一种用于形成电子结构的方法,包括步骤:
在第一电介质层中形成至少两个通孔;
以第一自钝化导电材料填充所述两个通孔;
在所述第一电介质层上形成熔丝链层,所述熔丝链层包括具有暴露于激光束之后改变其电阻这一特性的第二材料;
在所述熔丝链层之上形成台层,所述台层包括第三自钝化导电材料;及
由所述熔丝链层和所述台层分别形成熔丝链和两个台,其中所述熔丝链电连接所述两个通孔,且所述两个台位于所述两个通孔正上方。
2.如权利要求1所述的方法,其中所述第二材料包括选自含有TaN、TiN和WN的组的物质。
3.如权利要求1所述的方法,其中所述第一自钝化导电材料包括选自含有Al和W的组的物质。
4.如权利要求1所述的方法,其中所述第三自钝化导电材料包括选自含有Al和W的组的物质。
5.如权利要求1所述的方法,还包括在形成所述台层之前在所述熔丝链层上形成第二电介质层的步骤。
6.如权利要求1所述的方法,还包括在形成所述熔丝链之后将所述熔丝链暴露于环境气氛的步骤。
7.一种电子结构,包括:
第一电介质层,其具有填充以第一自钝化导电材料的至少两个通孔;
熔丝链,其在所述第一电介质层上,所述熔丝链电连接所述两个通孔且包括具有暴露于激光束之后改变其电阻这一特性的第二材料;及
两个台,其在所述熔丝链之上且在所述两个通孔正上方,所述两个台每个包括第三自钝化导电材料。
8.如权利要求7所述的电子结构,还包括第二电介质层,其在所述熔丝链之上且在所述两个台之下,但不完全覆盖所述熔丝链。
9.如权利要求7所述的电子结构,其中所述第二材料包括选自含有TaN、TiN和WN的组的物质。
10.如权利要求7所述的电子结构,其中所述第一自钝化导电材料包括选自含有Al和W的组的物质。
11.如权利要求7所述的电子结构,其中所述第三自钝化导电材料包括选自含有Al和W的组的物质。
12.一种用于编程激光熔丝的方法,该激光熔丝具有熔丝链,该熔丝链包括具有暴露于激光束之后改变其电阻这一特性的材料,该方法包括步骤:
提供所述熔丝链;及
将激光束导向所述熔丝链,控制所述激光束从而所述熔丝链的电阻响应于所述激光束对所述熔丝链的影响而改变,但所述熔丝链不熔断。
13.如权利要求12所述的方法,还包括检测所述熔丝链的电阻变化并将所述电阻变化转换成数字信号的步骤。
14.如权利要求12所述的方法,其中所述材料具有暴露于激光束之后增加其电阻这一特性。
15.如权利要求12所述的方法,其中所述材料具有暴露于激光束之后降低其电阻这一特性。
16.如权利要求12所述的方法,其中所述材料是自钝化的。
17.如权利要求12所述的方法,其中所述材料包括选自含有TaN、TiN和WN的组的物质。
18.一种电子结构,包括:
第一电介质层,其具有至少第一通孔和第二通孔,两者都被填充以第一导电材料;
第一吸氧剂屏蔽件和第二吸氧剂屏蔽件,其分别位于所述第一和第二通孔中的所述第一导电材料正上方且与其物理接触,所述第一和第二吸氧剂屏蔽件包括第二导电吸氧剂材料;及
熔丝链,其电连接所述第一和第二吸氧剂屏蔽件,所述熔丝链包括具有暴露于激光束之后改变其电阻这一特性的第三材料。
19.如权利要求18所述的电子结构,还包括分别位于所述第一和第二吸氧剂屏蔽件正上方且与其物理接触的第一台和第二台,所述第一和第二台包括第四导电材料。
20.如权利要求18所述的电子结构,其中所述第二导电吸氧剂材料包括钛。
CNB2004800321736A 2003-11-04 2004-11-04 电子结构及其形成方法 Active CN100499130C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/605,885 US7064409B2 (en) 2003-11-04 2003-11-04 Structure and programming of laser fuse
US10/605,885 2003-11-04

Publications (2)

Publication Number Publication Date
CN1875485A true CN1875485A (zh) 2006-12-06
CN100499130C CN100499130C (zh) 2009-06-10

Family

ID=34549682

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800321736A Active CN100499130C (zh) 2003-11-04 2004-11-04 电子结构及其形成方法

Country Status (6)

Country Link
US (3) US7064409B2 (zh)
EP (1) EP1687851B1 (zh)
JP (1) JP4871132B2 (zh)
KR (1) KR100754317B1 (zh)
CN (1) CN100499130C (zh)
WO (1) WO2005048304A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054816B (zh) * 2009-11-03 2012-05-30 中芯国际集成电路制造(上海)有限公司 熔丝的熔断方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9652637B2 (en) 2005-05-23 2017-05-16 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for allowing no code download in a code download scheme
US7381981B2 (en) * 2005-07-29 2008-06-03 International Business Machines Corporation Phase-change TaN resistor based triple-state/multi-state read only memory
US7768815B2 (en) * 2005-08-23 2010-08-03 International Business Machines Corporation Optoelectronic memory devices
US7701035B2 (en) * 2005-11-30 2010-04-20 International Business Machines Corporation Laser fuse structures for high power applications
US9904809B2 (en) 2006-02-27 2018-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for multi-level security initialization and configuration
US20070290715A1 (en) * 2006-06-19 2007-12-20 David Baer Method And System For Using One-Time Programmable (OTP) Read-Only Memory (ROM) To Configure Chip Usage Features
US9489318B2 (en) 2006-06-19 2016-11-08 Broadcom Corporation Method and system for accessing protected memory
DE102006043484B4 (de) * 2006-09-15 2019-11-28 Infineon Technologies Ag Fuse-Struktur und Verfahren zum Herstellen derselben
US20080308901A1 (en) * 2007-06-12 2008-12-18 Broadcom Corporation Integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof
KR20090102555A (ko) * 2008-03-26 2009-09-30 삼성전자주식회사 전기적 퓨즈 소자 및 그 동작방법
US9263384B2 (en) * 2008-05-13 2016-02-16 Infineon Technologies Ag Programmable devices and methods of manufacture thereof
JP2010118427A (ja) * 2008-11-12 2010-05-27 Nec Electronics Corp 半導体装置および半導体装置の製造方法
US8659118B2 (en) * 2011-07-29 2014-02-25 Infineon Technologies Ag Semiconductor device comprising a fuse structure and a method for manufacturing such semiconductor device
US8946000B2 (en) * 2013-02-22 2015-02-03 Freescale Semiconductor, Inc. Method for forming an integrated circuit having a programmable fuse
US10692811B1 (en) * 2018-12-02 2020-06-23 Nanya Technology Corporation Semiconductor structure
US11152568B2 (en) 2019-06-27 2021-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Top-electrode barrier layer for RRAM
US11469178B2 (en) 2020-12-18 2022-10-11 Globalfoundries U.S. Inc. Metal-free fuse structures

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084835A (ja) * 1983-10-17 1985-05-14 Hitachi Ltd ヒユ−ズ処理方法
JP3325714B2 (ja) * 1994-02-21 2002-09-17 株式会社リコー 半導体装置及び半導体装置の製造方法
JP3353520B2 (ja) * 1995-02-27 2002-12-03 ソニー株式会社 半導体装置
JPH08321549A (ja) * 1995-05-24 1996-12-03 Matsushita Electron Corp 半導体装置
JPH1027797A (ja) * 1996-07-10 1998-01-27 Oki Electric Ind Co Ltd Al/Ti積層配線およびその形成方法
KR100241061B1 (ko) * 1997-07-26 2000-02-01 윤종용 반도체장치의퓨즈제조방법및퓨즈를가진반도체장치
US6033939A (en) 1998-04-21 2000-03-07 International Business Machines Corporation Method for providing electrically fusible links in copper interconnection
DE19901540A1 (de) * 1999-01-16 2000-07-20 Philips Corp Intellectual Pty Verfahren zur Feinabstimmung eines passiven, elektronischen Bauelementes
US6348742B1 (en) 1999-01-25 2002-02-19 Clear Logic, Inc. Sacrificial bond pads for laser configured integrated circuits
US6423582B1 (en) 1999-02-25 2002-07-23 Micron Technology, Inc. Use of DAR coating to modulate the efficiency of laser fuse blows
US6249038B1 (en) * 1999-06-04 2001-06-19 International Business Machines Corporation Method and structure for a semiconductor fuse
US6444544B1 (en) * 2000-08-01 2002-09-03 Taiwan Semiconductor Manufacturing Company Method of forming an aluminum protection guard structure for a copper metal structure
US7087975B2 (en) * 2000-12-28 2006-08-08 Infineon Technologies Ag Area efficient stacking of antifuses in semiconductor device
US20030025177A1 (en) 2001-08-03 2003-02-06 Chandrasekharan Kothandaraman Optically and electrically programmable silicided polysilicon fuse device
US6495426B1 (en) 2001-08-09 2002-12-17 Lsi Logic Corporation Method for simultaneous formation of integrated capacitor and fuse
JP2003068856A (ja) * 2001-08-27 2003-03-07 Seiko Epson Corp ヒューズ素子、半導体装置及びその製造方法
US6873027B2 (en) 2001-10-26 2005-03-29 International Business Machines Corporation Encapsulated energy-dissipative fuse for integrated circuits and method of making the same
DE10156830B4 (de) 2001-11-20 2005-05-12 Infineon Technologies Ag Integrierte Schaltung mit einem programmierbaren Element und Verfahren zu ihrem Betrieb
TW511246B (en) * 2001-12-28 2002-11-21 Nanya Technology Corp Fuse structure
KR100463047B1 (ko) * 2002-03-11 2004-12-23 삼성전자주식회사 반도체 장치의 퓨즈 박스 및 그 제조방법
US6667534B1 (en) * 2002-07-19 2003-12-23 United Microelectronics Corp. Copper fuse structure and method for manufacturing the same
JP4127678B2 (ja) * 2004-02-27 2008-07-30 株式会社東芝 半導体装置及びそのプログラミング方法
US6970394B2 (en) * 2004-04-22 2005-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Programming method for electrical fuse cell and circuit thereof
US7381594B2 (en) * 2005-11-30 2008-06-03 International Business Machines Corporation CMOS compatible shallow-trench efuse structure and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054816B (zh) * 2009-11-03 2012-05-30 中芯国际集成电路制造(上海)有限公司 熔丝的熔断方法

Also Published As

Publication number Publication date
US7384824B2 (en) 2008-06-10
WO2005048304A2 (en) 2005-05-26
EP1687851A4 (en) 2011-02-23
JP4871132B2 (ja) 2012-02-08
WO2005048304A3 (en) 2005-07-28
US7981732B2 (en) 2011-07-19
US20050093091A1 (en) 2005-05-05
CN100499130C (zh) 2009-06-10
JP2007515057A (ja) 2007-06-07
KR20060115736A (ko) 2006-11-09
US7064409B2 (en) 2006-06-20
EP1687851B1 (en) 2013-08-07
KR100754317B1 (ko) 2007-09-03
US20080194064A1 (en) 2008-08-14
US20060145291A1 (en) 2006-07-06
EP1687851A2 (en) 2006-08-09

Similar Documents

Publication Publication Date Title
US7981732B2 (en) Programming of laser fuse
US6124194A (en) Method of fabrication of anti-fuse integrated with dual damascene process
US7479447B2 (en) Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses
US20060163734A1 (en) Fuse structure and method for making the same
KR100390691B1 (ko) 방사 흡수 도전체
US7659601B2 (en) Semiconductor device having moisture-proof dam and method of fabricating the same
US6518643B2 (en) Tri-layer dielectric fuse cap for laser deletion
KR100528743B1 (ko) 집적 회로 구조체 및 집적 회로 구조체를 마련하는 공정
US7704804B2 (en) Method of forming a crack stop laser fuse with fixed passivation layer coverage
US7449764B2 (en) Semiconductor device and method of manufacturing the same
US20060118963A1 (en) Semiconductor device and fabrication method for the same
US6750129B2 (en) Process for forming fusible links
EP0735583B1 (en) Process of trimming a fuse in an integrated circuit
US7811866B2 (en) Single passivation layer scheme for forming a fuse
US20110001212A1 (en) Fuse of semiconductor device and method for fabricating the same
KR20070097764A (ko) 반도체 장치의 퓨즈 구조물 형성 방법
US7888770B2 (en) Fuse box for semiconductor device and method of forming same
US6306746B1 (en) Backend process for fuse link opening
KR100871389B1 (ko) 반도체 소자의 퓨즈 및 그의 형성방법
CN113394193B (zh) 半导体结构及其形成方法、激光熔丝的熔断方法
US20050205965A1 (en) Semiconductor device having a fuse including an aluminum layer
US7943459B2 (en) Semiconductor device and method of manufacturing the semiconductor device
US20090302418A1 (en) Fuse structure of a semiconductor device
KR20070041113A (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20171204

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171204

Address after: American New York

Patentee after: Core USA second LLC

Address before: New York grams of Armand

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20210407

Address after: Hsinchu City, Taiwan, China

Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd.

Address before: Grand Cayman Islands

Patentee before: GLOBALFOUNDRIES INC.