CN1841736A - 集成半导体电感器及其方法 - Google Patents
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Abstract
在一个实施例中,覆盖半导体衬底形成多层电感器。
Description
技术领域
本发明通常涉及电子设备,更具体地,涉及形成半导体器件和结构的方法。
背景技术
过去,半导体工业中采用各种方法和结构来将滤波器集成到单片半导体器件上。典型地,这些滤波器仅局限于简单的包括阻性和容性元件的pi型滤波器,或者在某些情况下是包括感性和无源元件的pi型滤波器。pi型滤波器的一个例子是Phoenix Arizona的5005 East McDowell Road的ONSemiconductor销售的NUF6106。pi型滤波器通常在高于滤波器的截止频率上不能提供足够的衰减。包括有电感器的滤波器典型地是具有与pi型滤波器串联耦合的串联电感器的pi型滤波器。在公开号为US2003/0228848的美国专利申请中公开了这种滤波器的一个例子。感性滤波器典型地在高于滤波器截止频率的频率上具有过多的损耗(典型地称作插入损耗),并且通常具有所不希望有的群延迟失真。
因此,希望将滤波器集成到单片半导体器件上,其具有较低的群延迟失真,在低于截止频率处具有较低的插入损耗,并且在高于截止频率处具有较高的损耗。
附图说明
图1说明了根据本发明集成到半导体器件上的滤波器的实施例一部分的放大平面图;
图2示意性地说明了表示根据本发明的图1中所示的滤波器的电路的实施例的一部分;
图3说明了根据本发明的图1中所示的滤波器的一部分的分解图;
图4说明了根据本发明的图1中所示的滤波器的一部分的放大了的横截面图;和
图5说明了根据本发明的图1中所示的滤波器的另一部分的放大了的横截面图。
为了使说明简洁清楚,图中的各元件都不需要按比例绘制,并且在不同的图中相同的附图标记表示相同的元件。另外,为了使描述简洁,省略了公知的步骤和元件的描述和细节。如本文中所用到的,载流电极表示器件中传输流过该器件的电流的元件,如MOS晶体管的源极或漏极、或者双极晶体管的发射极或集电极、或者二极管的阴极或阳极,控制电极表示器件中控制流过该器件的电流的元件,如MOS晶体管的栅极或者双极晶体管的基极。尽管本文中将器件解释为特定的N沟道或P沟道器件,但本领域的普通技术人员应认识到,根据本发明也可以是互补型的器件。为了使附图清楚,所说明的器件结构中的掺杂区通常具有直线边缘和角度精确的拐角。但是,本领域的技术人员应理解,由于掺杂物的扩散和活动,掺杂区的边缘通常并不是直线,并且拐角的角度也不是很精确。
具体实施方式
图1示意性地说明了半导体器件10的实施例的一部分的放大了的平面图,该半导体器件10包括集成到半导体衬底37上的五阶贝赛尔滤波器20。采用通常的方式用箭头指示出该滤波器20。如下文中将进一步看到的,滤波器20的各元件有利于形成谐振结构。滤波器20包括用作滤波器20的电感器的第一堆叠的或多层电感器11和第二堆叠的或多层电感器12。如本领域的技术人员将理解的,集成的半导体电感器如电感器11或电感器12或它们的组合可以被用来形成除了五阶贝赛尔滤波器的滤波器20以外的其它类型的滤波器,包括有带通滤波器、Chebyschev滤波器和椭圆滤波器。滤波器20还包括第一暂态电压抑制器件(TVS)75、第一电容器70、第二暂态电压抑制器件(TVS)76、第二电容器71和第三暂态电压抑制器件(TVS)77。
图2示意性地说明了表示图1中所示的滤波器20的电路45的实施例的一部分。该描述既参考图1也参考图2。电感器11与电容器70并联耦合,以在衬底37上形成第一谐振电路。电感器12与电容器71并联耦合,以在衬垫37上形成第二谐振电路。TVS 75连接在电感器11的第一端子26和公共返回端子79之间。TVS 75由虚线表示的部分起到滤波器20的第三电容器的功能。TVS 76连接在端子79和电感器11的第二端子27与电感器12的第一端子29的公共连接点之间。TVS 76由虚线表示的部分起到滤波器20的第四电容器的功能。TVS 77连接在电感器12的第二端子28和端子79之间,由虚线表示的部分起到滤波器20的第五电容器的功能。本领域的技术人员理解的是,TVS75、76和77也可以提供对可以连接到滤波器20的其它元件或电路的静电放电保护。
图3说明了图1中所示的电感器11和12的一部分的放大了的分解图。
图4用常用的方式说明了电感器11的一部分的放大了的横截面图。通过切开电感器11的腿30、31、32、33和34来说明其横截面。该描述参考了图1、图2、图3和图4。所形成的电感器11包括第一电感器元件14和第二电感器元件13。所形成的第一电感器元件14覆盖在衬底37的表面的第一部分的上面,所形成的第二电感器元件13覆盖在元件14的上面。所形成的元件14的结构提供了在元件14的相邻部分之间的电磁耦合,用以使元件14的电感量大于直线导体的电感量。以相同的构图在元件14的上面形成元件13,使得元件13的结构提供了元件13相邻部分之间的电磁耦合,用以使元件13的电感量大于直线导体的电感量。这样,元件13和14彼此磁耦合。另外,元件14和13的构图和覆盖地接近没置提供了元件13和14之间的电磁耦合,这样使得元件13和14形成的用于电感器11的电感量大于单独的元件13的电感量加上单独的元件14的电感量之和。典型地,元件14的相邻部分大约间隔1到6(1-6)微米,元件13的相邻部分大约间隔2到10(2-10)微米。典型地,为了确保在元件13和14之间足够的耦合,元件13与元件14大约间隔0.5到2(0.5-2)微米。为了提供元件13和14之间的电连接,元件13的一个末端或端部在节点16电连接到元件14的一个末端或端部。元件14的第二端部起到电感器11的端子26的作用,元件13的第二端部起到电感器11的端子27的作用。
所形成的电感器12包括第一电感器元件22和第二电感器元件21。所形成的第一电感器元件22覆盖在衬底37的表面的第二部分的上面,所形成的第二电感器元件21覆盖在元件22的上面。所形成的元件22的构图提供了在元件22的相邻部分之间的电磁耦合,用以使元件22的电感量大于直线导体的电感量。以相同的构图在元件22的上面形成元件21,使得元件21的结构提供了元件21相邻部分之间的电磁耦合,用以使元件21的电感量大于直线导体的电感量。另外,元件22和21的构图和覆盖地接近设置提供了元件22和21之间的电磁耦合,这样使得元件22和21形成的用于电感器12的电感量大于单独的元件21的电感量加上单独的元件22的电感量之和。为了提供元件22和21之间的电连接,元件21的一个末端或端部在节点23电连接到元件22的一个末端或端部。元件22的第二端部起到电感器12的端子28的作用,元件21的第二端部起到电感器12的端子29的作用。
在优选的实施例中,元件13和14形成正方形的螺旋形形状。但是,元件13和14的每一个都可以形成在元件13的相邻部分之间、元件14的相邻部分之间以及元件13和14之间提供相互的磁通耦合的其它形状。例如,元件13和14可以形成圆形的螺旋形、或拉长的螺旋形、或提供磁通耦合的任意一种公知的形状。在该优选实施例中,元件14起始于节点16,在衬底37表面的上方以逆时针方向延伸,直到终止于端子26。元件13起始于节点16,在元件14的具有与元件13的对应部分基本上相同半径的那部分的上面以顺时针方向延伸,并直到终止于端子27。以与电感器11相同的方式形成电感器12。元件22起始于节点23,在衬底37表面的上方以顺时针方向延伸,最终终止于端子28。元件21起始于节点23,在元件22类似部分的上面以逆时针方向延伸,并最终终止于端子29。图2中的分解图帮助说明元件13和14之间以及元件21和22之间的覆盖关系。
参考图1和图4,元件14典型地包括导体41和覆盖电介质39。元件13典型地包括导体42和覆盖电介质40。典型地,为了使串联阻抗最小,导体41和42是由具有低阻抗的导体材料形成的,如金属。典型地,用于导体41和42的材料的电阻率不大于每厘米大约4到5(4-5)微欧姆。典型地,所形成的元件13和14覆盖在衬底37的第一部分的上面。为了使电感器11与衬底37电隔离,电介质38典型地形成在衬底37的表面上。导体41以元件14所希望的图案形成在电介质38的表面上。例如,可以对电介质38进行掩模并形成图案,以暴露电介质38中要形成导体41的部分。其后,形成覆盖导体41的电介质39。电介质39可以不形成在导体41中形成节点16的那部分的上面。导体42形成在覆盖了导体41顶部表面的电介质39的表面上。导体42也形成在形成有节点16的导体41表面上。典型地,提供电介质40用以覆盖导体42以使导体42与器件10的其它元件电隔离。
以与电感器11相同的方式形成电感器12。元件22包括与导体41相似的导体和与电介质39相似的覆盖电介质。元件21包括与导体42相似的导体和与电介质40相似的覆盖电介质。以与节点16相似的方式形成节点23。
应注意,为了说明图1和图2中的元件13、14、21和22,为描述清楚,在图1和图2中没有示出可能会使位于下面的元件14和22不清楚的电介质层40的边缘。
参考图1和图5,TVS 75、TVS 76和TVS 77形成在衬底37的表面上。典型地,TVS 75、TVS 76和TVS 77的每个都是通过在衬底37的表面上形成第一掺杂区46而形成的。为了形成用于每个TVS 75、76和77的接触区域,在掺杂区46的内部形成第二掺杂区47。电介质38可以在区域46和47之前形成,或者可以在形成区域46和47之后形成。提供导体49以形成与区域47的电接触。TVS 75和77的导体49典型地是跨电介质38延伸,用以与各自的电感器11和12中各自的端子26和28进行电接触。电感器11的导体42和电感器12的对应的导体可以延伸成与TVS 76的导体49进行电接触,从而将端子27和29连接到TVS 76。本领域的技术人员将认识到,衬底37起到图2中的端子79的作用。
电容器70和71可以是覆盖在衬底37表面上的平面电容器,或者可以是在衬底37的表面上形成的金属氧化物半导体(MOS)电容器,或者可以被形成为沟槽式电容器或其它公知的电容器结构。图5用通常的方式说明了作为电容器70的平面电容器和作为电容器71的MOS电容器。电容器71包括形成在衬底37表面上的掺杂区55。掺杂区56和掺杂区57形成在区域55的内部,用以作为形成电容器71的MOS晶体管的源极和漏极。电介质38可以形成MOS晶体管的栅极绝缘体,或者不同的绝缘体可以被形成作为栅极绝缘体。为了形成电容器71的栅极导体,栅极材料60典型地形成在区域55的上面并设置在区域56和57之间。通常绕材料60形成电介质58,用以使材料60与其它元件绝缘。可以形成导体63用以与区域56和57进行电接触。导体63也可以跨电介质38延伸,以与TVS 76的导体49进行电接触。通常形成导体64以在材料60和TVS 77的导体49之间进行电接触。如本领域中所公知的,导体63形成电容器71的一个端子,导体64形成电容器64的第二端子。可以给电介质38提供导体51,用以形成与TVS 75的导体49的电连接,并作为电容器70的一个极板。可以给导体51的一部分提供电介质52,用以形成电容器70的电介质,并且可以提供另一个导体53,用以放置在电介质52的至少一部分的下面,以形成电容器70的第二极板,并跨电介质38横向延伸,以与TVS76的导体49进行电接触。在图2的电路45中说明了导体51、53、63和64。
参考图2,在滤波器20的输入端65接收信号,在输出端66形成滤波后的输出信号。可以相信,滤波器20的插入损耗减少了大约10分贝(10db),群延迟失真减小了大约百分之50(50%)。还可以相信,在其它的滤波器结构中利用如电感器11或12的集成电感器也会改善插入损耗和群延迟失真。
鉴于上面所有内容,很明显公开了一种新的器件和方法。在其它的特征中所包括的是在半导体衬底上形成多层电感器。该多层电感器便于形成与电感器并联的电容器,并在半导体衬底上形成谐振电路。该多层电感器在半导体管芯的给定区域内提供了更大的电感量,从而降低了成本。另外,可以连同多层电感器一起在衬底37上形成其它电路元件。
尽管参考特定的优选实施例描述了本发明,但很明显的是,许多替换方式和变化对于半导体领域的技术人员来说都将是很显然的。例如,电感器11或12可以被用作独立电感器而不是用在滤波器电路中,可以改变滤波器20的级数以及各级的结构,从而形成其它类型的滤波器。另外,为描述清楚,全文中都使用词语“连接”,但是,其倾向于具有与词语“耦合”相同的含义。因此,“连接”应被解释为包括直接连接或间接连接。
Claims (10)
1、一种集成半导体电感器,包括:
半导体衬底;
覆盖半导体衬底至少一部分的第一多层电感器,该第一多层电感器具有第一端子和第二端子,该第一多层电感器还具有覆盖半导体衬底该部分的第一导体、覆盖第一导体的至少一部分的第二导体、设置在第一导体和第二导体之间的第一电介质。
2、权利要求1的集成半导体电感器,其中,第一多层电感器的电阻率不大于约每厘米5微欧姆。
3、权利要求1的集成半导体电感器,进一步包括延伸通过第一电介质的第一连接,用以形成第一导体和第二导体之间的电接触。
4、权利要求1的集成半导体电感器,其中,第一导体和第二导体是金属导体。
5、权利要求1的集成半导体电感器,进一步包括与第一多层电感器并联耦合的第一电容器,该第一电容器具有第一端子和第二端子,第一电容器的第一端子耦合到第一多层电感器的第一端子,第一电容器的第二端子耦合到第一多层电感器的第二端子。
6、权利要求5的集成半导体电感器,进一步包括第二电容器,该第二电容器具有耦合到第一多层电感器的第二端子的第一端子,其中,第二电容器是暂态电压抑制器。
7、一种形成集成半导体电感器的方法,包括:
提供半导体衬底;
形成覆盖半导体衬底的至少一部分的第一电感器元件;和
形成覆盖第一电感器元件的至少一部分的第二电感器元件,其中,第一电感器元件磁耦合到第二电感器元件,并且其中,第一电感器元件和第二电感器元件在相反方向上延伸。
8、权利要求7的方法,进一步包括与第一电感器元件和第二电感器元件并联耦合的电容器。
9、一种集成半导体滤波器,包括:
覆盖半导体衬底的表面的第一部分的第一多层电感器,该第一多层电感器包括覆盖半导体衬底在第一方向上延伸的第一电感器元件和覆盖第一电感器元件在不同的方向上延伸的第二电感器元件;和
与第一电感器串联耦合的第一电容器。
10、权利要求9的集成半导体滤波器,进一步包括以旁路结构形式与第一电感器耦合的第二电容器。
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