CN1822367A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1822367A
CN1822367A CNA2006100070692A CN200610007069A CN1822367A CN 1822367 A CN1822367 A CN 1822367A CN A2006100070692 A CNA2006100070692 A CN A2006100070692A CN 200610007069 A CN200610007069 A CN 200610007069A CN 1822367 A CN1822367 A CN 1822367A
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CN
China
Prior art keywords
electrode
semiconductor device
source electrode
interconnection
metal
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Pending
Application number
CNA2006100070692A
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English (en)
Inventor
高津纪男
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NEC Electronics Corp
NEC Corp
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NEC Corp
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Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1822367A publication Critical patent/CN1822367A/zh
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract

能够简化具有表面电极的半导体器件的结构。在半导体器件(100)中,可焊接的金属Cu被用于栅电极(101)和源电极(104)。因此,与传统技术不同,没有必要在栅电极的上部上和源电极的上部上单独地形成附加的可焊接的金属层。

Description

半导体器件
本申请基于日本专利申请No.2005-36,697,其内容在此参考引进。
技术领域
本发明涉及一种包括表面电极的半导体器件。
背景技术
在传统技术中,当半导体器件的表面电极用焊料连接到外部接线端时,需要通过光刻技术在铝电极上形成由两层或三层组成的阻挡金属,目的是获得与焊料的粘附性和获得可靠性,因此引发了与生产成本相关的问题。
因而,通过化学镀工艺来形成与铝电极有比较好粘附性的金属,如锌,钛,铬,钯等,然后,在其上形成镍(Ni)或铜(Cu)作为焊料的阻挡物,此外,通过化学镀工艺,形成用于防止Ni和Cu的氧化的金属,如Au等,然后,通过丝网印刷工艺形成焊料凸点,由此完成了具有焊料凸点的半导体器件的制造(日本专利特开No.H06-140,409(1994))。
如日本专利特开No.H06-140,409中所述的半导体器件中,由于用于传统半导体器件的互连的铝互连具有可焊性的问题,所以为了确保可焊性和提供较小的可靠性降低,在铝互连上提供附加的金属层,其中这种可靠性降低是由半导体器件的铝电极或焊料的逆扩散引起的。
在另一方面中,在传统的技术中,通常经由金属层(阻挡层)在上述的铝电极上形成焊料凸点。相反,在现代半导体器件中,正在向使用铜互连转变,相应地,如在日本专利特开No.H11-340,265(1999)和日本专利特开No.2002-110,799描述的半导体器件中,提出了一种适用于铜互连的结构,如在铜互连上形成粘附层(铝(Al)、钛(Ti)、铬(Cr)、钴(Co)、镍(Ni)、钼(Mo)、银(Ag)、钽(ta)、钨(W)、金(Au)等),并且进一步在其上形成用于凸点的基底金属的凸点限制金属(BLM)膜。
发明内容
然而,传统技术包括以下问题。参考图3进行如下描述。
半导体器件10包括:在其上部具有器件区的硅衬底9;栅电极1,其经由它和硅衬底9之间的绝缘膜13而位于硅衬底9上;栅互连5,其每一个都位于硅衬底9上从而嵌入在绝缘膜8内;源电极4,其经由它和栅互连5之间的阻挡金属12而位于栅互连5上;以及位于硅衬底9的下表面上的漏电极6。源电极4由铝互连构成。另外,半导体器件10还包括:分别设置在栅电极1上和源电极4上的金属层7;位于金属层7上的抗表面氧化金属3;以及表面保护膜2。金属层7由可焊接的金属如铜(Cu)、镍(Ni)等构成,并且通过镀的工艺等形成。
在半导体器件10中,源电极4由比较不适于焊接的铝互连构成。这样,在该传统结构中为了确保其可焊性,必需单独地在源电极4的上部上形成附加的金属层7,以提供与焊料的接触,该层由可焊接的金属构成并且提供了与铝和焊料的确保的接合可靠性。
根据本发明的一个方面,提供一种半导体器件,包括:包括器件区的半导体衬底;具有预定图形且位于半导体衬底的表面上的互连;为覆盖互连而提供的绝缘薄膜;位于半导体衬底上以填充各互连之间的空隙的第一电极;以及电气地连接互连的第二电极,第一电极被电气地连接到器件区,并且第一电极由可焊接的金属构成。
根据本发明,通过提供由可焊接的金属构成的第一电极可以获得复合功能,而不需要单独地在第一电极上提供可焊接的金属,其中该复合功能是作为形成焊接点的接触和作为电极的功能。因此,能够获得具有第一电极的半导体器件的结构,该结构允许其以简单的工艺制造,同时当用焊料把半导体器件贴装在衬底时,确保焊料与第一电极之间的接合的可靠性。
根据本发明,能够获得如下半导体器件的结构,该结构允许以简单的制造工艺来制造可焊接的且高可靠接合的第一电极。
附图说明
本发明的上述和其他目的,优点和特征通过结合附图的如下描述将变得更清楚,其中:
图1是剖面图,示意性地示出根据实施例的半导体器件;
图2是剖面图,示意性地示出根据实施例的、将半导体器件贴装在印刷电路板上的典型实施方式;以及
图3是剖面图,示意性地示出传统技术的半导体器件。
具体实施方式
现在,将参考示意性的实施例来在此描述本发明。本领域技术人员将认识到,使用本发明的讲解,能够完成多种可选择的实施例,并且本发明并不局限于以说明为目的而示出的实施例。
以下参考附图进一步详细描述根据本发明的优选的实施例。在所有的图中,相同的标号被赋予图中共同地出现的元件,并且将不提供其详细的描述。
图1示出的半导体器件100包括:包括器件区(源区107)的半导体衬底(硅衬底110);形成位于半导体衬底的表面上的预定图形的互连(栅互连105);为覆盖互连而提供的绝缘膜(绝缘膜108);第一电极(源电极104),其作为位于半导体衬底上以填充互连之间的空隙的表面电极;以及电气地连接到互连的第二电极(栅电极101),并且第一电极被电气地连接到器件区。第一电极由可焊接的金属构成,例如,诸如含Cu的金属。
参考图1描述根据本实施例的半导体器件100。
半导体器件100是金属氧化物半导体场效应晶体管(MOSFET),其包括:在其上表面上具有器件区的硅衬底110,其用n型杂质掺杂,并具有漏区的功能;为与硅衬底110的下表面接触而提供的漏电极106;经由其间的栅绝缘膜109位于硅衬底110的一部分上表面上的栅电极101;以及位于硅衬底110上的源电极104。这里,在本实施例中,半导体器件100是分立器件。
源电极104连接到用n型杂质掺杂的源区107,漏电极106连接到具有漏区功能的硅衬底110。用p型杂质掺杂的沟道扩散区111形成在硅衬底110的上表面上。
在硅衬底110和源电极104之间,半导体器件100还包括:绝缘膜108;每个都嵌入在绝缘膜108内的栅互连105;以及位于绝缘膜108上的阻挡金属112。半导体器件100还包括:形成在栅电极101上和源电极104上的金属层103;以及位于硅衬底110上的表面保护膜102。
栅电极101和源电极104由可焊接的金属构成。这里,“可焊接的金属”是指如下金属,例如:其与焊料如无铅焊料具有比较好的连接性,且对焊料具有比较好的抗腐蚀性,并且不包括铝。在本实施例中,采用铜(Cu)作为可焊接的金属。栅电极101和源电极104的厚度优选地可以等于或大于1.5μm,更优选地等于或大于2.5μm。这里,在本实施例中,栅电极101和源电极104的厚度大约是5μm。
在栅互连105形成之后,采用溅射工艺或填充工艺同时地形成栅电极101和源电极104。
由于栅电极101和源电极104由具有较高电导率水平的Cu构成,所以能够降低栅电极101和源电极104的电阻。此外,由于采用Cu,能够抑制应力迁移等的产生,因此提供了半导体器件100的提高的可靠性。
由于栅电极101通过栅绝缘膜109位于硅衬底110上,所以栅电极101没有电气地连接到位于硅衬底110的上表面中的器件区。栅电极101通过适合的接触(未示出)电气地连接到栅互连105。
栅互连105是位于半导体器件100的表面上的顶层互连,并且形成预定图形。在本实施例中,栅互连105由多晶硅构成,并且栅互连105的厚度比栅电极101的厚度小。
如图1所示,源电极104包括:通过阻挡金属112位于绝缘膜108上的各部分和通过阻挡金属112位于硅衬底110上的各部分,其中分别提供绝缘膜108以围绕栅互连105。由于源电极104包括通过阻挡金属112位于硅衬底110上的各部分,所以源电极104电气地连接到源区107,其中源区107是位于硅衬底110之上的器件区。提供源电极104,使其填充多个栅互连105之间产生的空隙。
绝缘膜108由例如SiO2,SiOC等构成,起到提供栅互连105和位于绝缘膜108的外围的阻挡金属112之间的绝缘的作用。
栅绝缘膜109由例如SiO2,SiOC等构成,起到提供栅电极101和硅衬底110之间的绝缘的作用。
在半导体器件100中,扩散阻挡膜(阻挡金属112)位于绝缘膜108的上表面和源电极104之间,以及硅衬底110的上表面的各部分和源电极104之间。
提供源电极104,使得阻挡金属112嵌入其中。
阻挡金属112位于绝缘膜108的上表面和源电极104之间,以及硅衬底110的上表面的各部分和源电极104之间。阻挡金属112由Ti/TiN等构成,起到抑制构成源电极104的Cu的离子扩散的作用。
漏电极106经由贴装材料122(图2)被电气地连接到位于印刷电路板120(图2)中的互连图形(未示出),从而与其下表面接触。
表面保护膜102由聚酰亚胺膜等构成,并且起到保护位于硅衬底110中的器件区的作用。
在半导体器件100中,形成用于抑制源电极104的表面氧化的层(金属层103),使其与源电极104的上表面接触。金属层103起到抑制栅电极101的表面和源电极104的表面氧化的作用,并且在本实施例中,通过借助于化学镀工艺提供Au来形成金属层103。
参考图2将描述把半导体器件100贴装到电路板120的结构。
印刷电路板120包括互连图形132和经由引线128引线键合到栅电极101上的焊盘130。
互连图形132经过铜片126和经由焊料层124电气地连接到源电极104,提供焊料层124是为了与源电极104的上表面接触。
漏电极106被电气地连接到互连图形(未示出),其中互连图形经过导电的贴装材料122位于印刷电路板120的上表面中。
以下描述采用半导体器件100的结构获得的有利效果。
在半导体器件100中,铜(Cu)被用于栅电极101和源电极104,其是能与焊料形成接合的金属。因此,与参考图3描述的传统技术不同,没有必要为了提供接触,在栅电极1和源电极4的上部上单独地形成附加的可焊接金属层。作为表面电极的源电极104显示出作为MOSFET的源电极和作为用于焊接接合的接触的复合功能。因此,与参考图3描述的传统技术相比,可以获得用简单工艺制造的半导体器件100的结构。此外,与参考图3描述的传统技术中的结构相比,由于半导体器件100的结构能被简化,所以能简单地形成焊接接合。另外,栅电极101和源电极104的上表面能被平坦化。因此,与参考图3描述的技术相比,可以得到更大的可焊接面积。因此,可以得到提供栅电极101或源电极104与焊料的接合的更宽的工艺允许度。
在该情况中,Cu被用作栅电极101和源电极104。因此,与传统技术中经常采用铝作为栅电极1和源电极4的情况相比,能够降低栅电极101上和源电极104上的电阻。因此,能够降低整个半导体器件100的电阻。另外,能够降低半导体器件100的功耗。
由于如日本专利特开No.H11-340,265和日本专利特开2002-110,799所述的技术中使用如下传统技术,即传统地采用BLM膜,用于减少焊料凸点的制造波动和保持其可靠性,所以引发了增加工艺时间的问题。相反,根据本实施例的半导体器件100能够通过选择栅电极101和源电极104的足够厚度,来阻止电极材料和焊料的合金到达位于硅衬底110上的器件区,其中合金是在源电极104和焊料层124之间形成焊接接合时产生的,而栅电极101和源电极104的厚度都等于或大于1.5μm。因此,半导体器件100的可靠性能够进一步提高。此外,根据本实施例半导体器件100还能够通过选择栅电极和源电极104的更足够的厚度,来阻止电极材料和焊料的合金到达位于硅衬底110上的器件区,其中栅电极和源电极104的厚度都等于或大于2.5μm。因此,半导体器件100的可靠性能够进一步提高。
此外,由于没有必要提供用于阻止电极材料和焊料的合金到达位于硅衬底110上的器件区的阻挡层,所以能够减少用于制造半导体器件100的必需的工艺操作,从而减少了用于制造半导体器件100的成本。
另外,由于没有必要在栅电极101和源电极104的上部上单独地形成附加的可焊接金属层,所示能够减少用于制造半导体器件100的必需的工艺操作,同时能保持半导体器件100的可靠性,从而减少了用于制造半导体器件100的成本。
尽管已经参照附图在上面描述了本发明的优选实施例,但是应该理解,提出上述公开是为了示意性地说明本发明的目的,并且还能采用除了上述结构之外的多种结构。
例如,上述实施例中描述了采用分立器件的结构用于半导体器件100,但是其它器件,如具有控制电路的功率器件等也可被采用。
另外,尽管上述实施例中描述了具有约5μm的厚度的栅电极101和源电极104的结构,但是也可以选择其它厚度,只要所选择的厚度提供等效于上述实施例的有利效果的有利效果。
另外,尽管上述实施例中描述了包含由Cu构成的栅电极101和源电极104的结构,但是其它种类的可焊接金属,如Cu合金,Ni等也可以被采用。
另外,尽管上述实施例中描述了包含由Au构成的金属层103的结构,但是其它种类的金属也可以被采用,只要该金属能够阻止栅电极101和源电极104的表面的氧化。
显然,本发明不局限于以上实施例,可以在不偏离本发明的范围和精神的情况下进行修改和变化。

Claims (7)

1.一种半导体器件,包括:
包括器件区的半导体衬底;
互连,其具有预定图形且位于所述半导体衬底的表面上;
绝缘膜,用于覆盖所述互连;
第一电极,其位于所述半导体衬底上以填充所述互连之间的空隙;以及
第二电极,其电气地连接到所述互连,
所述第一电极电气地连接到所述器件区,并且所述第一电极由可焊接的金属构成。
2.根据权利要求1所述的半导体器件,
其中源区和漏区位于所述器件区中,
所述第一电极是源电极,
所述第二电极是栅电极,并且
漏电极位于所述半导体衬底的背表面上。
3.根据权利要求1所述的半导体器件,其中扩散阻挡膜位于所述绝缘膜的上表面与所述第一电极之间以及所述半导体衬底的上表面的一部分与所述第一电极之间。
4.根据权利要求1所述的半导体器件,其中所述第一电极由含Cu的金属构成。
5.根据权利要求1所述的半导体器件,
其中形成与所述第一电极的上表面接触的层,所述层能够抑制所述第一电极的表面的氧化。
6.据权利要求3所述的半导体器件,
其中提供所述扩散阻挡膜使其遵循所述绝缘膜的上表面的几何形状,
提供所述第一电极使得所述扩散阻挡膜嵌入在所述第一电极内。
7.根据权利要求2所述的半导体器件,其中所述源电极的厚度等于或大于1.5μm。
CNA2006100070692A 2005-02-14 2006-02-14 半导体器件 Pending CN1822367A (zh)

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