CN1797952A - System and method of ultra sampling high speed time pulse / data recovery - Google Patents
System and method of ultra sampling high speed time pulse / data recovery Download PDFInfo
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- CN1797952A CN1797952A CN 200410103621 CN200410103621A CN1797952A CN 1797952 A CN1797952 A CN 1797952A CN 200410103621 CN200410103621 CN 200410103621 CN 200410103621 A CN200410103621 A CN 200410103621A CN 1797952 A CN1797952 A CN 1797952A
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Abstract
Using three fields of time pulse simply realizes high-speed time pulse / data recovery. Three fields of time pulse are: global internal clock, inverted global internal clock and recovered clock. The global internal clock and inverted global internal clock are in use for synchronizing ultra sampling data. Circuit of whole data recovery is driven by global internal clock. Finally, recovered clock sends out recovered data. Design is based on principle of synchronization data. The invention raises measurability, stability and correctness of ultra sampling high-speed time pulse / data recovery, as well as shortens time needed for realizing circuit.
Description
Technical field
The present invention relates to the System and method for that a kind of oversampling high speed clock pulse/data are replied.
Background technology
In the networking, for the frequency range (Bandwidth) of transmission data be towards at a high speed with tandem connecting technology (serial link technology) cheaply, especially more so with high speed transmission data.Based on this, the technology of oversampling (oversampling) is widely used, and this technology adopts the take a sample data of high-speed transfer of the oversampling clock pulse of plural phase place, replys out clock pulse and data at a high speed by the message of data state switching (transition) phase place.
Preceding case such as No. 20030142773 patent of U.S.'s publication, the renewal that its positive and negative edge variation by phase place (positive or negative) is detected the clock pulse phase place whether, in each clock pulse in the cycle, in case after phase place changes, will be upgraded.In addition, No. 20040022339 patents of preceding case such as U.S.'s publication propose the oversampling circuit that the frequency of pulse signal is exported in reduction.
Face the difficulty of a reality in the circuit that high-speed data is replied, it must the transmission control to data make correct and stable treated in the very short time (several nano-second).No matter above-mentioned is the preceding case of which kind of technology, any concrete solution is not proposed all this difficulty.
This shows that the System and method for that above-mentioned existing oversampling high speed clock pulse/data are replied obviously still has inconvenience and defective, and demands urgently further being improved in structure, method and use.In order to solve the problem that System and method for that oversampling high speed clock pulse/data replys exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the System and method for that above-mentioned existing oversampling high speed clock pulse/data are replied exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, the System and method for of replying in the hope of the oversampling high speed clock pulse of founding a kind of new structure/data, can improve the System and method for that general existing oversampling high speed clock pulse/data are replied, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective of the System and method for existence of existing oversampling high speed clock pulse/data answer, and the System and method for that provides a kind of new oversampling high speed clock pulse/data to reply, technical problem to be solved is being implemented in the actual integrated circuit that circuit that high speed clock pulse/data is replied can be quick and correct, thereby be suitable for practicality more, and have the value on the industry.
The object of the invention to solve the technical problems realizes by the following technical solutions.The system that a kind of oversampling high speed clock pulse/data that propose according to the present invention are replied, it comprises: an analog circuit in order to receiving an extraneous high-speed data, and is that 4*i tandem signal spreads out of with its oversampling; One tandem/converting unit arranged side by side, inside includes an inner overall clock pulse synchronizer, an anti-inner overall clock pulse synchronizer and a transducer at least, by the overall clock pulse synchronizer in this inside with should receive 2*i tandem signal respectively by anti-inner overall clock pulse synchronizer, and be translated into 4*i bus data arranged side by side by this transducer and spread out of; One phase selector receives this bus data arranged side by side, and produces 4*i phase place according to transition (transition) phase place that edge detection is judged high-speed data and select signal; One delayer is in order to the time delay of compensation because of selecting to judge that phase place produced; And a multiplexing data device, by the answer phase place that this phase selector is judged, reply data as high speed and in bus data arranged side by side, select i bit.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The system that aforesaid oversampling high speed clock pulse/data are replied, the preferred values of wherein said i variable value can be optional one in 2,3 and 4.
The system that aforesaid oversampling high speed clock pulse/data are replied, wherein said analog circuit more comprises: a phase latch loop is that its oversampling frequency then is the 1/i of high-speed data in order to 4*i oversampling clock pulse phase place of generation; One data oversampling device is done oversampling with 4*i oversampling clock pulse phase place to the high-speed data of input; And a clock pulse multiplexer, be that the phase place that produces according to phase selector is selected signal and select the answer phase place in 4*i oversampling clock pulse phase place.
The system that aforesaid oversampling high speed clock pulse/data are replied, it possesses at least 3 clock pulses and at least two group time domain transition interfaces.
The system that aforesaid oversampling high speed clock pulse/data are replied, wherein said 3 clock pulses are to be an inner overall clock pulse, an anti-inner overall clock pulse and a recovered clock (CLK-RX), it all is selected from 4*i oversampling clock pulse phase place, and selection principle that should the overall clock pulse in inside be the rise edge (rising edge) of this overall clock pulse in inside must be between phase place 7 and 0, and the rise edge that selection principle that should anti-inner overall clock pulse is must be between phase place 3 and 4.
The system that aforesaid oversampling high speed clock pulse/data are replied, wherein said two groups of time domain transition interfaces then provide following synchronous mode with the time relationship of the overall clock pulse in this inside, this anti-inner overall clock pulse and oversampling clock pulse phase place: the data sync pattern of one first time domain transition interface, with i=2 is example, data by phase place 1,2,3 and 4 oversamplings are at first done Synchronous Processing by the overall clock pulse synchronizer in this inside, are that synchronizer is done Synchronous Processing by this anti-inner overall clock pulse at first by the data of phase place 5,6,7 and 0 oversampling; The data sync pattern of one second time domain transition interface, with i=2 is example, reply phase place and be 4,5,6 and 7 and in via the data of the overall clock pulse synchronizer in this inside institute after synchronously, select the answer data, if reply phase place be 0,1,2 and 3 from via this anti-inner overall clock pulse be synchronizer select the answer data in the data after synchronous; These two kinds of synchronous modes all have the time in half clock pulse cycle that data are done further control and treatment for all data time domain conversions.
The system that aforesaid oversampling high speed clock pulse/data are replied, wherein said transducer is in order to be converted into signal arranged side by side with the tandem signal.
The system that aforesaid oversampling high speed clock pulse/data are replied, wherein said phase selector more comprises: an edge detector is the phase place that changes in order to detecting data; One initial phase judging unit is in order to specify initial phase; One phase comparator is in order to judge the speed relation of phase change; And a phase place selected cell, be according to the phase place that this phase comparator the produces slack-off information that accelerates, judge the phase place of high-speed data with specified initial phase.
The system that aforesaid oversampling high speed clock pulse/data is replied, it more includes an initial phase selected cell, is used for when initial, judges the state of clock pulse phase place.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.According to the method that a kind of oversampling high speed clock pulse/data of the present invention's proposition are replied, it may further comprise the steps: receive a high-speed data; By an analog circuit this high-speed data is carried out oversampling, and 4*i serial data of output; Utilize digital circuit to receive this serial data, and inside includes an inner overall clock pulse synchronizer and an anti-inner overall clock pulse synchronizer at least, the overall clock pulse in inside receive 2*i tandem signal respectively with being somebody's turn to do instead by the overall clock pulse in this inside, and this serial data is converted into bus data output arranged side by side; And judge the clock pulse phase place of high-speed data, and select the answer data of i bit by its information by this bus data arranged side by side.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method that aforesaid oversampling high speed clock pulse/data are replied, the preferred values of wherein said i variable value can be optional one in 2,3 and 4.
The method that aforesaid oversampling high speed clock pulse/data are replied, wherein judge the clock pulse phase place of high-speed data by this bus data arranged side by side, and select the step of the answer data of i bit by this information, it is the mode of utilizing edge detection, detect the position of phase change in the parallel data, and phase place must be continuous accelerates or slack-off ability is done renewal to phase place for 5 times.
The method that aforesaid oversampling high speed clock pulse/data are replied, the wherein said clock pulse phase place of judging high-speed data by this bus data arranged side by side, and select the step of the answer data of i bit by its information, more include the clock pulse multiplexer that this judged result is sent to this analog circuit, make this clock pulse multiplexer select recovered clock.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, the invention relates to the System and method for that a kind of oversampling high speed clock pulse/data are replied, only realize the answer of high speed clock pulse/data in digital circuit with simple three time pulse domains, these three time pulse domains are inner overall clock pulse (global internal clock), anti-inner overall clock pulse (inverted globalinternal clock) and recovered clock (recovered clock).Wherein totally clock pulse and anti-inner overall clock pulse are to be used for synchronous oversampling data, and the circuit of whole answer data is driven by the overall clock pulse in inside, with recovered clock the data of replying is sent at last again.So design is based on the principle of synchronous digital, so System and method for can be used for improving the measurability of oversampling high speed clock pulse/data recovery circuit, stable and correctness and shortening realization required time of circuit.
By technique scheme, the System and method for that oversampling high speed clock pulse of the present invention/data are replied proposes a simple and reliable framework at the use of time pulse domain especially, so that in the integrated circuit that is implemented in reality that the circuit that high speed clock pulse/data are replied can be quick and correct.It has above-mentioned many advantages and practical value, and in like product and method, do not see have similar structural design and method to publish or use and really genus innovation, no matter it all has bigger improvement on product structure, method or function, have large improvement technically, and produced handy and practical effect, and the System and method for that more existing oversampling high speed clock pulse/data are replied has the multinomial effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by a preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a system architecture diagram of the present invention.
Fig. 2 replys the idea schematic diagram of data for the present invention.
Fig. 3 is the schematic diagram of phase selector of the present invention.
Fig. 4 is a phase place judgment mechanism schematic diagram of the present invention.
Fig. 5 is a time pulse domain configuration diagram of the present invention.
Fig. 6 is the time relationship schematic diagram of CLK/CLKB of the present invention and oversampling clock pulse phase place.
11: analog circuit
111: phase latch loop (Phase Locked Loop; PLL)
112: data oversampling device
113: the clock pulse multiplexer
12: tandem/converting unit arranged side by side
121: inner overall clock pulse (global internal clock, CLK) synchronizer
122: anti-inner overall clock pulse (inverted global internal clock, CLKB) synchronizer
123: transducer
13: delayer
14: phase selector
15: the multiplexing data device
141: the edge detection device
142: the initial phase selector
143: phase comparator
144: the phase place selected cell
21: analog circuit
22: digital circuit
23: inner overall clock pulse/anti-inner overall clock pulse (CLK/CLKB) time pulse domain
24: recovered clock (CLK-RX) time pulse domain
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of System and method for, structure, method, step, feature and effect thereof that oversampling high speed clock pulse/data that foundation the present invention is proposed are replied, describe in detail as after.
The system and method that the disclosed oversampling high speed clock pulse according to the present invention/data is replied sees also shown in Figure 1ly, is system architecture diagram of the present invention, and it is described as follows:
As shown in Figure 1, the native system Organization Chart includes at least: analog circuit 11, tandem/converting unit 12 arranged side by side, delayer 13 (delay), phase selector 14 and multiplexing data device 15.
And analog circuit 11 includes: phase latch loop 111 (Phase Locked Loop; PLL), data oversampling device 112, clock pulse multiplexer 113.
Phase latch loop 111 (Phase Locked Loop; PLL) produce 4*i oversampling clock pulse phase place (CLK0, CLK1 ... CLK4*i-1), this oversampling frequency is M/i (wherein M is the frequency of high-speed data, i=2,3,4).
This 4*i oversampling clock pulse phase place of data oversampling device 112 usefulness (CLK0, CLK1 ... CLK4*i-1, i=2,3,4) high-speed data of input is done oversampling and produced the data of 4*i tandem.
Clock pulse multiplexer 113 is selected signal and select the answer phase place in 4*i oversampling clock pulse phase place according to the phase place that phase selector produced.
And tandem/side by side converting unit 12 includes inner overall clock pulse synchronizer 121, anti-inner overall clock pulse synchronizer 122 and transducer 123, from data that data oversampling device is produced at first by inside overall clock pulse synchronizer 121 and anti-inner overall clock pulse synchronizer 122 carry out Synchronous Processing (and its synchronous principle in after do further explain in detail); The overall clock pulse synchronizer in this inside with should anti-inner overall clock pulse synchronizer receive 2*i tandem signal respectively it done Synchronous Processing, be translated into by this transducer again and be resent to delayer 13 behind 4*i the bus data arranged side by side and phase selector 14 is done subsequent treatment.
Phase selector 14 is in order to receiving the bus data arranged side by side of 4*i bit, and produces 4*i phase place selection signal according to transition (transition) phase place that edge detection is judged high-speed data.
13 of delayers are in order to the time delay of compensation because of judging that phase place produced.
The answer phase place that multiplexing data device 15 is judged according to phase selector 14, and from the bus data arranged side by side of 4*i bit, select i bit as replying data.
See also shown in Figure 2, reply the idea schematic diagram of data for the present invention, this replys the basic concepts of data circuit to use explanation, USB2.0 high-speed data with 480MHZ is an example, if get the i value is 2, in the cycle of a 240MHZ, by serial data that oversampling produced at first be converted in the converting unit 12 of the tandem in aforesaid Fig. 1/side by side or 8 bits and column bus.By this, the data message in time domain just is presented in the also column bus of this 8 bit.14 of phase selectors are done phase place according to this bus data arranged side by side after synchronously and are judged.When contiguous bit not simultaneously, promptly represent high-speed data on time domain, to change to some extent, the time point of this change promptly is the clock pulse phase place of high-speed data.So the phase place that data change just is determined into recovered clock.Tentation data is less than changing, and then the phase place of former one-period is as recovered clock.In Fig. 2, the bit 0 of this 8 bit parallel data is different with bit 1, so 1 in phase place is judged to be broken into recovered clock.
Next seeing also shown in Figure 3ly, be the schematic diagram of phase selector of the present invention, wherein is to do further explanation at the internal structure of phase selector 14.
Phase selector 14 includes: edge detection device (edge detector) 141, initial phase judging unit 142, phase comparator 143 and phase place selected cell 144.
Edge detection device 141 is the phase places that change in order to detecting data; Whether the data of being taken a sample by phase place 7 at a last clock pulse must be imported into judgment data and change to some extent in phase place 0.
Initial phase judging unit 142 is in order to specify initial phase, just to specify an initial phase according to the data state switching phase place of the first stroke data.
Phase comparator 143, be with present data state switching phase place and selected phase place of previous clock pulse cycle compare mutually and then produce " soon " (faster), " slowly " (slower) and " stablizing " (steady) three signals come control phase selected cell 144.
" soon " signal means present phase place than next fast of previous phase place, " slowly " signal mean present phase place than previous phase place next slowly, " stablizing " then the present phase place of intention is identical with previous phase place.
Phase place selected cell 144, the phase place that produces according to the phase comparator 143 slack-off information that accelerates, judge the phase place of high-speed data with specified initial phase, the state transition graph of phase place selected cell 144 then as shown in Figure 4, and Fig. 4 is a phase place judgment mechanism schematic diagram of the present invention.
At this is example (that is 8 oversampling clock pulse phase places are arranged) with i=2, this mechanism produces 8 phase places and selects signal, each phase place all has its phase place separately to select signal, because shake (jitter) characteristic of high-speed data, this mechanism have only when detecting that phase place accelerates for continuous at least 5 times or just the clock pulse phase place can being upgraded when slack-off.
When coming in, high-speed data then the phase place of the first stroke data is appointed as initial phase (state 601) at the beginning, then enter stable state (state 602) at next clock pulse, if the next record data then get the hang of 701 when faster, when if continuous 5 secondary data of accumulation accelerate, then enter ' being updated to very fast phase place ' (state 705), if because shake has slack-off or keeps stablely, then state can be toward the rollback one-level in the process that accelerates; In addition on the one hand, after the state 602, when data are slack-off, also there is equal program to take place, must accumulate continuous 5 secondary data slack-off (state 801-805), just can enter ' being updated to ' (state 805) than the slow phase position, if because shake accelerates or keeps stablely, then state is remitted to the rollback one-level in slack-off process; If during ED, each state all can directly enter ' end ' state.
In state 705, if present phase place be j (j=0,1,2 ..., 6) and phase place after then upgrading is j+1; If present phase place is 7, the phase place after then upgrading is 0.
In state 805, if present phase place j (j=1,2 ...., 7), the phase place after then upgrading is j-1; If present phase place is 0, the phase place after then upgrading is 7.
This mechanism only can be replied the high-speed data of data variation.For the data that are 0 or 1 forever, this mechanism also can't be found out the clock pulse phase place of answer.
The above-mentioned judgement that is illustrated as the recovered clock phase place, and with the next selection that illustrates the answer data.
With the high-speed data of 480MHZ and to get the i=2 framework of 8 oversampling clock pulses (that is have) be example, the frequency of its oversampling clock pulse is 240MHZ, therefore must reply two data in a clock pulse cycle, because the recovered clock phase place is the phase place of data transaction, therefore by ' recovered clock phase place+2 ' and ' recovered clock phase place+6 ' data of being taken a sample then are stable data, and the data of these two oversamplings then are selected to the answer data.
Select signal and aforesaid answer data selection principle according to 8 phase places that phase place selected cell 144 is produced, multiplexing data device 15 can be selected 2 bits as replying data in the parallel bus data.
Then see also shown in Figure 5ly again, be time pulse domain configuration diagram of the present invention, this is main real concept of the present invention and characteristic.
Generally the answer of reaching data and clock pulse in the oversampling mode all relates to many phase differences apart from the plural clock pulse phase place that (is less than 1 nano second) slightly.In the digital circuit of this invention, only relate to 3 clock pulses, overall clock pulse CLK (global internal clock), anti-inner overall clock pulse CLKB (inverted global internal clock) and recovered clock CLK-RX (recoveredclock).Wherein CLK is the main clock pulse of whole digital circuit, and only in order to the data of synchronous oversampling, CLK-RX only is used for multiplexing data device 15 data of replying are sent with the clock pulse of CLK-RX CLKB, if with i=2 be example (that is pulse-phase position 0,1,2 sometimes, 3,4,5,6,7 pairs of high-speed datas are done oversampling), two groups of time domain transition interfaces are arranged in the arteries and veins framework at this moment, and first group for being converted to CLK and CLKB from the time domain of oversampling, and second group for to be converted to the CLK-RX time domain from CLK and CLKB time domain.CLK and CLKB are the clock pulse phase places that is selected from 8 oversamplings, and its selection principle is that the rise edge (rising edge) of CLK must be between phase place 7 and 0, and the rise edge of CLKB must be between phase place 3 and 4.Principle according to this, then the relation of oversampling phase place and CLK and CLKB is then shown in the 6th figure.
See also shown in Figure 6ly, be the time relationship schematic diagram of CLK/CLKB of the present invention and oversampling clock pulse phase place, according to this time relation:
Data sync principle for first group of time domain transition interface is, by phase place 1,2, the data of 3,4 oversamplings are at first done Synchronous Processing by CLK, and by phase place 5,6, the data of 7,0 oversamplings are at first done Synchronous Processing by CLKB.
Data sync principle for second group of time domain transition interface is, is 4,5 if reply phase place, in via the CLK institute data after synchronously, select the answer data for 6,7, and if the answer phase place is 0, select the answer data in 1,2,3 data after synchronous via CLKB institute.
With these two synchronous principles, all there is the time in half clock pulse cycle that data are done further control and treatment for all data time domain conversions, so framework also thereby simplify complicated time domain transition interface in the digital circuit thereby makes that the realization of circuit is stable and correct.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (13)
1, the system of a kind of oversampling high speed clock pulse/data answer is characterized in that it comprises:
One analog circuit in order to receiving an extraneous high-speed data, and is that 4*i tandem signal spreads out of with its oversampling;
One tandem/converting unit arranged side by side, inside includes an inner overall clock pulse synchronizer, an anti-inner overall clock pulse synchronizer and a transducer at least, by the overall clock pulse synchronizer in this inside with should receive 2*i tandem signal respectively by anti-inner overall clock pulse synchronizer, and be translated into 4*i bus data arranged side by side by this transducer and spread out of;
One phase selector receives this bus data arranged side by side, and produces 4*i phase place according to transition (transition) phase place that edge detection is judged high-speed data and select signal;
One delayer is in order to the time delay of compensation because of selecting to judge that phase place produced; And
One multiplexing data device by the answer phase place that this phase selector is judged, is replied data and select i bit in bus data arranged side by side as high speed.
2, the system of oversampling high speed clock pulse according to claim 1/data answer is characterized in that the preferred values of wherein said i variable value can be optional one in 2,3 and 4.
3, the system of oversampling high speed clock pulse according to claim 1/data answer is characterized in that wherein said analog circuit more comprises:
One phase latch loop is that its oversampling frequency then is the 1/i of high-speed data in order to 4*i oversampling clock pulse phase place of generation;
One data oversampling device is done oversampling with 4*i oversampling clock pulse phase place to the high-speed data of input; And
One clock pulse multiplexer is that the phase place that produces according to phase selector is selected signal and select the answer phase place in 4*i oversampling clock pulse phase place.
4, the system of oversampling high speed clock pulse according to claim 1/data answer is characterized in that it possesses at least 3 clock pulses and at least two group time domain transition interfaces.
5, the system of oversampling high speed clock pulse according to claim 4/data answer, it is characterized in that wherein said 3 clock pulses are an inner overall clock pulse, an anti-inner overall clock pulse and a recovered clock (CLK-RX), it all is selected from 4*i oversampling clock pulse phase place, and selection principle that should the overall clock pulse in inside be the rise edge (rising edge) of this overall clock pulse in inside must be between phase place 7 and 0, and the rise edge that selection principle that should anti-inner overall clock pulse is must be between phase place 3 and 4.
6, the system of oversampling high speed clock pulse according to claim 4/data answer is characterized in that wherein said two groups of time domain transition interfaces then provide following synchronous mode with the time relationship of the overall clock pulse in this inside, this anti-inner overall clock pulse and oversampling clock pulse phase place:
The data sync pattern of one first time domain transition interface, with i=2 is example, data by phase place 1,2,3 and 4 oversamplings are at first done Synchronous Processing by the overall clock pulse synchronizer in this inside, are that synchronizer is done Synchronous Processing by this anti-inner overall clock pulse at first by the data of phase place 5,6,7 and 0 oversampling;
The data sync pattern of one second time domain transition interface, with i=2 is example, reply phase place and be 4,5,6 and 7 and in via the data of the overall clock pulse synchronizer in this inside institute after synchronously, select the answer data, if reply phase place be 0,1,2 and 3 from via this anti-inner overall clock pulse be synchronizer select the answer data in the data after synchronous;
These two kinds of synchronous modes all have the time in half clock pulse cycle that data are done further control and treatment for all data time domain conversions.
7, the system of oversampling high speed clock pulse according to claim 1/data answer is characterized in that wherein said transducer, in order to the tandem signal is converted into signal arranged side by side.
8, the system of oversampling high speed clock pulse according to claim 1/data answer is characterized in that wherein said phase selector more comprises:
One edge detector is the phase place that changes in order to detecting data;
One initial phase judging unit is in order to specify initial phase;
One phase comparator is in order to judge the speed relation of phase change; And
One phase place selected cell is according to the phase place that this phase comparator the produces slack-off information that accelerates, and judges the phase place of high-speed data with specified initial phase.
9, the system replied of oversampling high speed clock pulse according to claim 8/data is characterized in that it more includes an initial phase selected cell, is used for when initial, judges the state of clock pulse phase place.
10, the method for a kind of oversampling high speed clock pulse/data answer is characterized in that it may further comprise the steps:
Receive a high-speed data;
By an analog circuit this high-speed data is carried out oversampling, and 4*i serial data of output;
Utilize digital circuit to receive this serial data, and inside includes an inner overall clock pulse synchronizer and an anti-inner overall clock pulse synchronizer at least, the overall clock pulse in inside receive 2*i tandem signal respectively with being somebody's turn to do instead by the overall clock pulse in this inside, and this serial data is converted into bus data output arranged side by side; And
Judge the clock pulse phase place of high-speed data by this bus data arranged side by side, and select the answer data of i bit by its information.
11, the method for oversampling high speed clock pulse according to claim 10/data answer is characterized in that the preferred values of wherein said i variable value can be optional one in 2,3 and 4.
12, the method for oversampling high speed clock pulse according to claim 10/data answer, it is characterized in that wherein judging the clock pulse phase place of high-speed data by this bus data arranged side by side, and select the step of the answer data of i bit by this information, it is the mode of utilizing edge detection, detect the position of phase change in the parallel data, and phase place must be continuous accelerates or slack-off ability is done renewal to phase place for 5 times.
13, the method for oversampling high speed clock pulse according to claim 11/data answer, it is characterized in that the wherein said clock pulse phase place of judging high-speed data by this bus data arranged side by side, and select the step of the answer data of i bit by its information, more include the clock pulse multiplexer that this judged result is sent to this analog circuit, make this clock pulse multiplexer select recovered clock.
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| CNB2004101036219A CN100512009C (en) | 2004-12-29 | 2004-12-29 | System and method of ultra sampling high speed time pulse/data recovery |
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| CNB2004101036219A CN100512009C (en) | 2004-12-29 | 2004-12-29 | System and method of ultra sampling high speed time pulse/data recovery |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101743B (en) * | 2006-07-06 | 2010-10-27 | 益士伯电子股份有限公司 | Low-voltage differential signal receiver |
| CN103713254A (en) * | 2012-10-09 | 2014-04-09 | 瑞昱半导体股份有限公司 | Scan clock domain distribution method for integrated circuit |
| CN106549578A (en) * | 2016-12-21 | 2017-03-29 | 湖南国科微电子股份有限公司 | Multi-mode power source managing system |
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2004
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101743B (en) * | 2006-07-06 | 2010-10-27 | 益士伯电子股份有限公司 | Low-voltage differential signal receiver |
| CN103713254A (en) * | 2012-10-09 | 2014-04-09 | 瑞昱半导体股份有限公司 | Scan clock domain distribution method for integrated circuit |
| CN103713254B (en) * | 2012-10-09 | 2016-08-10 | 瑞昱半导体股份有限公司 | IC scanning time pulse domain distribution method |
| CN106549578A (en) * | 2016-12-21 | 2017-03-29 | 湖南国科微电子股份有限公司 | Multi-mode power source managing system |
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| CN100512009C (en) | 2009-07-08 |
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