CN103713254A - Scan clock domain distribution method for integrated circuit - Google Patents
Scan clock domain distribution method for integrated circuit Download PDFInfo
- Publication number
- CN103713254A CN103713254A CN201210380386.4A CN201210380386A CN103713254A CN 103713254 A CN103713254 A CN 103713254A CN 201210380386 A CN201210380386 A CN 201210380386A CN 103713254 A CN103713254 A CN 103713254A
- Authority
- CN
- China
- Prior art keywords
- time pulse
- domain
- pulse domain
- domains
- function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a scan clock domain distribution method for an integrated circuit. The method comprises the following steps: using a circuit design file and a sequential restriction file of the integrated circuit to find out the number of the interlaced paths of the two function clock domains in multiple function clock domains of the integrated circuit so as to generate a clock domain reporting file; and according to the clock domain reporting file, grouping the multiple function clock domains for distributing to multiple scan clock domains.
Description
Technical field
The machine readable media that the present invention is relevant to one scan time pulse domain distribution method and uses this scanning time pulse domain distribution method, the espespecially a kind of scanning time pulse domain distribution method of an integrated circuit and relevant machine readable media of determining.
Background technology
Sweep test pattern (scan test pattern) is applied on testing integrated circuits widely, sweep test pattern must collocation scan clock pulse (scan clock) to test on automatic test machine platform, and the quantity of scanning clock pulse is often limited to stitch (pin) number of limited chip port or automatic test machine platform.Therefore, different function time pulse domain (function clock domain) often needs to merge to share one scan clock pulse when the scan testing mode, utilize this scanning clock pulse to replace original more than one function clock pulse, become a new scanning time pulse domain (scan clock domain), yet, instantaneous power consumes excessively when avoiding testing, and can use a plurality of scanning clock pulse frameworks and its phase place that staggers.But, when between two function time pulse domains being asynchronous relation or thering are a large amount of false paths (false path), this two functions time pulse domain is carried out to merging meeting and under scan testing mode, increase many timing conflicts (timing violation), cause the degree of difficulty of Clock Tree synthetic (clock tree synthesis), and then cause the increase of area and power.
Therefore, have to traditionally re-start the distribution of scanning time pulse domain after Clock Tree is synthetic, the iteration correction of process several times is to obtain preferably result, or be a large amount of chip areas of increase and manpower time to solve timing conflict, such process has expended a large amount of quality time and the resource of chip development, therefore, provide a mechanism to scan more a plurality of function time pulse domains merged and to be assigned to limited the problem that time pulse domain has become solution that field is needed badly for this reason.
Summary of the invention
Therefore, one of object of the present invention is to provide a kind of more efficient IC scanning time pulse domain distribution method and relevant machine readable media.
According to one first embodiment of the present invention, it discloses a kind of method that determines the one scan time pulse domain distribution of an integrated circuit.The method includes: the quantity of the zigzag path in a plurality of function time pulse domains of finding out this integrated circuit with a circuit design file and the sequential restriction file of this integrated circuit between two function time pulse domains, to produce a time pulse domain report file; And according to this time pulse domain report file, the plurality of function time pulse domain is divided into groups and distribute to a plurality of scanning time pulse domains.
According to one second embodiment of the present invention, it proposes a kind of machine readable media, store a source code, when this source code can be carried out following steps by a processor when performed: the quantity of the zigzag path in a plurality of function time pulse domains of finding out this integrated circuit with a circuit design file and the sequential restriction file of this integrated circuit between two function time pulse domains, to produce a time pulse domain report file; And according to this time pulse domain report file, the plurality of function time pulse domain is divided into groups and distribute to a plurality of scanning time pulse domains.
The embodiment that discloses of invention utilizes the zigzag path between the function time pulse domain of integrated circuit to scan the distribution of time pulse domain, that is provide and can and be assigned to limited mechanism that scans time pulse domain by a plurality of function time pulse domains merging, thus, reached and simplified the Complicated Flow of back segment test design and the object that reduces chip development cost.
Accompanying drawing explanation
Fig. 1 is an embodiment process flow diagram of the present invention's one IC scanning time pulse domain distribution method.
Fig. 2 is the process flow diagram of an embodiment of the IC scanning time pulse domain distribution method after the present invention simplifies.
Fig. 3 is that a plurality of function time pulse domains by an integrated circuit in Fig. 2 of the present invention divide into groups and distribute to one first embodiment process flow diagram of the method that the step of a plurality of scanning time pulse domains comprises.
Fig. 4 is that a plurality of function time pulse domains by an integrated circuit in Fig. 2 of the present invention divide into groups and distribute to one second embodiment process flow diagram of the method that the step (that is step 204) of a plurality of scanning time pulse domains comprises.
Fig. 5 is that a plurality of function time pulse domains by an integrated circuit in Fig. 2 of the present invention divide into groups and distribute to one the 3rd embodiment process flow diagram of the method that the step (that is step 204) of a plurality of scanning time pulse domains comprises.
Fig. 6 is that a plurality of function time pulse domains by an integrated circuit in Fig. 2 of the present invention divide into groups and distribute to one the 4th embodiment process flow diagram of the method that the step (that is step 204) of a plurality of scanning time pulse domains comprises.
Fig. 7 utilizes an IC scanning time pulse domain distribution method of Fig. 1 to distribute an embodiment schematic diagram of a circuit design file of an integrated circuit.
Wherein, description of reference numerals is as follows:
100,200,300,400,500,600 process flow diagrams;
102～116,202～204,302,402,502,602 steps;
700 circuit design files;
702 first function time pulse domains;
704 second function time pulse domains;
706 the 3rd function time pulse domains;
708 the 4th function time pulse domains;
710 five-function time pulse domains;
712 first scanning time pulse domains;
714 second scanning time pulse domains;
716 the 3rd scanning time pulse domains.
Embodiment
Please refer to Fig. 1, it is an embodiment process flow diagram of explanation IC scanning time pulse domain distribution method 100 of the present invention.In the present embodiment, IC scanning time pulse domain distribution method 100 can be used to a circuit design file of an integrated circuit to scan the distribution of time pulse domain, to produce the scanning time pulse domain allocation scheme an of the best.If can reach identical result substantially, do not need necessarily according to the step order in the flow process shown in Fig. 1, to carry out, and the step shown in Fig. 1 not necessarily will carry out continuously, that is other steps also can be inserted wherein.In addition, some step in Fig. 1 can be omitted it according to different embodiment or design requirement.IC scanning time pulse domain distribution method 100 includes following steps:
Step 102: receive a circuit design file;
Step 104: receive a sequential restriction file;
Step 106: this circuit design file and this sequential restriction file are analyzed;
Step 108: produce a time pulse domain report file;
Step 110: receive user's defined file;
Step 112: according to this time pulse domain report file and this user's defined file, a plurality of function time pulse domains of this integrated circuit are divided into groups, and the circuit after grouping is distributed to a plurality of scanning time pulse domains;
Step 114: produce one scan time pulse domain allocation report;
Step 116: complete the distribution of this IC scanning time pulse domain.
When a circuit designers complete the circuit of an integrated circuit synthetic after, it can produce a circuit design file (Netlist).For example, this integrated circuit can be the digital circuit with a specific function.Because digital circuit need to use one or more clock pulses when operating, trigger some specific circuit elements in this digital circuit, so this circuit designers also can provide the sequential restriction (step 104) of describing those clock pulses about a sequential restriction file of this integrated circuit.In order more accurately this circuit design file of this integrated circuit to be scanned to time pulse domain, divide the distribution combination that is equipped with generation one the best, IC scanning time pulse domain distribution method 100 of the present invention can be analyzed (step 106) to this circuit design file and this sequential restriction file.After analyzing, IC scanning time pulse domain distribution method 100 of the present invention can produce a time pulse domain report file, and wherein this time pulse domain report file is for recording the information (step 108) in the relevant clock pulse path being cross-linked in this circuit design file.
In addition, in the present embodiment, in this circuit design file, include a plurality of function time pulse domains, and this sequential restriction file can include the frequency, phase place of the plurality of function time pulse domain and the information of the definition in false path each other, in other words, utilize this sequential restriction file and this circuit design file to simulate particularly the functional operation of each clock pulse under the cycle before out this integrated circuit is manufactured, use check and whether have timing conflict.In addition, in this circuit design file, include a plurality of triggers (flip flop), wherein arbitrary trigger is all controlled by a corresponding function clock pulse, that is to say, each trigger all belongs to one of them of the plurality of function time pulse domain, utilizes the information in this sequential restriction file the plurality of trigger in this circuit design file can be corresponded to respectively to the plurality of function time pulse domain.Therefore, when having a path to exist between two triggers and this two trigger belongs to different function time pulse domain, this path is a zigzag path, this zigzag path can be divided into again true path (true path) or false path according to sequential restriction file in addition, in step 108, the quantity of the zigzag path between at least arbitrary scanning time pulse domain and another scanning time pulse domain can be stored in this time pulse domain report file, in addition, in this time pulse domain report file, can comprise again arbitrary zigzag path and belong to true path or the information in false path, or the flip flop number in the middle of arbitrary function time pulse domain.
In step 112, this time pulse domain report file is one be used for the plurality of function time pulse domain of this integrated circuit to divide into groups and distribute to the foundation of the plurality of scanning time pulse domain, in other words, because the number of the plurality of scanning time pulse domain is often less than the plurality of function time pulse domain, cannot directly the time pulse domain under functional mode be transformed into scan pattern in man-to-man mode, therefore the plurality of function time pulse domain need to be divided according to the number of the plurality of scanning time pulse domain and this time pulse domain report file.In addition, IC scanning time pulse domain distribution method 100 of the present invention can be separately with reference to user's defined file by a plurality of function time pulse domains of this integrated circuit divide into groups (step 110), wherein this user's defined file includes at least one of the setting of algorithm of one scan time pulse domain distribution and the setting of the number of one scan time pulse domain, the setting of the algorithm that this scanning time pulse domain distributes is for carrying out in addition setting and the adjustment of details according to different application or demand for the algorithm of the distribution of scanning time pulse domain, it is the size according to chip that the number of this scanning time pulse domain is set, the actual state of pin number and tester table decides.
On the other hand, circuit after grouping is distributed to after a plurality of scanning time pulse domains, IC scanning time pulse domain distribution method 100 of the present invention can produce one scan time pulse domain allocation report and consult (step 114) for this circuit designers, and completes the distribution (step 116) of this IC scanning time pulse domain.
In sum, IC scanning time pulse domain distribution method 100 of the present invention is separately expressed as the step shown in Fig. 2.Figure 2 shows that the process flow diagram of an embodiment of IC scanning time pulse domain distribution method 200 of the present invention, if can reach identical result substantially, do not need necessarily according to the step order in the flow process shown in Fig. 2, to carry out, and the step shown in Fig. 2 not necessarily will be carried out continuously, that is other steps also can be inserted wherein.In addition, some step in Fig. 2 can be omitted it according to different embodiment or design requirement.Method 200 includes following steps:
Step 202: the quantity of the zigzag path in a plurality of function time pulse domains of finding out this integrated circuit with a circuit design file and the sequential restriction file of this integrated circuit between two function time pulse domains, to produce a time pulse domain report file;
Step 204: according to this time pulse domain report file, the plurality of function time pulse domain of this integrated circuit is divided into groups and distributes to a plurality of scanning time pulse domains.
Therefore note that because a digital integrated circuit can be a huge and complicated circuit conventionally, conventionally cannot utilize the same set of standard just can the optimized distribution that each integrated circuit is scanned to time pulse domain.In other words, when method 200 of the present invention has produced after this time pulse domain report file in step 202, it can use different modes one integrated circuit to be scanned to the distribution of time pulse domain according to contained content in this time pulse domain report file, and the embodiment of those different modes is as shown in Fig. 3 ~ 6.Figure 3 shows that the plurality of function time pulse domain by this integrated circuit in Fig. 2 of the present invention divides into groups and distributes to one first embodiment 300 of the method that the step (that is step 204) of the plurality of scanning time pulse domain comprises.This first embodiment 300 includes following steps:
Step 302: when the quantity of the zigzag path between two function time pulse domains is less than a specific quantity, these two function time pulse domains are distributed to same one scan time pulse domain.
In step 302, this specific quantity can separately be set by user's defined file.It should be noted, the zigzag path number belonging between two function time pulse domains among same one scan time pulse domain is fewer, carrying out, the difficulty of Clock Tree when synthetic is less, the power consuming on the area increasing and tester table is also fewer, on the other hand, belong to zigzag path between two function time pulse domains among same one scan time pulse domain when more, especially wherein most of while be false path, can produce need to increase many extra areas and revise this script and do not need timing conflict to be processed when a large amount of timing conflicts causes Clock Tree synthetic.Therefore, the quantity of zigzag path can be used as at this main points whether different function time pulse domains is applicable to being sorted in same one scan time pulse domain.
Figure 4 shows that the plurality of function time pulse domain by this integrated circuit in Fig. 2 of the present invention divides into groups and distributes to one second embodiment 400 of the method that the step (that is step 204) of the plurality of scanning time pulse domain comprises.This second embodiment 400 includes following steps:
Step 402: when two function time pulse domains are asynchronous and when the quantity of zigzag path is between the two greater than a specific quantity, these two function time pulse domains are distributed to respectively to different scanning time pulse domains.
Asynchronous information in step 402 is drawn according to the information of the frequency in this sequential restriction file and phase place, when two function time pulse domains are while being asynchronous, major part in the middle of zigzag path between this two functions time pulse domain all can produce and when timing conflict causes Clock Tree synthetic, need to increase many extra areas and revise this script and do not need timing conflict to be processed, therefore, more with the zigzag path between the asynchronous function time pulse domain in the middle of one scan time pulse domain, the area increasing and the power of consumption are larger.Therefore, the quantity of zigzag path can be used as at this main points whether asynchronous function time pulse domain is applicable to being sorted in same one scan time pulse domain.
Figure 5 shows that the plurality of function time pulse domain by this integrated circuit in Fig. 2 of the present invention divides into groups and distributes to one the 3rd embodiment 500 of the method that the step (that is step 204) of the plurality of scanning time pulse domain comprises.The 3rd embodiment 500 includes following steps:
Step 502: when two function time pulse domains quantity that is the false path in zigzag path synchronously and between the two is greater than a specific quantity, these two function time pulse domains are distributed to respectively to different scanning time pulse domains.
In step 502, when two function time pulse domains quantity that is the false path in zigzag path synchronously and between the two is greater than a specific quantity, therefore represent that between this two functions time pulse domain, the direct common factor in function is little, can produce need to increase many extra areas and revise this and do not need timing conflict to be processed originally when a large amount of timing conflicts causes Clock Tree synthetic.
Figure 6 shows that the plurality of function time pulse domain by this integrated circuit in Fig. 2 of the present invention divides into groups and distributes to one the 4th embodiment 600 of the method that the step (that is step 204) of the plurality of scanning time pulse domain comprises.The 4th embodiment 600 includes following steps:
Step 602: whether the quantity that checks the trigger comprising in this specific scanning time pulse domain surpasses a specific quantity.
In addition, uneven for avoiding the flip flop number of the every one scan time pulse domain after grouping to distribute, cause the too much situation of flip flop number in this scanning time pulse domain, and then the instantaneous power consumption of increase test, in step 602, use this specific quantity to be used as the upper limit of the flip flop number of every one scan time pulse domain.
Note that the present invention does not limit wherein a kind of mode of only selecting in Fig. 3 ~ 6 and one integrated circuit scanned to the distribution of time pulse domain, it can also scan the distribution of time pulse domain with reference to more than one mode in figure 3 ~ 6 simultaneously to an integrated circuit.
Please refer to Fig. 7.Shown in Fig. 7, be to utilize the IC scanning time pulse domain distribution method 100 of Fig. 1 to distribute an embodiment schematic diagram of a circuit design file 700 of an integrated circuit.When step 112, IC scanning time pulse domain distribution method 100 of the present invention can define a plurality of function time pulse domains that circuit design file 700 comprises originally, that is one first function time pulse domain 702, one second function time pulse domain 704, one the 3rd function time pulse domain 706, one the 4th function time pulse domain 708 and a five-function time pulse domain 710, wherein the first function time pulse domain 702 has the individual trigger of 20K (thousand), the second function time pulse domain 704 has the individual trigger of 30K (thousand), the 3rd function time pulse domain 706 has the individual trigger of 15K (thousand), the 4th function time pulse domain 708 has the individual trigger of 10K (thousand), and five-function time pulse domain 710 has the individual trigger of 10K (thousand).Then, in step 108, IC scanning time pulse domain distribution method 100 of the present invention can be found out the quantity of the zigzag path between central any two function time pulse domains of this integrated circuit, wherein between the first function time pulse domain 702 and the second function time pulse domain 704, there is 20K (thousand) paths, between the first function time pulse domain 702 and the 3rd function time pulse domain 706, there is 50K (thousand) paths, between the first function time pulse domain 702 and the 4th function time pulse domain 708, there is 10K (thousand) paths, between the first function time pulse domain 702 and five-function time pulse domain 710, do not there is any path, between the second function time pulse domain 704 and the 3rd function time pulse domain 706, do not there is any path, between the second function time pulse domain 704 and the 4th function time pulse domain 708, there is 10K (thousand) paths, between the second function time pulse domain 704 and five-function time pulse domain 704, do not there is any path, between the 3rd function time pulse domain 706 and the 4th function time pulse domain 708, there is 9K (thousand) paths, between the 3rd function time pulse domain 706 and five-function time pulse domain 710, there is 30K (thousand) paths, between the 4th function time pulse domain 708 and five-function time pulse domain 710, there is 100K (thousand) paths.
Therefore, the mode of utilizing embodiment to disclose as Fig. 3 ~ 6, the second function time pulse domain 704 and the 3rd function time pulse domain 706 are just assigned to one first scanning time pulse domain 712, and it is corresponding one first scanning clock pulse clk1.The first function time pulse domain 702 and five-function time pulse domain 710 are just assigned to one second scanning time pulse domain 714, and it is corresponding one second scanning clock pulse clk2.The 4th function time pulse domain 708 is just assigned to one the 3rd scanning time pulse domain 716, and it is corresponding one the 3rd scanning clock pulse clk3, as shown in Figure 7.Thus, the circuit design file 700 of this integrated circuit just can come the first scanning time pulse domain 712 respectively, the second scanning time pulse domain 714, the 3rd scanning time pulse domain 716 with the correctness of proof scheme design document 700 with the first scanning clock pulse clk1, the second scanning clock pulse clk2 and the 3rd scanning clock pulse clk3.
In addition, the method according to this invention proposes a kind of machine readable media, it stores a procedure code, when this procedure code can be carried out following steps by a processor when performed: the quantity of the zigzag path in a plurality of function time pulse domains of finding out this integrated circuit with a circuit design file and the sequential restriction file of this integrated circuit between two function time pulse domains, to produce a time pulse domain report file; And at least according to this time pulse domain report file, the plurality of function time pulse domain of this integrated circuit is divided into groups and distributes to a plurality of scanning time pulse domains.Wherein the number of the plurality of scanning time pulse domain is less than the number of the plurality of function time pulse domain.The step of wherein the plurality of function time pulse domain of this integrated circuit being divided into groups and distributing to the plurality of scanning time pulse domain comprises: receive user's defined file; And according to this time pulse domain report file and this user's defined file, the plurality of function time pulse domain of this integrated circuit is divided into groups and distributes to the plurality of scanning time pulse domain.Wherein in this circuit design file, include a plurality of function time pulse domains, and this sequential restriction file can include the frequency, phase place of the plurality of function time pulse domain and the information of the definition in false path each other.In addition, in this circuit design file, include a plurality of triggers, wherein arbitrary trigger is all controlled by a corresponding function clock pulse, utilizes the information in this sequential restriction file the plurality of trigger in this circuit design file can be corresponded to respectively to the plurality of function time pulse domain.
In addition, the quantity of the zigzag path between at least arbitrary scanning time pulse domain and another scanning time pulse domain can be stored in this time pulse domain report file, and can comprise arbitrary zigzag path in this time pulse domain report file, belong to true path or the information in false path, or the flip flop number in the middle of arbitrary function time pulse domain.And this user's defined file includes at least one of the setting of algorithm of one scan time pulse domain distribution and the setting of the number of one scan time pulse domain, the setting of the algorithm that this scanning time pulse domain distributes is for carrying out in addition setting and the adjustment of details according to different application or demand for the algorithm of the distribution of scanning time pulse domain, and the number setting of this scanning time pulse domain is that the actual state of size, pin number and tester table according to chip decides.
Briefly, disclosed embodiment utilizes zigzag path between the function time pulse domain of integrated circuit to scan minute being equipped with of time pulse domain a plurality of function time pulse domains are merged and be assigned to limited scanning time pulse domain, and reach, simplifies the Complicated Flow of back segment test design and the object that reduces chip development cost.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application Patent right requirement scope change and modify, and all should belong to the covering scope of the claims in the present invention.
Claims (7)
1. a scanning time pulse domain distribution method for integrated circuit, includes:
The quantity of the zigzag path in a plurality of function time pulse domains of finding out this integrated circuit with a circuit design file and the sequential restriction file of this integrated circuit between two function time pulse domains, to produce a time pulse domain report file; And
According to this time pulse domain report file, the plurality of function time pulse domain is divided into groups and distribute to a plurality of scanning time pulse domains; Wherein, the number of the plurality of scanning time pulse domain is less than the number of the plurality of function time pulse domain.
2. the method for claim 1, wherein the plurality of function time pulse domain is divided into groups and the step of distributing to the plurality of scanning time pulse domain includes:
Receive user's defined file; And
According to this time pulse domain report file and this user's defined file, the plurality of function time pulse domain of this integrated circuit is divided into groups and distributes to the plurality of scanning time pulse domain.
3. the method for claim 1, wherein the plurality of function time pulse domain is divided into groups and the step of distributing to the plurality of scanning time pulse domain includes:
When the quantity of the zigzag path between these two function time pulse domains is less than a specific quantity, these two function time pulse domains are distributed to same one scan time pulse domain.
4. the method for claim 1, wherein the plurality of function time pulse domain is divided into groups and the step of distributing to the plurality of scanning time pulse domain includes:
When these two function time pulse domains are asynchronous and when the quantity of zigzag path is between the two greater than a specific quantity, these two function time pulse domains are distributed to respectively to different scanning time pulse domains.
5. the method for claim 1, wherein the plurality of function time pulse domain is divided into groups and the step of distributing to the plurality of scanning time pulse domain includes:
When these two function time pulse domains quantity that is the false path in zigzag path synchronously and between the two is greater than a specific quantity, these two function time pulse domains are distributed to respectively to different scanning time pulse domains.
6. the method for claim 1, the step that wherein produces this time pulse domain report file comprises:
With this circuit design file of this integrated circuit and this sequential restriction file, find out the quantity of the trigger that each function time pulse domain comprises in the middle of the quantity of the zigzag path between these two function time pulse domains in the middle of this integrated circuit and this integrated circuit, to produce this time pulse domain report file.
7. the method for claim 1, wherein the plurality of function time pulse domain is divided into groups and the step of distributing to the plurality of scanning time pulse domain includes:
According to the quantity of the zigzag path between these two function time pulse domains, a plurality of specific function time pulse domains of this integrated circuit are distributed to a specific scanning time pulse domain; And
Whether the quantity that checks the trigger comprising in this specific scanning time pulse domain surpasses a specific quantity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210380386.4A CN103713254B (en) | 2012-10-09 | 2012-10-09 | IC scanning time pulse domain distribution method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210380386.4A CN103713254B (en) | 2012-10-09 | 2012-10-09 | IC scanning time pulse domain distribution method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103713254A true CN103713254A (en) | 2014-04-09 |
| CN103713254B CN103713254B (en) | 2016-08-10 |
Family
ID=50406381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210380386.4A Active CN103713254B (en) | 2012-10-09 | 2012-10-09 | IC scanning time pulse domain distribution method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103713254B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1570805A (en) * | 2003-10-10 | 2005-01-26 | 威盛电子股份有限公司 | Device and operating method for signal synchronization between different time pulse domains |
| US20050091622A1 (en) * | 2003-10-28 | 2005-04-28 | Pappu Krishna K. | Method of grouping scan flops based on clock domains for scan testing |
| CN1797952A (en) * | 2004-12-29 | 2006-07-05 | 旺玖科技股份有限公司 | System and method of ultra sampling high speed time pulse / data recovery |
| US20090125771A1 (en) * | 2007-11-12 | 2009-05-14 | Texas Instruments Incorporated | Scan Based Testing of an Integrated Circuit Containing Circuit Portions Operable in Different Clock Domains during Functional Mode |
| TW201129893A (en) * | 2009-03-12 | 2011-09-01 | Qualcomm Inc | System and method of clock tree synthesis |
-
2012
- 2012-10-09 CN CN201210380386.4A patent/CN103713254B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1570805A (en) * | 2003-10-10 | 2005-01-26 | 威盛电子股份有限公司 | Device and operating method for signal synchronization between different time pulse domains |
| US20050091622A1 (en) * | 2003-10-28 | 2005-04-28 | Pappu Krishna K. | Method of grouping scan flops based on clock domains for scan testing |
| CN1797952A (en) * | 2004-12-29 | 2006-07-05 | 旺玖科技股份有限公司 | System and method of ultra sampling high speed time pulse / data recovery |
| US20090125771A1 (en) * | 2007-11-12 | 2009-05-14 | Texas Instruments Incorporated | Scan Based Testing of an Integrated Circuit Containing Circuit Portions Operable in Different Clock Domains during Functional Mode |
| TW201129893A (en) * | 2009-03-12 | 2011-09-01 | Qualcomm Inc | System and method of clock tree synthesis |
Non-Patent Citations (1)
| Title |
|---|
| 汪殿明: "振镜扫描器的ARM嵌入式负反馈控制系统研究", 《中国优秀硕士学位论文全文数据库·信息科技辑》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103713254B (en) | 2016-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104252481B (en) | The dynamic check method and apparatus of master-slave database consistency | |
| CN102906579B (en) | Method and apparatus for scheduling a use of test resources of a test arrangement for the execution of test groups | |
| CN106339312A (en) | API (application programming interface) testing method and system | |
| CN101908015B (en) | Device and method for creating test case based on components | |
| CN100422954C (en) | Software system multi-user characteristic testing method and system | |
| CN106156165A (en) | Method of data synchronization between heterogeneous data source and device | |
| Hutton et al. | Characterization and parameterized random generation of digital circuits | |
| Schneider et al. | GPU-accelerated simulation of small delay faults | |
| CN108415830A (en) | A kind of generation method and device of software test case | |
| CN104572301A (en) | Resource distribution method and system | |
| CN112232006A (en) | Standard cell library verification method and device, electronic equipment and storage medium | |
| CN201435074Y (en) | Device for generating test case based on member | |
| CN103020396B (en) | A kind of method that automatic generation is asserted and device | |
| CN112257362B (en) | Verification method, verification device and storage medium for logic code | |
| CN111624475B (en) | Method and system for testing large-scale integrated circuit | |
| CN103713254A (en) | Scan clock domain distribution method for integrated circuit | |
| TWI477794B (en) | Method of integrated circuit scan clock domain allocation and related machine readable media | |
| CN107315863B (en) | Layout optimization method and device, terminal and storage medium | |
| CN105677968B (en) | Programmable logic device circuit drawing drawing method and device | |
| CN112861455B (en) | FPGA modeling verification system and method | |
| CN107992417B (en) | Test method, device and equipment, readable storage medium storing program for executing based on storing process | |
| CN100527138C (en) | Simulating example producing method and device for integrated circuit element | |
| CN100417950C (en) | Method for constructing two-stage sweep test structure with low test power dissipation | |
| CN103218287B (en) | For the method for testing hadoop streaming script and device | |
| CN100440226C (en) | Chip algorithm simulating platform and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |