CN103713254B - IC scanning time pulse domain distribution method - Google Patents
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- CN103713254B CN103713254B CN201210380386.4A CN201210380386A CN103713254B CN 103713254 B CN103713254 B CN 103713254B CN 201210380386 A CN201210380386 A CN 201210380386A CN 103713254 B CN103713254 B CN 103713254B
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Abstract
The invention discloses a kind of IC scanning time pulse domain distribution method, include: use a circuit design file of this integrated circuit and a sequential to limit the file quantity to the zigzag path between two function time pulse domains in the multiple function time pulse domains find out this integrated circuit, to produce a time pulse domain report file；And according to this time pulse domain report file, the plurality of function time pulse domain is grouped and distributes to multiple scanning time pulse domain.
Description
Technical field
The present invention is relevant to one scan time pulse domain distribution method and uses this scanning time pulse domain distribution method
One machine readable media, a kind of determine an integrated circuit scanning time pulse domain distribution method to relevant
Machine readable media.
Background technology
Sweep test pattern (scan test pattern) is applied to test on integrated circuit widely, and scanning is surveyed
Attempt sample must collocation scanning seasonal pulse (scan clock) to test on automatic test machine platform, and when scanning
The quantity of arteries and veins is often limited to stitch (pin) number of limited chip port or automatic test machine platform.Therefore,
Different function time pulse domains (function clock domain) generally requires merging with when scan testing mode
Share one scan seasonal pulse, i.e. utilize this scanning seasonal pulse to replace original more than one function seasonal pulse, become
One new scanning time pulse domain (scan clock domain), but, during for avoiding testing, instantaneous power consumed
Greatly, multiple scanning seasonal pulse framework and its phase place that staggers can be used.But, between two function time pulse domains
For asynchronous relation or time there is a large amount of false path (false path), this two functions time pulse domain is closed
And many timing conflicts (timing violation) can be increased under scan testing mode, cause clock trees to synthesize
The degree of difficulty of (clock tree synthesis), in turn results in the increase of area and power.
Therefore, have in the distribution re-starting scanning time pulse domain later of clock trees synthesis traditionally,
Through iterated revision several times to obtain preferably result, or it is to increase a large amount of chip area and people
The power time solves timing conflict, and such process consumes a large amount of quality time and the money of chip development
Source, therefore it provides a mechanism is efficiently to merge multiple function time pulse domains and to be assigned to limited
The problem that individual scanning time pulse domain has become needed badly the solution in this field.
Summary of the invention
Therefore, an object of the present invention is to provide one more efficient IC scanning time pulse domain
Distribution method and relevant machine readable media.
A first embodiment according to the present invention, it discloses a kind of one scan seasonal pulse determining an integrated circuit
The method of territory distribution.The method includes: use a circuit design file and a sequential of this integrated circuit
Limit that file finds out in multiple function time pulse domains of this integrated circuit between two function time pulse domains is staggered
The quantity in path, to produce a time pulse domain report file；And according to this time pulse domain report file, should
Multiple function time pulse domains are grouped and distribute to multiple scanning time pulse domain.
One second embodiment according to the present invention, a kind of machine readable media of its proposition, store a source code,
When this source code can be performed following steps time performed by one processor: use a circuit of this IC
Design document and a sequential limit file and find out two merits in multiple function time pulse domains of this integrated circuit
The quantity of the zigzag path between energy time pulse domain, to produce a time pulse domain report file；And during according to this
Arteries and veins territory report file, is grouped and distributes to multiple scanning time pulse domain by the plurality of function time pulse domain.
Embodiment disclosed in invention utilizes the zigzag path between the function time pulse domain of integrated circuit to carry out
The distribution of scanning time pulse domain, that is provide and multiple function time pulse domains can be merged and be assigned to limited sweep
Retouch the mechanism of time pulse domain, consequently, it is possible to reached to simplify Complicated Flow and the reduction of back segment test design
The purpose of chip development cost.
Accompanying drawing explanation
Fig. 1 is an embodiment flow chart of the present invention one IC scanning time pulse domain distribution method.
Fig. 2 is the stream of an embodiment of the IC scanning time pulse domain distribution method after the present invention simplifies
Cheng Tu.
Fig. 3 is to be grouped and distribute to many by multiple function time pulse domains of an integrated circuit in Fig. 2 of the present invention
One first embodiment flow chart of the method that the step of individual scanning time pulse domain is comprised.
Fig. 4 is to be grouped and distribute to many by multiple function time pulse domains of an integrated circuit in Fig. 2 of the present invention
One second embodiment flow chart of the method that the step (that is step 204) of individual scanning time pulse domain is comprised.
Fig. 5 is to be grouped and distribute to many by multiple function time pulse domains of an integrated circuit in Fig. 2 of the present invention
One the 3rd embodiment flow chart of the method that the step (that is step 204) of individual scanning time pulse domain is comprised.
Fig. 6 is to be grouped and distribute to many by multiple function time pulse domains of an integrated circuit in Fig. 2 of the present invention
One the 4th embodiment flow chart of the method that the step (that is step 204) of individual scanning time pulse domain is comprised.
Fig. 7 is that the IC scanning time pulse domain distribution method utilizing Fig. 1 distributes an integrated circuit
One embodiment schematic diagram of one circuit design file.
Wherein, description of reference numerals is as follows:
100,200,300,400,500,600 flow chart；
102～116,202～204,302,402,502,602 steps；
700 circuit design file；
702 first function time pulse domains；
704 second function time pulse domains；
706 the 3rd function time pulse domains；
708 the 4th function time pulse domains；
710 five-function time pulse domains；
712 first scanning time pulse domains；
714 second scanning time pulse domains；
716 the 3rd scanning time pulse domains.
Detailed description of the invention
Refer to Fig. 1, it is the reality that IC scanning time pulse domain distribution method 100 of the present invention is described
Execute example flow chart.In the present embodiment, IC scanning time pulse domain distribution method 100 can be used to one
One circuit design file of integrated circuit is scanned the distribution of time pulse domain, during to produce an optimal scanning
The arteries and veins territory method of salary distribution.If generally can reach identical result, it is not required to necessarily according to shown in Fig. 1
Sequence of steps in flow process is carried out, and the step shown in Fig. 1 is not necessarily intended to be carried out continuously, that is other
Step also can be inserted into wherein.Additionally, some step in Fig. 1 can be according to different embodiments or design requirement
Omit it.IC scanning time pulse domain distribution method 100 includes following steps:
Step 102: receive a circuit design file；
Step 104: receive a sequential and limit file；
Step 106: this circuit design file and this sequential are limited file and is analyzed；
Step 108: produce a time pulse domain report file；
Step 110: receive a user definition file；
Step 112: define file by this integrated electricity according to this time pulse domain report file and this user
Multiple function time pulse domains on road are grouped, and the circuit after packet is distributed to multiple scanning time pulse domain；
Step 114: produce the distribution report of one scan time pulse domain；
Step 116: complete the distribution of this IC scanning time pulse domain.
After a circuit designers completes the circuit synthesis of an integrated circuit, it can produce a circuit design literary composition
Part (Netlist).For example, this integrated circuit can be the digital circuit with a specific function.Due to number
It is specific to trigger some in this digital circuit that word circuit needs to use one or more seasonal pulse when operation
Component, therefore this circuit designers also can provide the sequential about this integrated circuit to limit file
The sequential describing those seasonal pulse limits (step 104).In order to more accurately this circuit of this integrated circuit be set
Meter file is scanned time pulse domain distribution and combines to produce an optimal distribution, and the integrated circuit of the present invention is swept
Retouch time pulse domain distribution method 100 can this circuit design file and this sequential restriction file be analyzed
(step 106).After analyzing, the IC scanning time pulse domain distribution method 100 of the present invention can be produced
A raw time pulse domain report file, wherein this time pulse domain report file is used to record in this circuit design file
The information (step 108) in the relevant seasonal pulse path being cross-linked.
Additionally, in the present embodiment, this circuit design file includes multiple function time pulse domain, and is somebody's turn to do
Sequential limits file can include the frequency of the plurality of function time pulse domain, phase place and the most false road
The information of the definition in footpath, in other words, utilizes this sequential to limit file and this circuit design file is permissible
The functional operation under each clock cycle, mat was specifically simulated before this integrated circuit is manufactured
To check whether to there is timing conflict.It addition, this circuit design file includes multiple trigger (flip
Flop), any of which trigger is all controlled by a corresponding function seasonal pulse, say, that each tactile
Sending out device and broadly fall into one of them of the plurality of function time pulse domain, the information utilizing this sequential to limit in file can
Trigger the plurality of in this circuit design file is corresponded to the plurality of function time pulse domain respectively.Therefore, when
When belonging to different function time pulse domain with the presence of a path and this two trigger between two triggers, this path
Being a zigzag path, additionally this zigzag path can be divided into again true path (true according to sequential restriction file
Path) or false path, in step 108, arbitrary scanning time pulse domain and another scan time pulse domain
Between the quantity of zigzag path can be stored in this time pulse domain report file, additionally, this time pulse domain report
Announcement file can comprise again arbitrary zigzag path and belong to true path or the information in false path, or appoint
Flip flop number in the middle of one function time pulse domain.
In step 112, this time pulse domain report file is one for by the plurality of function of this integrated circuit
Time pulse domain is grouped and distributes to the foundation of the plurality of scanning time pulse domain, stated differently, since the plurality of scanning
The number of time pulse domain is often below the plurality of function time pulse domain, it is impossible in man-to-man mode directly by function
Time pulse domain under pattern is transformed into scan pattern, it is therefore desirable to by the plurality of function time pulse domain according to the plurality of
The number of scanning time pulse domain divides with this time pulse domain report file.Additionally, the integrated circuit of the present invention is swept
Retouching time pulse domain distribution method 100 can be referring in addition to a user definition file by multiple merit of this integrated circuit
Can carry out being grouped (step 110) by time pulse domain, wherein this user definition file includes one scan time pulse domain and divides
At least one of the setting of the setting of the algorithm joined and the number of one scan time pulse domain, this scanning seasonal pulse
The setting of the algorithm of territory distribution is used to the dividing for scanning time pulse domain according to different application or demand
The algorithm joined is additionally carried out setting and the adjustment of details, and the number of this scanning time pulse domain sets and is then
The actual state of size, foot number and tester table according to chip determines.
On the other hand, after the circuit after packet distributes to multiple scanning time pulse domain, the integrated electricity of the present invention
Road scanning time pulse domain distribution method 100 can produce the distribution report of one scan time pulse domain for this circuit designers
Refering to (step 114), and complete the distribution (step 116) of this IC scanning time pulse domain.
In sum, the IC scanning time pulse domain distribution method 100 of the present invention is separately expressed as Fig. 2 institute
The step shown.Fig. 2 show an enforcement of the IC scanning time pulse domain distribution method 200 of the present invention
The flow chart of example, if generally can reach identical result, is not required to necessarily according to the stream shown in Fig. 2
Sequence of steps in journey is carried out, and the step shown in Fig. 2 is not necessarily intended to be carried out continuously, that is other steps
Suddenly also can be inserted into wherein.Additionally, some step in Fig. 2 can save according to different embodiments or design requirement
Summary.Method 200 includes following steps:
Step 202: use a circuit design file of this integrated circuit and a sequential to limit file and find out
The quantity of zigzag path between two function time pulse domains in multiple function time pulse domains of this integrated circuit, with
Produce a time pulse domain report file；
Step 204: according to this time pulse domain report file, by the plurality of function time pulse domain of this integrated circuit
It is grouped and distributes to multiple scanning time pulse domain.
Note that owing to a digital integrated circuit would generally be a huge and complicated circuit, therefore
Same set of standard generally cannot be utilized just with optimized, each integrated circuit can be scanned time pulse domain
Distribution.In other words, this time pulse domain report literary composition is created when the method 200 of the present invention in step 202
After part, it can come one integrated by different modes according to content contained in this time pulse domain report file
Circuit is scanned the distribution of time pulse domain, and the enforcement of those different modes is such as shown in Fig. 3 ~ 6.Fig. 3 institute
Be shown as in Fig. 2 of the present invention is grouped and distributes to the plurality of by the plurality of function time pulse domain of this integrated circuit
One first embodiment 300 of the method that the step (that is step 204) of scanning time pulse domain is comprised.This is first years old
Embodiment 300 includes following steps:
Step 302: when the quantity of the zigzag path between two function time pulse domains is less than a specific quantity,
These two function time pulse domains are distributed to same one scan time pulse domain.
In step 302, this specific quantity separately can be defined file by user and sets.It should be noted that
Belong to the zigzag path number between two function time pulse domains among same one scan time pulse domain the fewest, carrying out
Difficulty during clock trees synthesis is the least, and the power that the area increased and tester table consume is the fewest,
On the other hand, the zigzag path between two function time pulse domains among same one scan time pulse domain is belonged to the most
Time, when especially wherein most is false path, then can produce substantial amounts of timing conflict and cause clock trees
Need the many extra areas of increase to revise this during synthesis and be originally not required to timing conflict to be processed.Therefore,
The quantity of zigzag path can be used as different function time pulse domains if appropriate for when being sorted in same one scan at this
One main points in arteries and veins territory.
What Fig. 4 showed in Fig. 2 of the present invention is grouped the plurality of function time pulse domain of this integrated circuit and divides
One second embodiment of the method that the step (that is step 204) of dispensing the plurality of scanning time pulse domain is comprised
400.This second embodiment 400 includes following steps:
Step 402: when two function time pulse domains are asynchronous and the quantity of zigzag path between the two is big
When a specific quantity, these two function time pulse domains are respectively allocated to different scanning time pulse domains.
Asynchronous information in step 402 is based on this sequential and limits the frequency in file and phase place
Information drawn, when two function time pulse domains are asynchronous, staggered between this two functions time pulse domain
Major part in the middle of path all can produce needs when timing conflict causes clock trees to synthesize to be increased many extra
Area is revised this script and is not required to timing conflict to be processed, therefore, and non-with in the middle of one scan time pulse domain
Zigzag path between synchronizing function time pulse domain is the most, and the area increased is the biggest with the power of consumption.Cause
This, it is same if appropriate for being sorted in that the quantity of zigzag path can be used as asynchronous function time pulse domain at this
One main points of scanning time pulse domain.
What Fig. 5 showed in Fig. 2 of the present invention is grouped the plurality of function time pulse domain of this integrated circuit and divides
One the 3rd embodiment of the method that the step (that is step 204) of dispensing the plurality of scanning time pulse domain is comprised
500.3rd embodiment 500 includes following steps:
Step 502: when two function time pulse domains are the false road in synchronization and zigzag path between the two
When the quantity in footpath is more than a specific quantity, when these two function time pulse domains are respectively allocated to different scanning
Arteries and veins territory.
In step 502, it is to synchronize and vacation in zigzag path between the two when two function time pulse domains
Property path quantity more than a specific quantity time, represent between this two functions time pulse domain functionally is direct
Occuring simultaneously little, therefore can produce needs when substantial amounts of timing conflict causes clock trees to synthesize increases many extra
Area revise this and be originally not required to timing conflict to be processed.
What Fig. 6 showed in Fig. 2 of the present invention is grouped the plurality of function time pulse domain of this integrated circuit and divides
One the 4th embodiment of the method that the step (that is step 204) of dispensing the plurality of scanning time pulse domain is comprised
600.4th embodiment 600 includes following steps:
Step 602: check that whether the quantity of trigger included in this specific scanning time pulse domain is more than one
Specific quantity.
Additionally, the flip flop number for the every one scan time pulse domain after avoiding packet distributes inequality, cause this
The too much situation of flip flop number in scanning time pulse domain, and then increase the instantaneous power consumption of test, in step
In rapid 602, this specific quantity is used to be used as the upper limit of flip flop number of every one scan time pulse domain.
Note that the present invention does not limit only selects the one way in which in Fig. 3 ~ 6 to come an integrated electricity
Road is scanned the distribution of time pulse domain, and it is right that it can also come with reference to more than one mode in Fig. 3 ~ 6
One integrated circuit is scanned the distribution of time pulse domain.
Refer to Fig. 7.It it is the IC scanning time pulse domain distribution method 100 utilizing Fig. 1 shown in Fig. 7
Distribute an embodiment schematic diagram of a circuit design file 700 of an integrated circuit.When step 112,
The IC scanning time pulse domain distribution method 100 of the present invention can define circuit design file 700 originally
The multiple function time pulse domains comprised, that is one first function time pulse domain 702,1 second function time pulse domain
704, one the 3rd function time pulse domain 706, the 4th function time pulse domain 708 and a five-function time pulse domain
710, wherein the first function time pulse domain 702 has 20K (thousand) individual trigger, the second function time pulse domain 704
Having 30K (thousand) individual trigger, the 3rd function time pulse domain 706 has 15K (thousand) individual trigger, the 4th merit
Can have 10K (thousand) individual trigger by time pulse domain 708, and five-function time pulse domain 710 has 10K (thousand)
Individual trigger.Then, in step 108, the IC scanning time pulse domain distribution method 100 of the present invention
Can find out in the middle of this integrated circuit the quantity of zigzag path between any two function time pulse domains, wherein first
Between function time pulse domain 702 and the second function time pulse domain 704, there is 20K (thousand) paths, the first function
There is between time pulse domain 702 and the 3rd function time pulse domain 706 50K (thousand) paths, the first function seasonal pulse
There is between territory 702 and the 4th function time pulse domain 708 10K (thousand) paths, the first function time pulse domain 702
And not there is between five-function time pulse domain 710 any path, the second function time pulse domain 704 and the 3rd merit
Between time pulse domain 706, can not there is any path, the second function time pulse domain 704 and the 4th function time pulse domain
Have between 708 10K (thousand) paths, the second function time pulse domain 704 and five-function time pulse domain 704 it
Between not there is any path, have between the 3rd function time pulse domain 706 and the 4th function time pulse domain 708
9K (thousand) paths, has 30K (thousand) between the 3rd function time pulse domain 706 and five-function time pulse domain 710
Paths, has 100K (thousand) article road between the 4th function time pulse domain 708 and five-function time pulse domain 710
Footpath.
Therefore, the mode implemented disclosed in such as Fig. 3 ~ 6, the second function time pulse domain 704 and the 3rd are utilized
It is one first scanning time pulse domain 712 that function time pulse domain 706 is assigned, when it is corresponding one first scanning
Arteries and veins clk1.It is one second scanning that first function time pulse domain 702 and five-function time pulse domain 710 are assigned
Time pulse domain 714, it is corresponding one second scanning seasonal pulse clk2.4th function time pulse domain 708 is assigned
Being one the 3rd scanning time pulse domain 716, it is corresponding one the 3rd scanning seasonal pulse clk3, as shown in Figure 7.As
This one, the circuit design file 700 of this integrated circuit just can with first scanning seasonal pulse clk1, second
Scanning seasonal pulse clk2 and the 3rd scanning seasonal pulse clk3 distinguishes the first scanning time pulse domain 712, second and scans
Time pulse domain the 714, the 3rd scanning time pulse domain 716 is to verify the correctness of circuit design file 700.
It addition, the method according to the invention proposes a kind of machine readable media, it stores a procedure code, when
This procedure code can be performed following steps time performed by one processor: uses a circuit of this integrated circuit to set
When two functions in multiple function time pulse domains of this integrated circuit found out by meter file and sequential restriction file
The quantity of the zigzag path between arteries and veins territory, to produce a time pulse domain report file；And during depending at least on this
Arteries and veins territory report file, when being grouped the plurality of function time pulse domain of this integrated circuit and distribute to multiple scanning
Arteries and veins territory.The number of the most the plurality of scanning time pulse domain is less than the number of the plurality of function time pulse domain.Wherein will
The plurality of function time pulse domain of this integrated circuit is grouped and distributes to the step bag of the plurality of scanning time pulse domain
Contain: receive a user definition file；And according to this time pulse domain report file and this user definition literary composition
Part, is grouped and distributes to the plurality of scanning time pulse domain by the plurality of function time pulse domain of this integrated circuit.Its
In this circuit design file includes multiple function time pulse domain, and this sequential limits file and can include this
The information of the definition in the frequency of multiple function time pulse domains, phase place and the most false path.It addition,
Including multiple trigger in this circuit design file, any of which trigger is all by a corresponding function
Seasonal pulse is controlled, and utilizing this sequential to limit the information in file can touch the plurality of in this circuit design file
Send out device and correspond to the plurality of function time pulse domain respectively.
Additionally, the quantity meeting of the zigzag path between arbitrary scanning time pulse domain and another scanning time pulse domain
It is stored in this time pulse domain report file, and this time pulse domain report file can comprise arbitrary staggered road
Footpath belongs to the trigger number in the middle of true path or the information in false path, or arbitrary function time pulse domain
Amount.And this user definition file includes the setting of the algorithm that one scan time pulse domain distributes and sweeps
Retouching at least one of the setting of the number of time pulse domain, the setting of the algorithm of this scanning time pulse domain distribution is to use
It is additionally carried out details for the algorithm of the distribution of scanning time pulse domain according to different application or demand
Set and adjust, the number of this scanning time pulse domain set be then size according to chip, foot number and
The actual state of tester table determines.
Briefly, disclosed embodiment is between the function time pulse domain utilizing integrated circuit
Zigzag path is scanned the distribution of time pulse domain to be merged by multiple function time pulse domains and to be assigned to limited
Individual scanning time pulse domain, and reach simplify the Complicated Flow of back segment test design and reduce chip development cost
Purpose.
The foregoing is only presently preferred embodiments of the present invention, all according to the present patent application scope of the patent claims
Impartial change and the modification done, all should belong to the covering scope of the claims in the present invention.
Claims (11)
1. a scanning time pulse domain distribution method for integrated circuit, includes:
The circuit design file and the sequential that use this integrated circuit limit the file quantity to the zigzag path between two function time pulse domains in the multiple function time pulse domains find out this integrated circuit, to produce a time pulse domain report file；And
According to this time pulse domain report file, the plurality of function time pulse domain is grouped and distributes to multiple scanning time pulse domain；Wherein, the number of the plurality of scanning time pulse domain is less than the number of the plurality of function time pulse domain.
2. the method for claim 1, wherein this circuit design file includes the plurality of function time pulse domain and multiple trigger, and each of which trigger belongs to one of them of the plurality of function seasonal pulse；When having a path and this two triggers to belong to function time pulse domains different in the plurality of function time pulse domain between two triggers in the plurality of trigger, this path is a zigzag path, and this zigzag path is divided into true path and false path；This sequential limits the information that file includes the definition in the frequency of the plurality of function time pulse domain, phase place and this false path each other.
3. method as claimed in claim 2, wherein this time pulse domain report file includes that arbitrary zigzag path belongs to the flip flop number in the middle of this true path or the information in this false path, or arbitrary the plurality of function seasonal pulse.
4. the method for claim 1, the step wherein the plurality of function time pulse domain being grouped and being distributed to the plurality of scanning time pulse domain includes:
Receive a user definition file；And
Define file according to this time pulse domain report file with this user, the plurality of function time pulse domain of this integrated circuit is grouped and distributes to the plurality of scanning time pulse domain.
5. method as claimed in claim 4, wherein this user definition file includes at least one of setting of the setting of algorithm of a plurality of scanning time pulse domain distribution and the number of a plurality of scanning time pulse domain.
6. the method for claim 1, the step wherein the plurality of function time pulse domain being grouped and being distributed to the plurality of scanning time pulse domain includes:
When the quantity of the zigzag path between these two function time pulse domains is less than a specific quantity, these two function time pulse domains are distributed to same one scan time pulse domain.
7. the method for claim 1, the step wherein the plurality of function time pulse domain being grouped and being distributed to the plurality of scanning time pulse domain includes:
When these two function time pulse domains be asynchronous and the quantity of zigzag path between the two more than a specific quantity time, these two function time pulse domains are respectively allocated to different scanning time pulse domains.
8. the method for claim 1, the step wherein the plurality of function time pulse domain being grouped and being distributed to the plurality of scanning time pulse domain includes:
When the quantity in the false path during these two function time pulse domains are synchronization and zigzag path between the two is more than a specific quantity, these two function time pulse domains are respectively allocated to different scanning time pulse domains.
9. the method for claim 1, the step wherein producing this time pulse domain report file comprises:
This circuit design file of this integrated circuit and this sequential is used to limit file to find out in the middle of this integrated circuit the quantity of the trigger that each function time pulse domain is comprised in the middle of the quantity of the zigzag path between these two function time pulse domains and this integrated circuit, to produce this time pulse domain report file.
10. the method for claim 1, the step wherein the plurality of function time pulse domain being grouped and being distributed to the plurality of scanning time pulse domain includes:
According to the quantity of the zigzag path between these two function time pulse domains, multiple specific function time pulse domains of this integrated circuit are distributed to a specific scanning time pulse domain；And
Check that whether the quantity of trigger included in this specific scanning time pulse domain is more than a specific quantity.
11. the method for claim 1, also include: produce the distribution report of one scan time pulse domain.
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| US20050091622A1 (en) * | 2003-10-28 | 2005-04-28 | Pappu Krishna K. | Method of grouping scan flops based on clock domains for scan testing |
| US7624322B2 (en) * | 2007-11-12 | 2009-11-24 | Texas Instruments Incorporated | Scan based testing of an integrated circuit containing circuit portions operable in different clock domains during functional mode |
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| CN1570805A (en) * | 2003-10-10 | 2005-01-26 | 威盛电子股份有限公司 | Device and operating method for signal synchronization between different time pulse domains |
| CN1797952A (en) * | 2004-12-29 | 2006-07-05 | 旺玖科技股份有限公司 | System and method of ultra sampling high speed time pulse / data recovery |
| TW201129893A (en) * | 2009-03-12 | 2011-09-01 | Qualcomm Inc | System and method of clock tree synthesis |
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