CN103020396B - A kind of method that automatic generation is asserted and device - Google Patents
A kind of method that automatic generation is asserted and device Download PDFInfo
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- CN103020396B CN103020396B CN201210595076.4A CN201210595076A CN103020396B CN 103020396 B CN103020396 B CN 103020396B CN 201210595076 A CN201210595076 A CN 201210595076A CN 103020396 B CN103020396 B CN 103020396B
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Abstract
The embodiment of the invention discloses method and device that a kind of automatic generation asserts, the method comprises the first output step, exports user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification; Instantiating step, what input at described instantiation interface according to user asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation; Binding step, the first assertion verification code of described instantiation is tied to described design under test by the module information of the design under test inputted according to described user, obtains assertion verification simulation document.The present invention substantially increases in project development process the binding speed asserted between Validation Code and module, ensure that project process.
Description
Technical field
The present invention relates to verification technique field, particularly a kind of method asserted of automatic generation and device.
Background technology
Current SoC (SystemonChip, system level chip/SOC (system on a chip)) becomes increasingly complex, and simulating, verifying is also more and more difficult.
Checking based on Assertion (asserting) more and more comes into one's own as a kind of important checking.
But at least there is following shortcoming in the checking based on Assertion (asserting):
Because each development project has certain time limit requirement, because Assertion code needs the technician being familiar with SVA (SystemVerilogAssertion) grammer to write, and the construction cycle is long, therefore when project pressure is larger, project delay will be caused.
Summary of the invention
A kind of method that the object of the embodiment of the present invention is to provide automatic generation to assert and device, reduce the use difficulty of Assertion (asserting) code, Guarantee item progress.
To achieve these goals, embodiments provide a kind of method that automatic generation is asserted, comprising:
First exports step, exports user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification;
Instantiating step, what input at described instantiation interface according to user asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation;
Binding step, the first assertion verification code of described instantiation is tied to described design under test by the module information of the design under test inputted according to described user, obtains assertion verification simulation document.
Above-mentioned method, wherein, also comprises:
Second exports step, exports one and supplies user to input the module information inputting interface of described module information.
Above-mentioned method, wherein, described module information inputting interface and described instantiation interface are realized by Excel.
Above-mentioned method, wherein, described binding step specifically comprises:
First analyzing step, by module information described in the acquisition of information of resolving Excel module information inputting interface;
Second analyzing step, resolves the RTL file in described module information, obtains the port list in described RTL file and signal list;
Integration step, is tied to described design under test according to described module information and described port list and signal list by the assertion verification code of described instantiation.
Above-mentioned method, wherein, described checking simulation document comprises one for preserving the second assertion verification code, and is set to the reserve area of non-renewable state.
To achieve these goals, the embodiment of the present invention additionally provides the device that a kind of automatic generation is asserted, comprising:
First output module, for exporting user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification;
For what input at described instantiation interface according to user, instantiation module, asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation;
Binding module, the first assertion verification code of described instantiation is tied to described design under test by the module information for the design under test inputted according to described user, obtains assertion verification simulation document.
Above-mentioned device, wherein, also comprises:
Second output module, supplies user to input the module information inputting interface of described module information for exporting one.
Above-mentioned device, wherein, described module information inputting interface and described instantiation interface are realized by Excel.
Above-mentioned device, wherein, described binding module specifically comprises:
First resolution unit, for module information described in the acquisition of information by resolving Excel module information inputting interface;
Second resolution unit, for resolving the RTL file in described module information, obtains the port list in described RTL file and signal list;
Integral unit, for being tied to described design under test according to described module information and described port list and signal list by the assertion verification code of described instantiation.
Above-mentioned device, wherein, the second analyzing step specifically comprises:
Delete step, deletes all comment statements in described RTL file, generates the first temporary file;
First scanning step, scans the first temporary file, only retains the statement of specifying simulation model corresponding, obtains the second temporary file;
Second scanning step, scans described second temporary file, obtains final port list and signal name list.
Above-mentioned device, wherein, described second resolution unit specifically comprises:
Deleting subelement, for deleting all comment statements in described RTL file, generating the first temporary file;
First scanning subelement, for scanning the first temporary file, only retaining the statement of specifying simulation model corresponding, obtaining the second temporary file;
Second scanning subelement, for scanning described second temporary file, obtains final port list and signal name list.
Above-mentioned device, wherein, described checking simulation document comprises one for preserving the second assertion verification code, and is set to the reserve area of non-renewable state.
The embodiment of the present invention at least has following beneficial effect:
In the embodiment of the present invention, multiple template is taken out in advance according to the scene of assertion verification, and write corresponding assertion verification code in advance, when the demand of user according to assertion verification, instantiation is carried out according to the code of user's input to the template corresponding with its demand selected, and the code after instantiation is tied to corresponding module, obtain assertion verification simulation document.
Compared with prior art, owing to need not develop assertion verification code temporarily, and get with the instantiation of code, substantially increase in project development process the binding speed asserted between Validation Code and module, ensure that project process, simultaneously can also when not affecting project process for project provides quality assurance.Reduce the use restriction threshold based on the checking of asserting, promote the range of application based on the checking of asserting.
Accompanying drawing explanation
Fig. 1 represents the schematic flow sheet of the method for the embodiment of the present invention;
Fig. 2 represents the structural representation of the device of the embodiment of the present invention.
Embodiment
In the method that the automatic generation of the embodiment of the present invention is asserted and device, by pre-setting multiple template of asserting, user to arrange according to checking demand design under test and to select assert that template carries out instantiation after, can directly according to asserting to this selection, instantiation parameter asserts that assertion verification code corresponding to template carries out instantiation, and the assertion verification code after instantiation is tied to described design under test, obtain assertion verification simulation document, reduce the use difficulty of Assertion (asserting) code, ensure that project process.
The method that a kind of automatic generation of the embodiment of the present invention is asserted, assert code comprise as shown in Figure 1 for generating for a design under test:
First exports step 11, exports user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification;
Instantiating step 12, what input at described instantiation interface according to user asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation;
Binding step 13, the first assertion verification code of described instantiation is tied to described design under test by the module information of the design under test inputted according to described user, obtains assertion verification simulation document.
In the embodiment of the present invention, multiple template is taken out in advance according to the scene of assertion verification, and write corresponding assertion verification code in advance, when the demand of user according to assertion verification, instantiation is carried out according to the code of user's input to the template corresponding with its demand selected, and the code after instantiation is tied to corresponding module, obtain assertion verification simulation document.
Compared with prior art, owing to need not develop assertion verification code temporarily, and get with the instantiation of code, substantially increase in project development process the speed and efficiency of applying assertion verification code, ensure that project process, simultaneously can also when not affecting project process for project provides quality assurance.Reduce the use restriction threshold based on the checking of asserting, promote the range of application based on the checking of asserting.
In a particular embodiment of the present invention, that preserves in advance asserts that template can be divided into the template of asserting for timing verification asserting template and Second Type for Numerical Validation of the first kind, as follows to some of them typical template brief description in the template of this two type below.
The template > that asserts for Numerical Validation of the < first kind
Normal true Always template, code corresponding to this template is for verifying whether object to be verified is true always;
Normal false Never template, code corresponding to this template is for verifying whether object to be verified is false always;
Constant value Always_Value template, code corresponding to this template is for verifying whether object to be verified is a certain particular value always;
Single true One-Hot template, code corresponding to this template is for verifying whether object to be verified only has one to be true;
Single false One-Cold template, code corresponding to this template is for verifying whether object to be verified only has one to be false;
In fact above-mentioned single true One-Hot template and single false One-Cold template can use a template to realize, and inputted, can also be used for verifying that figure place true/false in object to be verified is odd/even etc. by target to be detected by user.
Successive value scope Value_Range template, code corresponding to this template is for verifying whether the value of object to be verified is positioned at a scope;
Range of discrete values V_Inside template, code corresponding to this template is for verifying whether the value of object to be verified is arranged in one of the discrete value of regulation;
Value change V_Value_Chg template, code corresponding to this template is for verifying the variation tendency (as increase progressively, successively decrease) of the value of object to be verified;
Certainly, above template is only citing, the specific embodiment of the invention does not limit concrete template, as arranged corresponding code for verifying that figure place true/false in object to be verified is the template etc. of odd/even, does not describe in detail one by one at this to all templates.
Instantiation parameter is asserted below for this template illustrated example interface of value scope V_Value wherein and correspondence.
User select this template of V_Value (certainly can also to template name (being assumed to v_hdmi_data) to be instantiated after, what namely occur that this template of V_Value needs to carry out instantiation asserts instantiation parameter, comprising:
Width parameter Width, the bit wide of the examined signal of definition, as user inputs 16, then represents that the bit wide of examined signal is 16bit.
Range parameter Range, the variation range of the examined signal of definition, as user's input [0,255], then represents that the variation range of examined signal is [0,255];
Clock signal parameter Clk, defines the internal clock signal for examined signal of sampling, and for sampling to examined signal, as user inputs pix_clk, then represents and utilizes the pix_clk signal of design under test to carry out the sampling of examined signal;
Verify enable parameter Chk_En, definition checks enable signal, carries out assertion verification inspection when only having this signal to be high, as user inputs resetn, then represents and carries out assertion verification inspection when the resetn signal of design under test is high;
Sample event parameter s p_evt, definition sample event signal, starts to carry out assertion verification inspection after this signal occurs, as user inputs pix_en, then carries out assertion verification inspection when representing after the pix_en signal appearance of design under test;
Target component expr, the signal of definition examine or expression formula, as user inputs pix_data, then represent that examined signal is the pix_data of design under test.
The template > that asserts for timing verification of < Second Type
Because timing verification is more complicated relative to Numerical Validation, be therefore difficult to use limited template to carry out accurate corresponding with application scenarios.Inventor, by analyzing various sequential scene, concludes SVA temporal specification grammer, following two the basic assertion verification templates for timing verification of creationary proposition:
S_sequence template; With
S_seq_expr template.
Wherein:
S_sequence template is abstract is sp_evtol_mode (event1rl_modeevent2) rp_mode, and s_seq_expr template is the simple version of s_sequence template, abstract is sp_evtol_modeevent, and defined sequence can be nested in inside other sequence, the convenient sequential inspection generating complexity.
Parameter declaration in template is as follows:
Sample event parameter s p_evt, for defining sample event signal, have sp_evt occur after just carry out subsequent examination; As user inputs pix_en, then represent and utilize the pix_en signal of design under test to carry out the sampling of examined signal;
Contain mode parameter ol_mode, for defining Overlapmode, being used to specify after sp_evt occurs is that to contain overlapping pattern be also non-ly contain non-overlapping pattern;
Target component event1, for another template of asserting for timing verification of the signal expression or instantiation that define first examine; As user inputs vsync, then represent that one of them examined signal is the pix_data of design under test;
Target component event2, for define second examine signal expression or or another template of asserting for timing verification of instantiation; As user inputs vsync_out, then represent that one of them examined signal is the vsync_out of design under test;
Sequential relationship mode parameter rl_mode, for defining the sequential relationship pattern between event1 and event2, can be one of following: " ##n, and, or, intersect, troughout, within " etc.; As user inputs ##2, then represent that the sequential relationship between event1 and event2 is delay 2 clock units, cross-mode, passes through pattern etc.
Repeat pattern parameter rp_mode, is used to specify the repeat pattern of (event1rl_modeevent2), comprises continuous mode and non-continuous mode etc., can be one of following: " [* n]; [* m:n], [-> n], [=n] ".
Certainly, can also comprise:
Clock signal parameter Clk, defines the internal clock signal for examined signal of sampling, and for sampling to examined signal, as user inputs pix_clk, then represents and utilizes the pix_clk signal of design under test to carry out the sampling of examined signal;
Disable parameter, the signal that assertion verification checks is closed in definition, as user's input! Resetn, then represent and utilize design under test! Resetn signal judges whether to close assertion verification inspection;
On_off parameter, defines the switch whether this template generates final checking, as user inputs on, then represents the switch needing to generate final checking.
Should be understood that, the instantiation parameter of above-mentioned template only illustrates, the embodiment of the present invention is not limited to above template, is also not limited to above instantiation mode.
As everyone knows, it is the checking carrying out certain project for certain object in module based on the checking of asserting, and object and project are realized by instantiation, this will illustrate later, and be realize by code being bound Bind to module for module, before binding it to module, need user to specify corresponding module, therefore in a particular embodiment of the present invention, also comprise:
Second exports step, exports one and supplies user to input the module information inputting interface of described module information.
In a particular embodiment of the present invention, this module information inputting interface comprises following parameter:
Authenticating documents name parameter, is used to specify the title of assertion verification simulation document;
RTL file name parameter, is used to specify the RTL file that assertion verification simulation document is corresponding;
Module name parameter, is used to specify module to be verified in RTL file;
Module parameter, records the parameter of module to be verified;
Assert and macroparameter be used to specify the emulation based on the checking of asserting controlling in simulations whether to carry out current block; In simulation process, by this grand work controlling assertion verification simulation document whether user can;
Simulation model parameter, is used to specify simulation model, comprising: ASIC pattern and FPGA pattern.
Binding pattern parameter, is used to specify binding pattern parameter, comprises and is tied to module Module and is tied to these two kinds of patterns of Instance (example);
Bound targets parameter, for selecting bound object according to binding pattern.
In a particular embodiment of the present invention, above-mentioned module information inputting interface and described instantiation interface can be realized by various mode, but consider the convenience of realization, and described module information inputting interface and described instantiation interface are realized by Excel.
To above-mentioned instantiation process and after determining module to be verified, just need the module code of instantiation being tied to needs checking, when binding, first need to know that the code of this instantiation needs to be tied to which module, this can by module information (module corresponding to be verified) described in the acquisition of information of parsing Excel module information inputting interface.
In the process of instantiation, (may be individual signals by the signal of the signal of template inside and module-external, also may be the expression formula comprising multiple signal, this depends on the project of checking) connect, but the signal of this module-external can only be come from module to be verified.
Therefore, when the signal of module-external is not in signal list, then assertion verification simulation document will report an error in simulation process, can check instantiation process by reminding user, finally obtains correct assertion verification simulation document.
Port list in RTL file and signal list are a part of contents code being tied to design under test.
Consider as above 2 points, also comprise in binding step:
By resolving the RTL file in described module information, obtain the port list in described RTL file and signal list.
After completing above-mentioned two steps, according to described module information and described port list and signal list, the assertion verification code of described instantiation can be tied to described design under test.
In a particular embodiment of the present invention, RTL file can be resolved by three scanning algorithms and obtain above-mentioned port list and signal list.
Below to how utilizing three scanning algorithms to be described in detail as follows to resolve RTL file:
By resolving the RTL file in described module information, obtain port list in described RTL file and signal list specifically comprises:
Delete all comment statements in described RTL file, generate the first temporary file; Wherein comment statement comprises row annotation, namely (// ...) and block annotation (that is :/* ... * /);
First temporary file is scanned, only retains the statement that simulation model that described simulation model parameter specifies is corresponding, obtain the second temporary file; As selected ASIC pattern, then the statement that have " ifdefFPGA...endif " comprised is needed to delete;
Described second temporary file is scanned, obtains final port list and signal name list.
Consider and assert and be that is difficult to the imperfection of template list the module that can complete all checkings based on asserting, in a particular embodiment of the present invention, a reserve area is set in the described checking simulation document of generation.
This reserve area is for preserving the second assertion verification code, and this second assertion verification code can be the assertion verification code that user adds when validation template cannot satisfy the demands.And this reserve area is set to non-renewable state simultaneously.
By above-mentioned setting, when the first assertion verification code is made mistakes, when the assertion verification simulation document obtained based on the method for the embodiment of the present invention reports an error in simulation process, user can return the amendment carrying out instantiation process, now can obtain the 3rd new assertion verification code, now just can cover the first assertion verification code, assertion verification simulation document after final updated comprises the 3rd assertion verification code and the second assertion verification code, and the second assertion verification code can not be override, avoid user and again write this second assertion verification code, save user time.
The method of the embodiment of the present invention is described with an actual example below.
First, the method for the embodiment of the present invention needs to provide a Simulation Control grand, assuming that as follows: `ifdefHDMI_ASSERTION;
Secondly, an Aseertion module can be generated according to the module information parsed and the list of RTL signal, as follows:
Then write the User Defined code being saved in reserve area according to the actual requirements, an example is as follows:
//####ASSERTIONFIXEDAREABEGIN####
wirepix_en＝hsync&vsync；
//####ASSERTIONFIXEDAREAEND####
After this, carry out the process of instantiation, as follows:
So far the example of template terminates.
Finally will assert that template and RTL module are bound after example, code is as follows:
At this, should be noted that, in the embodiment of the present invention, surface is it is seen that in instantiation interface input assertion instantiation parameter, establish and assert contacting between the signal of template inside and external signal, but this contact being finally for asserting that code corresponding to template carries out instantiation to this, and is tied to corresponding module, making to assert that code corresponding to template becomes and finally can certain object (signal or signal expression) in a certain module being verified.
The embodiment of the present invention additionally provides the device that a kind of automatic generation is asserted, as shown in Figure 2, comprising:
First output module, for exporting user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification;
For what input at described instantiation interface according to user, instantiation module, asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation;
Binding module, the first assertion verification code of described instantiation is tied to described design under test by the module information for the design under test inputted according to described user, obtains assertion verification simulation document.
Above-mentioned device can also comprise:
Second output module, supplies user to input the module information inputting interface of described module information for exporting one.
In the specific embodiment of the invention, consider the convenience of realization, described module information inputting interface and described instantiation interface are realized by Excel.
Described binding module specifically comprises:
First resolution unit, for module information described in the acquisition of information by resolving Excel module information inputting interface;
Second resolution unit, for resolving the RTL file in described module information, obtains the port list in described RTL file and signal list;
Integral unit, for being tied to described design under test according to described module information and described port list and signal list by the assertion verification code of described instantiation.
Above-mentioned device, wherein, described second resolution unit specifically comprises:
Deleting subelement, for deleting all comment statements in described RTL file, generating the first temporary file;
First scanning subelement, for scanning the first temporary file, only retaining the statement of specifying simulation model corresponding, obtaining the second temporary file;
Second scanning subelement, for scanning described second temporary file, obtains final port list and signal name list.
Described checking simulation document comprises one for preserving the second assertion verification code, and is set to the reserve area of non-renewable state.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (12)
1. automatically generate the method asserted, it is characterized in that, comprising:
First exports step, exports user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification;
Instantiating step, what input at described instantiation interface according to user asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation;
Binding step, first assertion verification code of described instantiation is tied to described design under test by the module information of the design under test inputted according to described user, obtain assertion verification simulation document, make to assert that code corresponding to template can be verified the object in design under test;
Described design under test is the module in RTL file.
2. method according to claim 1, is characterized in that, also comprises:
Second exports step, exports one and supplies user to input the module information inputting interface of described module information.
3. method according to claim 2, is characterized in that, described module information inputting interface and described instantiation interface are realized by Excel.
4. method according to claim 3, is characterized in that, described binding step specifically comprises:
First analyzing step, by module information described in the acquisition of information of resolving Excel module information inputting interface;
Second analyzing step, resolves the RTL file in described module information, obtains the port list in described RTL file and signal list;
Integration step, is tied to described design under test according to described module information and described port list and signal list by the assertion verification code of described instantiation.
5. method according to claim 4, is characterized in that, the second analyzing step specifically comprises:
Delete step, deletes all comment statements in described RTL file, generates the first temporary file;
First scanning step, scans the first temporary file, only retains the statement of specifying simulation model corresponding, obtains the second temporary file;
Second scanning step, scans described second temporary file, obtains final port list and signal name list.
6. method according to claim 1, is characterized in that, described checking simulation document comprises one for preserving the second assertion verification code, and is set to the reserve area of non-renewable state.
7. automatically generate a device of asserting, it is characterized in that, comprising:
First output module, for exporting user from multiple instantiation interface of asserting the target asserts template selected template of preserving in advance; Eachly assert that template corresponds to one for the assertion verification code of functional verification;
For what input at described instantiation interface according to user, instantiation module, asserts that instantiation parameter carries out instantiation to described assertion verification code, obtains the first assertion verification code of instantiation;
Binding module, first assertion verification code of described instantiation is tied to described design under test by the module information for the design under test inputted according to described user, obtain assertion verification simulation document, make to assert that code corresponding to template can be verified the object in design under test;
Described design under test is the module in RTL file.
8. device according to claim 7, is characterized in that, also comprises:
Second output module, for exporting the module information inputting interface inputting described module information for user.
9. device according to claim 8, is characterized in that, described module information inputting interface and described instantiation interface are realized by Excel.
10. device according to claim 9, is characterized in that, described binding module specifically comprises:
First resolution unit, for module information described in the acquisition of information by resolving Excel module information inputting interface;
Second resolution unit, for resolving the RTL file in described module information, obtains the port list in described RTL file and signal list;
Integral unit, for being tied to described design under test according to described module information and described port list and signal list by the assertion verification code of described instantiation.
11. devices according to claim 10, is characterized in that, described second resolution unit specifically comprises:
Deleting subelement, for deleting all comment statements in described RTL file, generating the first temporary file;
First scanning subelement, for scanning the first temporary file, only retaining the statement of specifying simulation model corresponding, obtaining the second temporary file;
Second scanning subelement, for scanning described second temporary file, obtains final port list and signal name list.
12. devices according to claim 7, is characterized in that, described checking simulation document comprises one for preserving the second assertion verification code, and is set to the reserve area of non-renewable state.
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| CN105760612B (en) * | 2016-02-26 | 2018-12-04 | 中国科学院计算技术研究所 | Detection device, method, system, chip are asserted for chip checking after silicon |
| CN111615688A (en) * | 2019-05-28 | 2020-09-01 | 深圳市大疆创新科技有限公司 | Assertion verification code binding method and device |
| US11953887B2 (en) * | 2019-09-27 | 2024-04-09 | Rockwell Automation Technologies, Inc. | System and method for customer-specific naming conventions for industrial automation devices |
| CN115098400B (en) * | 2022-07-19 | 2022-12-06 | 北京航空航天大学 | FPGA software simulation test environment establishment method based on SVA formal verification |
| CN114924992B (en) * | 2022-07-20 | 2022-11-15 | 北京航空航天大学 | Formalized FPGA software security verification method and verification system |
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| CN102841841A (en) * | 2011-06-20 | 2012-12-26 | 阿里巴巴集团控股有限公司 | Method and system for processing assertion in test |
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| CN102402628A (en) * | 2010-09-07 | 2012-04-04 | 无锡中星微电子有限公司 | Method and system for generating systems-on-a-chip (SoC) verification platform |
| CN102841841A (en) * | 2011-06-20 | 2012-12-26 | 阿里巴巴集团控股有限公司 | Method and system for processing assertion in test |
| CN102662657A (en) * | 2012-03-19 | 2012-09-12 | 苏州芯禾电子科技有限公司 | Port network parameter simulation software design method based on visualization operation |
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