CN106295048A - A kind of digit chip function verification method and system - Google Patents
A kind of digit chip function verification method and system Download PDFInfo
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- CN106295048A CN106295048A CN201610693370.7A CN201610693370A CN106295048A CN 106295048 A CN106295048 A CN 106295048A CN 201610693370 A CN201610693370 A CN 201610693370A CN 106295048 A CN106295048 A CN 106295048A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Abstract
The present invention proposes a kind of digit chip function verification method and system, for solving to verify present in prior art the technical problem that accuracy is low, the present invention considers the impact on the result of application system environmental factors and fault message, and verification method step is: simulation application system environmental information；Simulated failure information；Design specification according to design to be verified generates basic test vector；Environmental information and fault message are integrated with basic test vector；Vector after integrating inputs to design to be verified, obtains output response；Output response is inputed to digit chip functional verification platform, the correctness of inspection output response, draws checking conclusion；Checking system includes end to end digit chip functional verification platform and design to be verified, digit chip functional verification platform outfan is connected with integration module, integrate module input connection and have application system environmental information analog module and fault message analog module, integrate module outfan and be connected to design input to be verified.
Description
Technical field
The invention belongs to digit chip checking field, relate to a kind of number considering application system environmental factors and fault message
Word chip functions verification method and system, can be used for the technical field relevant to digit chip.
Background technology
In integrated circuit design, the design specification describing chip functions and specifications parameter is normally used as designing starting point,
And based on this design specification, designer can use the hardware description languages such as Verilog, VHDL (HDL) subsequently, pass at depositor
On defeated level (RTL) this levels of abstraction, design is realized.Design result would generally present with the form of HDL code,
HDL code will describe how chip operates data, enables data to correctly at input, output and the clock of circuit
Flow between depositor.Chip must be verified after having designed, and the main task of chip checking uses machine language exactly
Build software test platform (Testbench) and check whether HDL code or gate level circuit netlist meet all of design rule
Model.
Chip checking is in a chip design in occupation of considerable effect, and it has been increasingly becoming the bottle of launch
Neck.In chip design stage, if not done by sufficient functional verification, the leak in the presence of design is difficult to below
Physical design phase is found, and can only after flow just can tested out, this results in the serious soaring of design cost
Delay with chip Time To Market.Therefore, consider from the angle of cost and Time To Market, find that leak exists by chip checking
In whole design cycle most important.
The design space of chip often exists recessive leak, the signal matter that these recessive leaks receive at chip interface
Will not embody when measuring normal.But, along with modern Electronic Design and the very fast development of chip fabrication techniques, electronic product
Complexity, clock and bus frequency etc. all in rapid increase trend, the problems of Signal Integrity of High Speed System highlights day by day, core
Application system environment during sheet work is the most severe.Chip is the most no longer more at the signal that its seam is an actually-received
Preferably signal, and be affected by the impact of application system environment, becomes and there is the signal integrity such as relative time delay or pulse and ask
The signal of topic.At this moment, the recessive leak that will not be embodied as out when interface signal quality is normal will be excited, thus causes
Chip failure and its due characteristic cannot be embodied, more serious also result in whole Circuits System and cannot work.This is just
Require just should find this recessive leak ahead of time when the functional verification of digit chip, avoid further losing to cause.
Existing digit chip function verification method comprises the following steps: step one, for setting of design to be verified (DUV)
Meter specification information, generates test vector according to its interface；Step 2, test vector step one generated is applied to connecing of DUV
On mouth, and catch the output response of DUV；Step 3, the correctness of the output response data of inspection DUV, draw checking conclusion.Depend on
According to existing verification method, do not consider application system environment and the impact of fault message during chip operation when checking,
Therefore the signal being applied to DUV interface is ideal signal, does not consider that chip institute under complicated applications system environments may meet
The problems of Signal Integrity arrived, so that the checking accuracy of chip is low.This is it is possible to can cause after verifying, chip
Present in design, recessive leak is not found, then also bring hidden danger with actually used to the test of chip.
Summary of the invention
It is an object of the invention to overcome above-mentioned the deficiencies in the prior art, it is provided that a kind of digit chip function verification method
And system, for solving to verify present in prior art the technical problem that accuracy is low.
For achieving the above object, the technical solution used in the present invention is as follows:
A kind of digit chip function verification method, comprises the following steps:
(1) application system environmental information during application system environmental simulation module simulation chip operation to be verified, the amount of obtaining
Application system environmental information after change；
(2) fault message that fault message analog module is likely to occur when simulating chip operation to be verified, after being quantified
Fault message；
(3) digit chip functional verification platform generates basic test vector according to the design specification information of design to be verified；
(4) module is integrated by the quantified application system environmental information obtained in step (1) and step (2) and fault
Information is added in step (3) the basic test vector obtained, and obtains final test vector；
(5) integrate module and the final test vector obtained in step (4) is inputed to the input of design to be verified, obtain
The output response of design to be verified；
(6) digit chip functional verification platform obtains the output response of design to be verified, and checks this output just responding
Really property, draws checking conclusion.
A kind of digit chip functional verification system, including end to end digit chip functional verification platform with to be verified set
Meter, wherein:
Digit chip functional verification platform, generates basic test vector for the design specification according to design to be verified, and
Catch the output response of design to be verified, check the correctness of design output response to be verified simultaneously；
Design to be verified, for receiving the output vector integrating module, obtains output response；
It is connected between outfan and the input of design to be verified of described digit chip functional verification platform and has integration mould
Block, the input of this integration module connects application system environmental information analog module and fault message analog module, wherein, should
The application system environment of analog chip it is used for, the application system environment letter after generating quantification with system environmental information analog module
Breath；Fault message analog module, the fault message being likely to occur when analog chip works, the fault letter after generating quantification
Breath；Integrate module for by digit chip functional verification platform, application system environmental simulation module and fault message analog module
The information exported is integrated.
Above-mentioned digit chip functional verification system, described digit chip application system environmental simulation module, including phase successively
Hypothesis testing vector output interface module even, application system environmental information generation module, chip model input interface to be verified
Module and threshold value thresholding modular converter, wherein:
Hypothesis testing vector output interface module, for using the corresponding interface model to design conveying excitation to be verified
Chip interface is simulated, and exports the analogue signal meeting this chip output interface characteristic；
Application system environmental information generation module, for the application system environment of design to be verified is simulated, and will
The system environmental information produced is added in the analogue signal of hypothesis testing vector output interface module output；
Chip model input interface module to be verified, for carrying out the input interface of design to be verified by interface model
Simulation, and receive the signal of application system environmental information generation module output, output meets design input interface characteristic to be verified
The analogue signal comprising applied environment information；
Threshold value thresholding modular converter, is used for the threshold value threshold voltage according to interface by chip model input interface to be verified
The analogue signal that module is exported is converted to digital signal.
Above-mentioned digit chip functional verification system, described digit chip functional verification platform, refer to based on various authentications
The software verification platform that the science of law is built.
Above-mentioned digit chip functional verification system, described design to be verified, refer to the depositor of digit chip to be verified
Transmitting stage model or behavioral scaling model or comprehensive network list file.
The present invention compared with prior art, has the advantage that
Due to the fact that when digit chip functional verification, by application system environments and the simulation of fault message,
Make the input vector of design to be verified in addition to basic test vector information, also comprise environmental information and fault message, can
Effectively to find recessive leak present in some chips, thus the checking to numeral chip functions is more comprehensive, with existing
Technology is compared, and improves accuracy and the credibility of digit chip functional verification.
Accompanying drawing explanation
Fig. 1 be verification method of the present invention realize FB(flow block)；
Fig. 2 is the structural representation that the present invention verifies system；
Fig. 3 is the structural representation of application system environmental information analog module of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is more specifically described.
Referring to the drawings 1:
The digit chip function verification method of the present invention simulates its real system by certain method and software emulation
The impact of the desired excitation that environment and fault message docking port receive, is brought system environmental information and fault message
Problems of Signal Integrity be incorporated in basic test vector, thus to comprise the test of system environmental information and fault message
Vector verifies sequential and the correctness of function of design to be verified (DUV), specifically comprises the following steps that
Application system environmental information during step 1. application system environmental simulation module simulation chip operation to be verified, obtains
Application system environmental information after quantization.
Step 1a. application system environmental simulation module is according to the design on board level file of application system and this application system inner core
The interface model of sheet design, utilizes signal integrity simulation instrument to simulate the impact on input signal of the application system environment, obtains
The analog signal waveform received at design input interface to be verified.
This step specific practice is: first get out applied system design file, Yi Jiying according to the emulation tool used
Interface model with chips all in system.The PCB SI software and the Sigrity software that use Cadence company in the present invention are made
For signal integrity simulation instrument, therefore the PCB layout file of brd form and the IBIS model of respective chip should be got out.Accurate
After Bei, emulation tool load the IBIS model of chip, and simulation parameter and observed parameter are set.It is after setting completed
Application system environments emulation be can be simulated, the analog signal waveform at DUV input interface and related data obtained the most at last
Report.Its DUV can be the register transfer level model of chip to be verified, behavioral scaling model or comprehensive network list file.
Step 1b. application system environmental simulation module according to the signal threshold value threshold voltage of design input interface to be verified,
Utilize signal crossover tool, the analog signal waveform obtained is converted to digital signal waveform, and extracts this digital signal waveform
Characteristic information.
This step specific practice is: first have to the analog signal waveform obtained in step 1a is imported to Synopsys company
Hspice software in, this utilizes the S parameter model of application system that signal integrity simulation instrument generates and chip to connect
The IBIS model of mouth can realize.In HSpice, edit circuit code, add threshold according to the threshold voltage value of DUV input interface
Value translation buffer, is converted to digital signal waveform by analog signal waveform.From the numeral letter of performance application system environmental information
In number waveform, easily extract and obtain the characteristic informations such as the relative time delay of signal, pulse position, pulse width, number of pulses.
The fault message that step 2. fault message analog module is likely to occur when simulating chip operation to be verified, is quantified
After fault message.
Fault message in this step refers to some the outburst surroundings information, such as thunder being likely to occur during chip operation
The impact of the desired excitation that chip interface is received by these information of electricity, ionizing radiation, high pressure etc..Specific practice is: by mould
The fault message signal intended imports to, in signal integrity simulation instrument, convert analog signals into digital signal.From this numeral
Signal waveform carries the characteristic informations such as the relative time delay of signal, pulse position, pulse width, number of pulses.
Step 3. digit chip functional verification platform according to the design specification information of design to be verified generate basic test to
Amount.
This step is particularly as follows: according to the design specification of DUV, use the high level of authentication such as rudimentary orientation test or VVM, UVM
Methodological mode, generates specific or random test vector.
Step 4. integrates module by the quantified application system environmental information obtained in step 1 and step 2 and fault
Information is added to the basic test vector obtained in step 3, obtains final test vector.
The process integrated in this step can be accomplished manually by engineer, it is also possible to design program uses test platform automatic
Complete.Illustrating, such as obtain at preferable test vector output interface is preferable high level signal, by above step
Rapid enforcement can obtain comprising the system environmental information through quantifying, and system environmental information is mainly the relative time delay of signal, arteries and veins
Rush the characteristic informations such as position, pulse width, number of pulses.Assume the environmental information after being quantified to show as in 0 moment to start
The short negative pulse of one 3ns occurs, then at rear 10ns in the basic test vector produced by digit chip software verification platform
High level signal after, the short negative pulse of this 3ns is incorporated in the high level signal of this basic test vector.Equally, fault
Information is integrated the most in the same way with basic test vector.Then the final test vector after integrating is sent to chip to be verified
Model is verified.
Step 5. is integrated module and the final test vector obtained in step 4 is inputed to the input of design to be verified,
Output to design to be verified responds.
Step 6. digit chip functional verification platform obtains the output response of design to be verified, and checks this output to respond
Correctness, draws checking conclusion.
Referring to the drawings 2:
The digit chip functional verification system of the present invention, including end to end digit chip functional verification platform and to be tested
Card design, wherein:
Digit chip functional verification platform, generates basic test vector for the design specification according to design to be verified, and
Catch the output response of design to be verified, check the correctness of design output response to be verified simultaneously.
This digit chip software verification platform comprises the function of traditional test platform (Testbench), can be to comprise
The software verification platform being built into based on various verification methodology means.Such as, this platform can use Verilog HDL or VHDL
Hardware description language is write, and produces orientation test vector or random test vector, it is possible to use System Verilog or
The OO high abstraction hierarchy language such as System C combine the methodologies such as VVM, UVM and write, and produce and orient test accordingly
Vector or random test vector.
The interface model of plate level applied system design file and related chip is inputted digit chip application system simulation mould
Block, this module will application system environmental information after generating quantification, the fault letter being likely to occur during analog chip work simultaneously
It is also quantified by breath, then system environmental information, fault message and basic test vector is integrated, finally by whole
Final test vector after conjunction inputs the interface of design to be verified (DUV).Finally, digit chip functional simulation verification platform will be caught
Catch the output response of DUV and check the correctness of DUV output response, exporting the result data report, draw checking conclusion.
Design to be verified, refers to the register transfer level model of digit chip to be verified or behavioral scaling model or comprehensive network
List file, for receiving the output vector integrating module, obtains output response.
It is connected between the outfan of digit chip functional verification platform and the input of design to be verified and has integration module, should
The input connection integrating module has application system environmental information analog module and fault message analog module, wherein, application system
System environmental information analog module is for the application system environment of analog chip, the application system environmental information after generating quantification；Therefore
Barrier information simulation module, the fault message being likely to occur when analog chip works, the fault message after generating quantification；Integrate
Module is for being exported digit chip functional verification platform, application system environmental simulation module and fault message analog module
Information is integrated.
Referring to the drawings 3:
Application system environmental information analog module of the present invention, including the hypothesis testing vector output interface mould being sequentially connected
Block, application system environmental information generation module, chip model input interface module to be verified and threshold value thresholding modular converter.
Hypothesis testing vector output interface module, the chip using corresponding IBIS model to simulate to DUV conveying excitation connects
Mouthful, and export the analogue signal of the output interface characteristic meeting this chip；Application system environmental information generation module, is used for simulating
The application system environment of DUV, the analogue signal to the output of test vector output interface module adds application system environmental information；Treat
Proofing chip mode input interface module, uses corresponding IBIS model to simulate the input interface of DUV, receives application system environment
The signal of information-generation module output, output meets the analogue signal comprising applied environment information of DUV input interface characteristic；Threshold
Value thresholding modular converter, for export chip model input interface module to be verified according to the threshold value threshold voltage of interface
Analogue signal is converted to digital signal.
Claims (7)
1. a digit chip function verification method, it is characterised in that comprise the following steps:
(1) application system environmental information during application system environmental simulation module simulation chip operation to be verified, after being quantified
Application system environmental information；
(2) fault message that fault message analog module is likely to occur when simulating chip operation to be verified, the event after being quantified
Barrier information；
(3) digit chip functional verification platform generates basic test vector according to the design specification information of design to be verified；
(4) module is integrated by the quantified application system environmental information obtained in step (1) and step (2) and fault message
It is added in step (3) the basic test vector obtained, obtains final test vector；
(5) integrate module and the final test vector obtained in step (4) is inputed to the input of design to be verified, obtain to be tested
The output response of card design；
(6) digit chip functional verification platform obtains the output response of design to be verified, and checks the correctness that this output responds,
Draw checking conclusion.
Digit chip function verification method the most according to claim 1, it is characterised in that the quantization described in step (1)
After application system environmental information and fault message after the quantization described in step (2), including relative time delay, the pulse of signal
Position, pulse width, number of pulses information.
Digit chip function verification method the most according to claim 1, it is characterised in that the simulation described in step (1) is treated
Application system environmental information during proofing chip work, it is achieved step is:
(1a) application system environmental simulation module is according to the design on board level file of application system and chip design in this application system
Interface model, utilize signal integrity simulation instrument simulate the impact on input signal of the application system environment, obtain to be verified
The analog signal waveform received at design input interface；
(1b) application system environmental simulation module is according to the signal threshold value threshold voltage of design input interface to be verified, utilizes signal
Crossover tool, is converted to the analog signal waveform obtained digital signal waveform, and extracts the feature letter of this digital signal waveform
Breath.
4. a digit chip functional verification system, it is characterised in that include end to end digit chip functional verification platform
With design to be verified, wherein:
Digit chip functional verification platform, generates basic test vector for the design specification according to design to be verified, and catches
The output response of design to be verified, checks the correctness of design output response to be verified simultaneously；
Design to be verified, for receiving the output vector integrating module, obtains output response；
It is characterized in that, being connected between outfan and the input of design to be verified of described digit chip functional verification platform has
Integrating module, the input of this integration module connects application system environmental information analog module and fault message analog module,
Wherein, application system environmental information analog module is for the application system environment of analog chip, the application system after generating quantification
Environmental information；Fault message analog module, the fault message being likely to occur when analog chip works, the event after generating quantification
Barrier information；Integrate module for digit chip functional verification platform, application system environmental simulation module and fault message being simulated
The information that module is exported is integrated.
Digit chip functional verification system the most according to claim 4, it is characterised in that described digit chip application system
Environmental simulation module, including the hypothesis testing vector output interface module being sequentially connected, application system environmental information generation module,
Chip model input interface module to be verified and threshold value thresholding modular converter, wherein:
Hypothesis testing vector output interface module, for using the corresponding interface model to the chip to design conveying excitation to be verified
Interface is simulated, and exports the analogue signal meeting this chip output interface characteristic；
Application system environmental information generation module, for being simulated the application system environment of design to be verified, and will produce
System environmental information add to hypothesis testing vector output interface module output analogue signal in；
Chip model input interface module to be verified, for carrying out mould by interface model to the input interface of design to be verified
Intending, and receive the signal of application system environmental information generation module output, output meets design input interface characteristic to be verified
Comprise the analogue signal of applied environment information；
Threshold value thresholding modular converter, is used for the threshold value threshold voltage according to interface by chip model input interface module to be verified
The analogue signal exported is converted to digital signal.
Digit chip functional verification system the most according to claim 4, it is characterised in that described digit chip functional verification
Platform, refers to the software verification platform built based on various verification methodologies.
Digit chip function verification method the most according to claim 4, it is characterised in that described design to be verified, be
Refer to the register transfer level model of digit chip to be verified or behavioral scaling model or comprehensive network list file.
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| CN107608845A (en) * | 2017-08-18 | 2018-01-19 | 北京摩拜科技有限公司 | Test method for hardware, apparatus and system |
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