CN117034841B

CN117034841B - Method, computing equipment and medium for digital-analog hybrid simulation verification

Info

Publication number: CN117034841B
Application number: CN202311298047.6A
Authority: CN
Inventors: 施立立; 雍超
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2023-10-09
Filing date: 2023-10-09
Publication date: 2024-02-09
Anticipated expiration: 2043-10-09
Also published as: CN117034841A

Abstract

The application relates to the technical field of computers and provides a method, computing equipment and medium for digital-analog hybrid simulation verification. The method comprises the following steps: performing first-stage simulation verification on the first chip design through a first digital simulation verification environment to obtain a first simulation verification result; performing second-stage simulation verification on the first chip design through a second digital simulation verification environment to obtain a second simulation verification result; performing third-stage simulation verification on the first chip design through the first digital-analog hybrid simulation verification environment to obtain a third simulation verification result; performing fourth-stage simulation verification on the first chip design through a second digital-analog hybrid simulation verification environment to obtain a fourth simulation verification result; and generating a digital-analog hybrid simulation verification result of the first chip design based on the simulation verification results. Thus, the simulation time is shortened and the response speed is improved.

Description

Method, computing equipment and medium for digital-analog hybrid simulation verification

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method, a computing device, and a medium for digital-analog hybrid simulation verification.

Background

In the prior art, system-on-chip generally includes digital circuits and analog circuits, such as digital signal processors and analog radio frequency circuits, and employs digital-analog mixed signals. Therefore, the digital circuit and the analog circuit are respectively designed and simulated in the chip design link, and then the digital circuit and the analog circuit are combined for digital-analog hybrid simulation verification. Because the digital circuit and the analog circuit have differences in the aspects of control mechanism, simulation model, simulation tool and the like, the digital-analog hybrid simulation verification has the problems of low simulation speed, low verification efficiency, high cost and the like, and is not beneficial to realizing the quick response and the quick iteration of the product.

Therefore, the application provides a method, computing equipment and medium for digital-analog hybrid simulation verification, which are used for solving the technical problems in the prior art.

Disclosure of Invention

In a first aspect, the present application provides a method for digital-to-analog hybrid simulation verification. The method comprises the following steps: performing first-stage simulation verification on a first chip design through a first digital simulation verification environment to obtain a first simulation verification result, wherein the first digital simulation verification environment is constructed based on a first register transmission level model associated with a first digital module and a first behavior level model associated with a first analog module, the first digital module and the first analog module belong to the first chip design, the first behavior level model is generated based on a first behavior level description, and the first behavior level description is a behavior level description of a digital-analog interface function of the first analog module; performing second-stage simulation verification on the first chip design through a second digital simulation verification environment to obtain a second simulation verification result, wherein the second digital simulation verification environment is constructed based on the first register transmission stage model and a second behavior stage model associated with the first simulation module, the second behavior stage model is generated based on the first behavior stage description and a second behavior stage description, and the second behavior stage description is a behavior stage description of circuit structure, internal connection relation and real stage information of the first simulation module; performing third-stage simulation verification on the first chip design through a first digital-analog hybrid simulation verification environment to obtain a third simulation verification result, wherein the first digital-analog hybrid simulation verification environment is constructed based on the first register transmission level model and a first hybrid model, and the first hybrid model is generated by replacing a behavior level description associated with at least one single-point function in the second behavior level model with a circuit netlist description; performing fourth-stage simulation verification on the first chip design through a second digital-analog hybrid simulation verification environment to obtain a fourth simulation verification result, wherein the second digital-analog hybrid simulation verification environment is constructed based on the first register transmission level model and a second hybrid model, and the second hybrid model is generated by replacing all behavior level descriptions in the second behavior level model with circuit netlist descriptions; and generating a digital-analog hybrid simulation verification result of the first chip design based on the first simulation verification result, the second simulation verification result, the third simulation verification result and the fourth simulation verification result.

According to the first aspect of the method, the digital-analog hybrid simulation verification scheme for the first chip design is gradually built according to the first-stage simulation verification, the second-stage simulation verification, the third-stage simulation verification and the fourth-stage simulation verification, so that the simulation time of the digital-analog hybrid simulation verification is greatly shortened, various excitation, configuration, verification components and regression tools in a digital simulation verification environment can be fully utilized, the reliability of verification results is improved, the product development time is shortened, and the response speed is improved.

In a possible implementation manner of the first aspect of the present application, the third simulation verification result includes a system level modulo hybrid simulation verification result associated with the at least one single point function.

In a possible implementation manner of the first aspect of the present application, the fourth simulation verification result includes a system level modulo hybrid simulation verification result associated with a complete function of the first chip design.

In a possible implementation manner of the first aspect of the present application, the third simulation verification result further includes simulation verification results of a relationship of the circuit control signal associated with the at least one single point function with respect to the clock frequency under different process angles.

In a possible implementation manner of the first aspect of the present application, the first simulation verification result includes a digital simulation verification result of a digital-to-analog interface function of the first analog module, and the second simulation verification result includes a digital simulation result of a circuit structure and an internal connection relationship of the first analog module.

In a possible implementation manner of the first aspect of the present application, the second simulation verification result further includes real-level information of the voltage and the current of the first simulation module.

In one possible implementation manner of the first aspect of the present application, the first chip design is a receiving end voltage controlled oscillator, the first simulation verification result is associated with a calibration algorithm convergence of the receiving end voltage controlled oscillator, the second simulation verification result is associated with a calibration algorithm convergence of the receiving end voltage controlled oscillator, a built-in self-test module and an analog high-speed calculation logic, the third simulation verification result is associated with a calibration algorithm convergence of the receiving end voltage controlled oscillator, a built-in self-test module, an analog high-speed calculation logic and suitability of the analog high-speed calculation logic with respect to digital logic under different process angles, and the fourth simulation verification result is associated with a calibration algorithm convergence of the receiving end voltage controlled oscillator, a built-in self-test module, an analog high-speed calculation logic, suitability of the analog high-speed calculation logic with respect to digital logic under different process angles and an upper current path of the receiving end voltage controlled oscillator.

In a possible implementation manner of the first aspect of the present application, the digital-analog hybrid simulation verification result of the first chip design includes a plurality of calibration steps associated with a given function of the first chip design, an initial one or more steps of the plurality of calibration steps are covered by the fourth simulation verification result, and remaining steps of the plurality of calibration steps, relative to the initial one or more steps, are covered by the first simulation verification result, the second simulation verification result, and the third simulation verification result.

In a possible implementation manner of the first aspect of the present application, the simulation time of each of the first-stage simulation verification, the second-stage simulation verification, and the third-stage simulation verification is controllable by a preset simulation condition.

In a possible implementation manner of the first aspect of the present application, the first register transfer level model is generated based on a first register transfer level description, the first register transfer level description including a register transfer level code of the first digital module.

In a possible implementation manner of the first aspect of the present application, the first digital module is a digital circuit portion of the first chip design, and the first analog module is an analog circuit portion of the first chip design.

In one possible implementation manner of the first aspect of the present application, the first chip design is a serializer deserializer product, and the first-stage simulation verification, the second-stage simulation verification, the third-stage simulation verification, and the fourth-stage simulation verification are all implemented by a first simulation verification platform, where the first simulation verification platform includes a configuration path component, a flow control component, a parallel port transmitting component, a parallel port checking component, a serial port transmitting component, a circuit key node checking component, a design configuration constraint component to be tested, and an environmental configuration constraint component.

In a possible implementation manner of the first aspect of the present application, the environment configuration constraint component is configured to implement data flow direction control, simulation timeout control, and simulation acceleration control of the first simulation verification platform.

In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a chip design flow including digital-analog hybrid simulation verification;

FIG. 2 is a flow chart of a method for digital-analog hybrid simulation verification according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a simulation verification platform according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

FIG. 1 is a schematic diagram of a chip design flow including digital-analog hybrid simulation verification. As shown in FIG. 1, the chip design flow includes a system plan 102, a digital circuit design 104, an analog circuit design 106, and a digital-to-analog hybrid design 108. The chip design flow shown in fig. 1 refers to the chip front end design. Specifically, the front-end design of the chip is based on specification, and the purpose and the efficiency of the chip, the agreement standards to be met and the like are set, then the functional allocation and the unit division are carried out, and the hardware description language (hardware description language, HDL) such as the common Verilog HDL is used for describing the hardware behavior, the structure and the data flow of the circuit system. The system planning 102 is a specification definition and system design link, and is used for determining a requirement analysis of a chip and determining an overall design direction, for example, determining a cost control level, a power consumption sensitivity degree, a supported connection mode, a system security level and the like, and further determining designs of a chip architecture, a service module, a power supply system and the like, namely, performing function allocation and unit division, for example, determining interaction, a specific interface and the like between various systems. With the greater complexity of chip designs and chip functionality, chip designs, such as system-on-a-chip, typically include digital circuitry and analog circuitry, and employ digital-to-analog mixed signals, such as digital signal processors and analog radio frequency circuitry, and the like. In chip design, digital and analog modules are typically designed and simulated separately because digital and analog circuits differ greatly in circuit principles, design tools, and simulation models. As shown in fig. 1, after system planning 102, digital circuit design 104 and analog circuit design 106 are performed in parallel, or separately. The digital circuit design 104 is used to design and simulate the digital circuit portion of a digital module or chip. The analog circuit design 106 is used for design and simulation verification of analog circuit portions in an analog module or chip. After the digital circuit simulation verification and the analog circuit simulation verification are respectively carried out on the digital module and the analog module, the digital module and the analog module are combined for digital-analog hybrid simulation verification. As shown in fig. 1, a digital-to-analog hybrid design 108 is also performed after the digital circuit design 104 and the analog circuit design 106. The digital-analog hybrid design 108 is used for performing digital-analog hybrid simulation verification on a digital circuit for which the design and simulation verification under the digital circuit design 104 have been completed and an analog circuit for which the design and simulation verification under the analog circuit design 106 has been completed, respectively.

With continued reference to fig. 1, in the chip design flow, the digital-analog hybrid design 108 is critical to ensure that chips produced according to the chip design function properly. As chip functionality becomes more abundant, chip design complexity increases and various heterogeneous computing architectures may be employed within the chip. Therefore, the system-on-chip has wide application in fields such as mobile phones, data centers, intelligent wearable devices and the like. The system-on-chip typically includes digital circuitry and analog circuitry, such as a digital signal processor and analog radio frequency circuitry, and employs digital-to-analog mixed signals. If the mixed simulation of digital and analog is involved in the chip product, the digital and analog are often made to simulate the circuits in the respective fields separately in the early stage of the project, and then the mixed simulation is started to be performed by combining the digital and analog when the circuit design is basically stable in the later stage of the project. One implementation of digital-analog hybrid simulation verification is to mainly use analog requirements and to match digital requirements to generate excitation. For example, advanced Mixed-Signal (AMS) simulators introduce register transfer level (Register Transfer Level, RTL) code of digital circuits into analog circuits through AMS flows, and the simulation model of the analog circuits is built based on netlist descriptions extracted from circuit diagrams. However, AMS or similar analog-to-digital hybrid simulation verification methods based on analog demand and digital matching generate stimulus, so different demands can generate many different verification platforms, resulting in slow simulation speed and difficulty in realizing fast response (time-to-mark) of products. Thus, for long development cycle projects, or small-change projects such as non-customized products or generic products, these chip projects are insensitive to product iteration and response speed. However, for projects with short development period or frequently changed projects such as customized products and products with short market period, the digital-analog hybrid simulation verification mode mainly comprising analog simulation is difficult to meet the project requirements. The other implementation mode of the digital-analog hybrid simulation verification is a digital-analog hybrid simulation verification mode which mainly uses digital requirements and generates excitation according to the analog requirements, namely mainly uses digital simulation. However, in the digital-analog hybrid simulation verification method based on digital simulation, it is necessary to abstract the analog circuit into a circuit model which can be described in a hardware description language, extract timing information of the analog circuit, integrate the timing information with the digital circuit, and verify digital logic correctness and overall digital-analog cooperation logic in the analog circuit. The digital process generally has faster simulation speed than the analog process, and the verification efficiency is reduced and the cost is increased on a large-scale chip project.

Therefore, the application provides a method, computing equipment and medium for digital-analog hybrid simulation verification, which not only utilizes the advantage of high simulation speed of a digital process, but also reduces the influence caused by abstraction and extraction of an analog circuit as much as possible, and has a larger verification range, and can flexibly and comprehensively meet the digital-analog hybrid simulation verification requirements of various chip designs. The following is a detailed description of specific embodiments of the present application.

Fig. 2 is a flow chart of a method for digital-analog hybrid simulation verification according to an embodiment of the present application. As shown in fig. 2, the method includes the following steps.

Step S210: and performing first-stage simulation verification on the first chip design through a first digital simulation verification environment to obtain a first simulation verification result, wherein the first digital simulation verification environment is constructed based on a first register transmission level model associated with a first digital module and a first behavior level model associated with a first analog module, the first digital module and the first analog module belong to the first chip design, the first behavior level model is generated based on a first behavior level description, and the first behavior level description is a behavior level description of a digital-analog interface function of the first analog module.

Step S212: and performing second-stage simulation verification on the first chip design through a second digital simulation verification environment to obtain a second simulation verification result, wherein the second digital simulation verification environment is constructed based on the first register transmission stage model and a second behavior stage model associated with the first simulation module, the second behavior stage model is generated based on the first behavior stage description and a second behavior stage description, and the second behavior stage description is a behavior stage description of circuit structure, internal connection relation and real number stage information of the first simulation module.

Step S214: and performing third-stage simulation verification on the first chip design through a first digital-analog hybrid simulation verification environment to obtain a third simulation verification result, wherein the first digital-analog hybrid simulation verification environment is constructed based on the first register transmission level model and a first hybrid model, and the first hybrid model is generated by replacing a behavior level description associated with at least one single-point function in the second behavior level model with a circuit netlist description.

Step S216: and performing fourth-stage simulation verification on the first chip design through a second digital-analog hybrid simulation verification environment to obtain a fourth simulation verification result, wherein the second digital-analog hybrid simulation verification environment is constructed based on the first register transmission stage model and a second hybrid model, and the second hybrid model is generated by replacing all behavior stage descriptions in the second behavior stage model with circuit netlist descriptions.

Step S218: and generating a digital-analog hybrid simulation verification result of the first chip design based on the first simulation verification result, the second simulation verification result, the third simulation verification result and the fourth simulation verification result.

Referring to fig. 2, in step S210, a first stage of simulation verification is performed on a first chip design by using a first digital simulation verification environment to obtain a first simulation verification result. The first digital simulation verification environment is constructed based on a first register transmission level model associated with a first digital module and a first behavior level model associated with a first analog module, the first digital module and the first analog module both belong to the first chip design, the first behavior level model is generated based on a first behavior level description, and the first behavior level description is a behavior level description of a digital-analog interface function of the first analog module. Here, the first register transfer level model associated with the first digital module is generated based on the register transfer level description, e.g., a register transfer level code of the first digital module. A first behavioral level model associated with the first simulation module is generated based on the first behavioral level description. In integrated circuit designs, there are a variety of ways to describe the circuit, including behavioral level descriptions, register transfer level descriptions, and gate level netlist descriptions. Wherein, the behavior level description is used for describing the functions of the circuit, and does not relate to the specific hardware structure of the circuit. The register transmission stage description comprises a description of a register and combination logic, and represents the processing procedure and pipeline principle of data. The register transfer level description, typically in the form of register transfer level code, may be synthesized to obtain a gate level netlist. Gate level netlist description describes a circuit in logic gates for subsequent fabrication of a physical layout. The working principle of the digital circuit means that the conversion can be performed to complete data processing through the storage of registers and the logic operation between registers, and the flow of the data processing can be controlled through a time sequence state machine. The digital circuit may thus generally be embodied with a register transfer level description, for example, the first register transfer level model associated with the first digital module is generated based on the register transfer level description. The operating principle of analog circuits means that it is difficult to embody the operating principle of analog circuits through a register transfer level description, and it is necessary to digitize analog circuits, for example, extract timing information in analog circuits and abstract analog circuits. Simulation verification of analog circuits is therefore typically accomplished by simulators, such as behavioral level descriptions and circuit netlist descriptions. Here, at step S210, the first digital simulation verification environment is constructed based on the first register transfer level model associated with the first digital module and the first behavior level model associated with the first analog module, and the first-stage simulation verification performed at step S210 is under the first digital simulation verification environment and is constructed based on the first behavior level model associated with the first analog module. The first behavioral level model is generated based on a first behavioral level description of a digital-to-analog interface function of the first analog module. In this way, the contribution of the first simulation module to the first simulation verification result is reflected by adopting the first behavior level model in the first stage simulation verification, and the first digital simulation verification environment can be constructed according to the behavior level description of the digital-analog interface function of the first simulation module (for example, the related specification, definition and the like of the digital-analog interface of the first simulation module). The behavior level description of the interface function is embodied through the first behavior level model, so that the specific structure related to the first simulation module is not required to be simulated and verified in the first stage, the simulation speed is high, and the obtained first simulation verification result can also realize the quick positioning problem by utilizing the first register transmission level model related to the first digital module.

With continued reference to fig. 2, in step S212, a second stage of simulation verification is performed on the first chip design by using a second digital simulation verification environment to obtain a second simulation verification result. The second digital simulation verification environment is constructed based on the first register transmission level model and a second behavior level model associated with the first simulation module, the second behavior level model is generated based on the first behavior level description and a second behavior level description, and the second behavior level description is a behavior level description of circuit structures, internal connection relations and real level information of the first simulation module. Here, a second behavior level model is generated based on the first behavior level description and a second behavior level description, and the second behavior level model is generated based on not only the first behavior level description (the first behavior level description is a behavior level description of a digital-analog interface function of the first analog module) but also a second behavior level description (the second behavior level description is a behavior level description of a circuit structure, an internal connection relationship, and real level information of the first analog module) compared to the first behavior level model generated based on the first behavior level description. Therefore, the second behavioral level model associated with the first analog module means that the circuit structure, the internal connection relation and the real number level information of the first analog module need to be extracted, that is, the second behavioral level model can embody the connection relation between various modules and units inside the first analog module, such as a multiplexer, a register and the like, and therefore, the second behavioral level model also comprises a part with consistent digital behaviors of various modules, units and the like inside the first analog module. The second behavioral level model also contains real level information, such as voltage, current, etc., that cannot be represented by the register transfer level description. In addition, the second behavior level description abstracts the circuit which cannot be extracted, such as the bottom circuit unit of the first analog module or the circuit which cannot be extracted due to the correlation of capacitance and resistance, through the behavior level description, and adds the extracted real level information. For example, the behavioral level description of real level information of the second behavioral level description may include a description of signal amplitude by an Analog Front End (AFE) circuit; as another example, the behavioral level description of the real level information of the second behavioral level description may include a decision quantized description of a multiple superposition by a decision feedback equalizer (Decision Feedback Equalizer, DFE). This means that the second stage simulation verification is performed on the first chip design through the second digital simulation verification environment in step S212, which has the characteristics of high consistency between the simulation result and the circuit and controllable simulation time. Thus, the first-stage simulation verification of the first chip design by the first digital simulation verification environment in step S210 and the second-stage simulation verification of the first chip design by the second digital simulation verification environment in step S212 are both performed by digitizing the analog circuit in the digital simulation verification environment, but the first-stage simulation verification uses the first behavior-level model and the second-stage simulation verification uses the second behavior-level model. As such, the first behavioral level model may be regarded as a primary model, implementing a behavioral level description of the interface function according to the definition of the digital-to-analog interface without involving the specific circuit structure of the first analog module; in contrast, the second behavior level model can be regarded as a high-level model, extracts the circuit structure, the internal connection relation and the real level information of the first simulation module, and has the characteristics of high consistency of simulation results and circuits and controllable simulation time. In addition, the second behavioral level model may be a high-level model reflecting the true circuit structure, so overlay circuit structural issues may be verified. In addition, for the bottom layer circuit unit, for example, the receiving end voltage controlled oscillator, the relation between the circuit control signal and the clock frequency under different process angles can be obtained through analog simulation, so that the corresponding relation can be described in the bottom layer circuit unit of the receiving end voltage controlled oscillator, for example, in a table look-up or formula description mode. In this way, during the second-stage simulation verification, the actual circuit working condition can be simulated and verified through the calibration algorithm of the digital circuit and the configuration of the analog circuit.

With continued reference to fig. 2, in step S214, a third stage of simulation verification is performed on the first chip design by using a first digital-analog hybrid simulation verification environment to obtain a third simulation verification result, where the first digital-analog hybrid simulation verification environment is constructed based on the first register transmission level model and a first hybrid model, and the first hybrid model is generated by replacing a behavior level description associated with at least one single point function in the second behavior level model with a circuit netlist description. As such, the first behavioral level description in the first stage simulation verification above is passed. The method can realize the main function verification and algorithm verification of the first chip design, and the second behavior level description is added in the second-stage simulation verification, so that the cooperation between the first digital module and the first module, for example, the cooperation between the function of the digital circuit and the algorithm of the analog circuit can be tested, and in addition, the function simulation of part of modules in the analog circuit is basically completed. Thus, in step S214, the first hybrid model is generated by replacing a behavioral level description associated with at least one single point function in the second behavioral level model with a circuit netlist description on the basis of the second behavioral level model. In this way, the first mixed model can select one or more single-point functions according to the requirement of the verification scene, and then the corresponding module in the selected analog circuit is used for participating in the third-stage simulation verification (by replacing the behavior level description associated with at least one single-point function in the second behavior level model with the circuit netlist description), so that the partial mixed simulation is performed by replacing part of the behavior level description in the advanced behavior model of the analog circuit with the real netlist. And, one or more single-point functions can be selected according to the needs of the verification scene, which means that the simulation conditions and the control simulation time can be flexibly set. For example, simulation conditions under different process angle conditions can be set, simulation verification can be performed for given functions of the first chip design, and flexibility and controllability in terms of simulation time, response speed and the like are achieved. For the projects needing small changes frequently, such as products needing quick response, including short development period, high iteration speed and the like, the method can help ensure that the changed chip design meets the main function verification and algorithm verification of the first chip design and also meets the cooperation between the functions of the digital circuit and the algorithms of the analog circuit on the basis of the first-stage simulation verification and the second-stage simulation verification, and further the simulation verification is carried out on one or more single-point functions in a targeted mode in the third-stage simulation verification. This advantageously shortens the digital-to-analog hybrid simulation time in product development and also ensures the correctness of the chip design, allowing for a flexible increase or decrease in the single point functions selected in the third stage simulation verification, i.e., the generation of the first hybrid model by replacing the behavioral level descriptions associated with more or fewer single point functions in the second behavioral level model with circuit netlist descriptions. Therefore, the third-stage simulation verification selects a corresponding module in the simulation circuit to simulate by using a netlist according to the requirements of a verification scene, and the rest part of the simulation circuit is simulated by using a low-level model, so that the single-point function which needs to be covered by most of digital-analog hybrid simulation verification can be covered, and the simulation time is shortened. For example, when verifying the single point function for calibration of the receiving-side voltage controlled oscillator in the third-stage simulation verification, it is irrelevant to other modules of the analog circuit. Therefore, on the basis of an advanced model with the same structure as an analog circuit, a circuit description part of the receiving end pressure control oscillator and an associated module which is strongly related to a single-point function used for calibration are replaced to simulate a circuit netlist, so that the single-point function is subjected to digital-analog hybrid simulation verification, and a simulation result has a system-level meaning.

With continued reference to fig. 2, in step S216, a fourth stage of simulation verification is performed on the first chip design by using a second mixed simulation verification environment to obtain a fourth simulation verification result, where the second mixed simulation verification environment is constructed based on the first register transmission level model and a second mixed model, and the second mixed model is generated by replacing all the behavior level descriptions in the second behavior level model with circuit netlist descriptions. In this way, by replacing all the behavioral level descriptions in the second behavioral level model with circuit netlist description generation, it means that replacing all the simulation models performs integer-mode hybrid simulation verification for the real circuit. It should be understood that the fourth stage simulation verification means that the analog circuit is abstracted into a circuit model describable in a hardware description language, and timing information of the analog circuit is also extracted to be integrated with the digital circuit, and digital logic correctness and overall digital-analog cooperation logic in the analog circuit are verified. However, the fourth-stage simulation verification is based on the above first-stage simulation verification, second-stage simulation verification, and third-stage simulation verification. That is, the first behavioral level description in the above first-stage simulation verification is passed. The main function verification and algorithm verification of the first chip design can be realized; by adding a second behavior level description in the second-stage simulation verification, the cooperation between the first digital module and the first module can be tested, for example, the cooperation between the function of the digital circuit and the algorithm of the analog circuit can be realized; through the third-stage simulation verification, one or more single-point functions can be selected according to the requirements of verification scenes, and then the corresponding modules in the selected analog circuit are used for participating in the third-stage simulation verification by using the circuit netlist, so that the partial digital-analog hybrid simulation is performed by replacing partial behavioral level description in the advanced behavioral model of the analog circuit as a real netlist. Thus, most of the environmental configuration and chip design configuration constraints are already completed before the fourth stage simulation verification, so that the fourth stage simulation verification mainly completes the whole circuit starting to module entering flow confirmation, and the complete part test case does not need to be run. This means that the fourth stage simulation verification can set the simulation accuracy and simulation time, and in general, since the basis of the foregoing first stage simulation verification, second stage simulation verification, and third stage simulation verification is provided, the digital-analog hybrid simulation verification of the first chip can be considered to pass as long as the upper current flow, i.e., the stage result of the module entering flow, is correct. Therefore, the simulation verification of the fourth stage has relatively low requirements on the simulation process of the test case based on the previous simulation verification result. Taking the receiving end voltage controlled oscillator as an example, the calibration of the receiving end voltage controlled oscillator is provided with 10 steps. Because the time of the first three stages is controllable, all calibration processes of the receiving end pressure-controlled oscillator need to be run out, and the result of the fourth stage which only needs to run to the 1 st step of calibration meets the expectation, the simulation can be considered to pass, and the actual simulation conditions of the last 9 steps are covered in the first three stages. The simulation time occupied by the last 9 steps is generally more than 50% of the whole simulation time, so the simulation time of the fourth stage can be greatly shortened. When the project time is enough, the complete part test case can be run, if the project period is short, for example, the project with higher response speed is needed, and the simulation verification in the fourth stage can be considered to pass only when the result of the 1 st step is correct. Therefore, in step S218, a digital-analog hybrid simulation verification result of the first chip design is generated based on the first simulation verification result, the second simulation verification result, the third simulation verification result, and the fourth simulation verification result. In summary, the method for digital-analog hybrid simulation verification shown in fig. 2 gradually builds a digital-analog hybrid simulation verification scheme for the first chip design according to the first-stage simulation verification, the second-stage simulation verification, the third-stage simulation verification and the fourth-stage simulation verification, so that the simulation time of the digital-analog hybrid simulation verification is greatly shortened, various excitation, configuration, verification components and regression tools in the digital simulation verification environment can be fully utilized, and the reliability of the verification result is improved, the product development time is shortened, and the response speed is improved.

In one possible implementation, the third simulation verification result includes a system level modulo hybrid simulation verification result associated with the at least one single point function. In some embodiments, the fourth simulation verification result includes a system level modulo hybrid simulation verification result associated with a complete function of the first chip design. In some embodiments, the third simulation verification result further comprises a simulation verification result at a different process corner of a relationship of the circuit control signal associated with the at least one single point function with respect to the clock frequency. The first hybrid model is generated by replacing a behavior level description associated with at least one single point function in the second behavior level model with a circuit netlist description on the basis of the second behavior level model. In this way, the first mixed model can select one or more single-point functions according to the requirement of the verification scene, and then the corresponding module in the selected analog circuit is used for participating in the third-stage simulation verification (by replacing the behavior level description associated with at least one single-point function in the second behavior level model with the circuit netlist description), so that the partial mixed simulation is performed by replacing part of the behavior level description in the advanced behavior model of the analog circuit with the real netlist. Therefore, the third-stage simulation verification selects a corresponding module in the simulation circuit to simulate by using a netlist according to the requirements of a verification scene, and the rest part of the simulation circuit is simulated by using a low-level model, so that the single-point function which needs to be covered by most of digital-analog hybrid simulation verification can be covered, and the simulation time is shortened. In contrast, the fourth-stage simulation verification mainly completes the process from the start of the whole circuit to the confirmation of the module entering, so that the fourth simulation verification result comprises a system series-mode mixed simulation verification result related to the complete function of the first chip design, namely, the whole simulation model is replaced to complete the whole-mode mixed simulation verification for the real circuit. It should be appreciated that, although the fourth simulation verification result includes a system series-level analog-to-digital hybrid simulation verification result associated with the complete function of the first chip design, because the fourth-level simulation verification is based on the above first-level simulation verification, second-level simulation verification, and third-level simulation verification, most of the environmental configuration and chip design configuration constraints are already completed before the fourth-level simulation verification, the fourth-level simulation verification does not need to run a complete part of the test case and has relatively low requirements on the simulation process of the test case, and the simulation time of the digital-to-analog hybrid simulation verification can be greatly shortened on the premise of ensuring quality according to the project period length and the response speed requirements.

In one possible implementation manner, the first simulation verification result includes a digital simulation verification result of a digital-to-analog interface function of the first analog module, and the second simulation verification result includes a digital simulation result of a circuit structure and an internal connection relationship of the first analog module. In some embodiments, the second simulation verification result further includes real-level information of the voltage and current of the first simulation module. Therefore, the behavior level description of the interface function is embodied through the first behavior level model, so that the specific structure related to the first simulation module is not required to be simulated and verified in the first stage, the simulation speed is high, and the obtained first simulation verification result can also realize the quick positioning problem by utilizing the first register transmission level model related to the first digital module. The second behavioral level model may be a high-level model reflecting the actual circuit structure, so overlay circuit structural issues may be verified. The second behavioral level model also contains real level information, such as voltage, current, etc., that cannot be represented by the general register transfer level description. In this way, during the second-stage simulation verification, the actual circuit working condition can be simulated and verified through the calibration algorithm of the digital circuit and the configuration of the analog circuit.

In one possible implementation manner, the first chip design is a receiving end voltage controlled oscillator, the first simulation verification result is associated with the calibration algorithm convergence of the receiving end voltage controlled oscillator, the second simulation verification result is associated with the calibration algorithm convergence of the receiving end voltage controlled oscillator, a built-in self-test module and analog high-speed calculation logic, the third simulation verification result is associated with the calibration algorithm convergence of the receiving end voltage controlled oscillator, the built-in self-test module, the analog high-speed calculation logic and the suitability of the analog high-speed calculation logic to the digital logic under different process angles, and the fourth simulation verification result is associated with the calibration algorithm convergence of the receiving end voltage controlled oscillator, the built-in self-test module, the analog high-speed calculation logic, the suitability of the analog high-speed calculation logic to the digital logic under different process angles and the upper current range of the receiving end voltage controlled oscillator. The first behavioral level description in the verification is simulated through a first stage. The main function verification and algorithm verification of the first chip design can be realized; by adding a second behavior level description in the second-stage simulation verification, the cooperation between the first digital module and the first module can be tested, for example, the cooperation between the function of the digital circuit and the algorithm of the analog circuit can be realized; through the third-stage simulation verification, one or more single-point functions can be selected according to the requirements of verification scenes, and then the corresponding modules in the selected analog circuit are used for participating in the third-stage simulation verification by using the circuit netlist, so that the partial digital-analog hybrid simulation is performed by replacing partial behavioral level description in the advanced behavioral model of the analog circuit as a real netlist. Thus, most of the environmental configuration and chip design configuration constraints are already completed before the fourth stage simulation verification, so that the fourth stage simulation verification mainly completes the whole circuit starting to module entering flow confirmation, and the complete part test case does not need to be run. Taking the first chip design as the receiving end voltage controlled oscillator as an example, the test cases can be distributed in stages by using the method for digital-analog hybrid simulation verification shown in fig. 2, so that the digital-analog hybrid simulation verification scheme of the receiving end voltage controlled oscillator is distributed to the first-stage simulation verification, the second-stage simulation verification, the third-stage simulation verification and the fourth-stage simulation verification, the simulation time of the digital-analog hybrid simulation verification is greatly shortened, various excitation, configuration, verification components and regression tools in the digital simulation verification environment can be fully utilized, the reliability of verification results is improved, the product development time is shortened, and the response speed is improved. Specifically, the fourth simulation verification result is related to the convergence of the calibration algorithm of the receiving-end voltage-controlled oscillator, the built-in self-test module, the analog high-speed calculation logic, the suitability of the analog high-speed calculation logic relative to the digital logic under different process angles, and the current-up range of the receiving-end voltage-controlled oscillator. The fourth-stage simulation verification means that the whole simulation model is replaced to perform integer-mode hybrid simulation verification for the real circuit, but because the fourth-stage simulation verification is based on the first-stage simulation verification, the second-stage simulation verification and the third-stage simulation verification, most of environment configuration and chip design configuration constraint are completed before the fourth-stage simulation verification, the fourth-stage simulation verification does not need to run a complete test case and has relatively low simulation process requirements on the test case, and the simulation time of the digital-to-analog hybrid simulation verification can be greatly shortened on the premise of ensuring quality according to the project period length and response speed requirements.

In one possible implementation, the digital-to-analog hybrid simulation verification result of the first chip design includes a plurality of calibration steps associated with a given function of the first chip design, an initial one or more of the plurality of calibration steps being covered by the fourth simulation verification result, remaining ones of the plurality of calibration steps relative to the initial one or more steps being covered by the first simulation verification result, the second simulation verification result, and the third simulation verification result. The fourth-stage simulation verification mainly completes the process from the starting of the whole circuit to the entering of the module, so that the fourth simulation verification result comprises a system series-mode mixed simulation verification result related to the complete function of the first chip design, namely, the whole simulation model is replaced to complete the whole-mode mixed simulation verification for the real circuit. It should be appreciated that, although the fourth simulation verification result includes a system series-level analog-to-digital hybrid simulation verification result associated with the complete function of the first chip design, because the fourth-level simulation verification is based on the above first-level simulation verification, second-level simulation verification, and third-level simulation verification, most of the environmental configuration and chip design configuration constraints are already completed before the fourth-level simulation verification, the fourth-level simulation verification does not need to run a complete part of the test case and has relatively low requirements on the simulation process of the test case, and the simulation time of the digital-to-analog hybrid simulation verification can be greatly shortened on the premise of ensuring quality according to the project period length and the response speed requirements. Here, it is assumed that a plurality of calibration steps associated with a given function of the first chip design, an initial one or more of the plurality of calibration steps are covered by the fourth simulation verification result, for example, the fourth-stage simulation verification covers only an initial one step, that is, the first step, so that the simulation time of the digital-analog hybrid simulation verification can be greatly shortened while ensuring the quality. For example, the calibration of the receiving end voltage controlled oscillator has 10 steps, because the time of the first three steps is controllable, all calibration processes of the receiving end voltage controlled oscillator need to be run out, but the result of the fourth step, which only needs to be run to the 1 st step of calibration, is in line with expectations, the simulation can be considered to pass, and the actual simulation conditions of the last 9 steps are covered in the first three steps.

In one possible implementation, the simulation time of each of the first-stage simulation verification, the second-stage simulation verification, and the third-stage simulation verification is controllable by a preset simulation condition. In one possible implementation, the first register transfer level model is generated based on a first register transfer level description that includes register transfer level code of the first digital module. In one possible embodiment, the first digital module is a digital circuit part of the first chip design and the first analog module is an analog circuit part of the first chip design. Therefore, the simulation time of the digital-analog hybrid simulation verification is greatly shortened, various excitation, configuration, verification components and regression tools in the digital simulation verification environment can be fully utilized, and the reliability of the verification result is improved, the product development time is shortened, and the response speed is improved.

In one possible implementation manner, the first chip design is a serializer deserializer product, and the first-stage simulation verification, the second-stage simulation verification, the third-stage simulation verification and the fourth-stage simulation verification are all implemented through a first simulation verification platform, wherein the first simulation verification platform comprises a configuration access component, a flow control component, a parallel port sending component, a parallel port checking component, a serial port sending component, a circuit key node checking component, a design to be tested configuration constraint component and an environment configuration constraint component. In some embodiments, the environment configuration constraint component is configured to implement data flow trend control, simulation timeout control, and simulation acceleration control of the first simulation verification platform. In the above-mentioned method for digital-analog hybrid simulation verification shown in fig. 2, the digital-analog hybrid simulation verification scheme is dispersed into the first-stage simulation verification, the second-stage simulation verification, the third-stage simulation verification and the fourth-stage simulation verification, so that the simulation time of the digital-analog hybrid simulation verification is greatly shortened, various excitation, configuration, verification components and regression tools in the digital simulation verification environment can be fully utilized, and the reliability of the verification result, the product development time and the response speed are improved. Taking the first chip design as a SERializer-deserializer (SERIALER/DESerializer, SERDES) product as an example, in the first stage, simulation verification is performed, the configuration path component mainly realizes the configuration port time sequence of SERDES, and registers which want to operate are written in or read out in an optional front-back gate mode; the flow control component mainly realizes a series of flows related to SERDES functions, and realizes an initialization flow, a rate switching flow, a power consumption state switching flow, a calibration flow and the like through control function signals and handshake signals; the parallel port transmitting component and the parallel port checking component realize data generation of a parallel port transmitting side and data checking of a parallel port receiving side, and generate and check data according to configured frequency points, wherein the data types are common clock code types and code types related to each protocol; the serial port transmitting assembly and the serial port checking assembly realize data checking at a serial port receiving side and data generation at the serial port transmitting side, and generate data according to the configured frequency point check sum, wherein the data type is a common clock code type and a code type related to each protocol; the circuit key node verification component realizes time sequence and numerical verification of the circuit key node under different procedures; the to-be-tested design configuration constraint component realizes different configurations of to-be-tested designs under different reference clocks, protocol rates and data bit widths automatically generated according to the whole SERDES configuration table, and is used by the configuration access component and the flow control component; the environment configuration constraint component realizes the whole verification environment control configuration, such as data flow trend control, simulation timeout control, simulation acceleration control and the like, and is used by the environment itself, the configuration access component and the flow control component. Functional cases of different verification scenes can be written, simulation is started, and multiple rounds of regression are completed. In contrast, in the second stage of simulation verification, for example, for a relatively complex receiving end circuit part in a SERDES product, the clock and data path level description is mainly used, so that in order to achieve both simulation speed and algorithm verification, the simulation advanced behavior model further improves description accuracy, real number type data is added, and real number level description is performed on the simulation front end. In order to adapt the modification of the model, the following adjustments need to be made: in the environment configuration constraint component, a simulation advanced behavior model mode is added; the serial port transmitting component simulates an advanced behavior model mode, and adds a real number type as input excitation; sampling the output result of the analog front end in the analog advanced behavior model to generate an eye diagram, and evaluating the usability of the digital algorithm. Simulation can be initiated and multiple rounds of regression can be completed. In contrast, in the third stage of simulation verification, according to the requirements of verification scenes, selecting corresponding modules in the simulation circuit to simulate by using a netlist, and simulating by using a low-level model in the rest part; in the environment configuration constraint component, corresponding temperature, process angle, power supply voltage and the like of the analog module circuit under different process angles are additionally arranged; in the environment configuration constraint component, the threshold voltage of each mode to the number or the number to the mode is increased and the like; the to-be-tested design configuration constraint component increases the relevant configuration values of the register transmission level corresponding to the normal operation of the analog module circuit under different process angles; the circuit key node verification component adapts to the node which does not exist in the original model under the mode; and adding channel models on the output side and the input side, and bringing the signal attenuation into a front simulation link. The simulation tool may be started and a round of regression is completed. In contrast, in the fourth stage simulation verification, in the environment configuration constraint component, the simulation circuit part is fully constrained into a simulation netlist; in the environment configuration constraint component, corresponding temperature, process angle, power supply voltage and the like of the analog module circuit under different process angles are additionally arranged; in the environment configuration constraint component, the threshold voltage of the mode-to-number or the mode-to-number in each test case is increased and set. The simulation tool may be started and a round of regression is completed.

Fig. 3 is a schematic diagram of a simulation verification platform according to an embodiment of the present application. As shown in FIG. 3, simulation verification platform 300 includes a configuration pass component 302, a flow control component 304, a parallel port send component 306, a parallel port verification component 308, a serial port verification component 310, a serial port send component 312, a circuit critical node verification component 314, a design under test configuration constraint component 316, and an environmental configuration constraint component 318. For details of the simulation verification platform shown in fig. 3, reference may be made to the above specific embodiments, which are not described herein.

Fig. 4 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, where the input/output interface 450 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 400 performing various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the present embodiment, the computing device 400 may be configured to implement some or all of the functions of one or more components of the apparatus embodiments described above, and the communication interface 420 may be configured to implement communication functions and the like necessary for the functions of the apparatuses, components, and the processor 410 may be configured to implement processing functions and the like necessary for the functions of the apparatuses, components.

It should be appreciated that the computing device 400 of fig. 4 may include one or more processors 410, and that the processors 410 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the processors 410 may constitute a processor sequence or processor array, or that the processors 410 may be separated into primary and secondary processors, or that the processors 410 may have different architectures such as heterogeneous computing architectures. In addition, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in fig. 4, or combine certain components, or split certain components, or have a different arrangement of components.

The processor 410 may have various specific implementations, for example, the processor 410 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), which are not limited in this embodiment. Processor 410 may also be a single-core processor or a multi-core processor. Processor 410 may be comprised of a combination of a CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 410 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 420 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.

The memory 430 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 430 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 430 may also be used to store program code and data such that processor 410 invokes the program code stored in memory 430 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components.

The bus 440 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 4 for clarity of illustration, but does not represent only one bus or one type of bus.

The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated. Embodiments of the present application also provide a system that includes a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.

Claims

1. A method for digital-analog hybrid simulation verification, the method comprising:

performing first-stage simulation verification on a first chip design through a first digital simulation verification environment to obtain a first simulation verification result, wherein the first digital simulation verification environment is constructed based on a first register transmission level model associated with a first digital module and a first behavior level model associated with a first analog module, the first digital module and the first analog module belong to the first chip design, the first behavior level model is generated based on a first behavior level description, and the first behavior level description is a behavior level description of a digital-analog interface function of the first analog module;

Performing second-stage simulation verification on the first chip design through a second digital simulation verification environment to obtain a second simulation verification result, wherein the second digital simulation verification environment is constructed based on the first register transmission stage model and a second behavior stage model associated with the first simulation module, the second behavior stage model is generated based on the first behavior stage description and a second behavior stage description, and the second behavior stage description is a behavior stage description of circuit structure, internal connection relation and real stage information of the first simulation module;

performing third-stage simulation verification on the first chip design through a first digital-analog hybrid simulation verification environment to obtain a third simulation verification result, wherein the first digital-analog hybrid simulation verification environment is constructed based on the first register transmission level model and a first hybrid model, and the first hybrid model is generated by replacing a behavior level description associated with at least one single-point function in the second behavior level model with a circuit netlist description;

performing fourth-stage simulation verification on the first chip design through a second digital-analog hybrid simulation verification environment to obtain a fourth simulation verification result, wherein the second digital-analog hybrid simulation verification environment is constructed based on the first register transmission level model and a second hybrid model, and the second hybrid model is generated by replacing all behavior level descriptions in the second behavior level model with circuit netlist descriptions;

And generating a digital-analog hybrid simulation verification result of the first chip design based on the first simulation verification result, the second simulation verification result, the third simulation verification result and the fourth simulation verification result.

2. The method of claim 1, wherein the third simulation verification result comprises a system level modulo hybrid simulation verification result associated with the at least one single point function.

3. The method of claim 2, wherein the fourth simulation verification result comprises a system level modulo hybrid simulation verification result associated with a complete function of the first chip design.

4. The method of claim 3, wherein the third simulation verification result further comprises: simulation verification of the relationship between the circuit control signal and the clock frequency at different process corners, wherein the circuit control signal is associated with the at least one single point function.

5. The method of claim 1, wherein the first simulation verification result comprises a digital simulation verification result of a digital-to-analog interface function of the first analog module, and the second simulation verification result comprises a digital simulation result of a circuit structure and an internal connection relationship of the first analog module.

6. The method of claim 5, wherein the second simulation verification result further comprises real level information of the voltage and current of the first simulation module.

7. The method of claim 1, wherein the first chip design is a receiver voltage controlled oscillator, the first simulation verification result is associated with a calibration algorithm convergence of the receiver voltage controlled oscillator, the second simulation verification result is associated with a calibration algorithm convergence of the receiver voltage controlled oscillator, a built-in self-test module, and analog high-speed computation logic, the third simulation verification result is associated with a calibration algorithm convergence of the receiver voltage controlled oscillator, a built-in self-test module, analog high-speed computation logic, and an adaptation of the analog high-speed computation logic to digital logic at different process angles, and the fourth simulation verification result is associated with a calibration algorithm convergence of the receiver voltage controlled oscillator, a built-in self-test module, analog high-speed computation logic, an adaptation of the analog high-speed computation logic to digital logic at different process angles, and an upper current path of the receiver voltage controlled oscillator.

8. The method of claim 1, wherein the digital-to-analog hybrid simulation verification result of the first chip design includes a plurality of calibration steps associated with a given function of the first chip design, a first one or more of the plurality of calibration steps being covered by the fourth simulation verification result, remaining ones of the plurality of calibration steps relative to the first one or more steps being covered by the first simulation verification result, the second simulation verification result, and the third simulation verification result.

9. The method of claim 1, wherein the respective simulation times of the first stage simulation verification, the second stage simulation verification, and the third stage simulation verification are controllable by preset simulation conditions.

10. The method of claim 1, wherein the first register transfer level model is generated based on a first register transfer level description, the first register transfer level description comprising a register transfer level code of the first digital module.

11. The method of claim 1, wherein the first digital module is a digital circuit portion of the first chip design and the first analog module is an analog circuit portion of the first chip design.

12. The method of claim 1, wherein the first chip design is a serializer deserializer product, and the first stage simulation verification, the second stage simulation verification, the third stage simulation verification, and the fourth stage simulation verification are all implemented by a first simulation verification platform, the first simulation verification platform including a configuration pass component, a flow control component, a parallel port send component, a parallel port check component, a serial port send component, a circuit key node check component, a design under test configuration constraint component, and an environmental configuration constraint component.

13. The method of claim 12, wherein the environmental configuration constraint component is configured to implement data flow trend control, simulation timeout control, and simulation acceleration control of the first simulation verification platform.

14. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 13 when executing the computer program.

15. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 13.