WO2021128171A1 - Formal verification method and device for chip, and storage medium - Google Patents

Abstract

Provided are a formal verification method and device for a chip, and a storage medium. The method comprises: acquiring a synthesized netlist corresponding to a chip design code; dividing the synthesized netlist into a plurality of functional modules according to design functions, wherein each functional module has boundary and hierarchy information, and a division mode for the plurality of functional modules does not change the logical hierarchical structure of a register transfer level corresponding to the synthesized netlist; and performing formal verification on the synthesized netlist on the basis of the plurality of functional modules. The formal verification method and device for a chip, and the storage medium provided by the present embodiment effectively shorten the operation time of formal verification, and further improve the quality and efficiency of formal verification.

Description

Formal verification method, equipment and storage medium of chip Technical field

The embodiments of the present invention relate to the technical field of chip design, and in particular to a method, device and storage medium for formal verification of a chip.

Background technique

With the development of very large-scale integrated circuits, the number of logic gates is increasing. The running time of the formal verification from Register Transfer Level (RTL) code to the integrated netlist is gradually becoming longer, which consumes resources. Increasing size has led to inefficient delivery of chip designs and uncontrollable time, especially when iterative modifications are required, which seriously affects the efficiency and progress of formal verification.

Summary of the invention

The embodiment of the present invention provides a method, device and storage medium for formal verification of a chip.

The first aspect of the present invention is to provide a formal verification method for a chip, including:

Obtain a comprehensive netlist corresponding to the chip design code;

Divide the comprehensive netlist into multiple functional modules according to design functions, where each functional module has boundary and level information, and the division of multiple functional modules does not change the register corresponding to the comprehensive netlist The logical hierarchy of the transmission level;

Perform formal verification on the integrated netlist based on a plurality of the functional modules.

The second aspect of the present invention is to provide a chip formal verification device, including:

Memory, used to store computer programs;

The processor is configured to run a computer program stored in the memory to realize:

Obtain a comprehensive netlist corresponding to the chip design code;

Divide the comprehensive netlist into multiple functional modules according to design functions, where each functional module has boundary and level information, and the division of multiple functional modules does not change the register corresponding to the comprehensive netlist The logical hierarchy of the transmission level;

Perform formal verification on the integrated netlist based on a plurality of the functional modules.

The third aspect of the present invention is to provide a computer-readable storage medium, the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used in the first aspect. The formal verification method of the chip described.

The chip formal verification method, device and storage medium provided by the embodiments of the present invention effectively shorten the running time of formal verification, and further improve the quality and efficiency of formal verification.

Description of the drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The exemplary embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation of the application. In the attached picture:

FIG. 1 is a schematic flowchart of a method for formal verification of a chip provided by an embodiment of the present invention;

2 is a schematic diagram of dividing the integrated netlist into multiple functional modules according to design functions according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a flow of detecting whether the state of the formal verification performed by the functional module is a normal state according to an embodiment of the present invention;

4 is a schematic flowchart of another method for formal verification of a chip provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of dividing the functional module into multiple sub-functional modules according to an embodiment of the present invention;

6 is a schematic flowchart of another method for formal verification of a chip provided by an embodiment of the present invention;

FIG. 7 is a schematic flowchart of another method for formal verification of a chip provided by an embodiment of the present invention;

8 is a schematic flowchart of another method for formal verification of a chip provided by an embodiment of the present invention;

9 is a schematic flowchart of another method for formal verification of a chip provided by an embodiment of the present invention;

FIG. 10 is a schematic diagram of a comprehensive netlist provided by an embodiment of the present invention including register transfer-level codes in addition to multiple functional modules;

FIG. 11 is a schematic structural diagram of a formal verification device for a chip provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention.

With the development of VLSI, there are more and more logic gates after synthesis. The running time required from RTL code to formal verification operation is gradually getting longer, and the resource consumption is increasing, which leads to the realization of chip design and delivery. The efficiency is low and the time is uncontrollable. Especially when iterative modification is required, the running time and accuracy required for formal verification become a bottleneck, and it is easy to affect the efficiency and progress of formal verification.

In the design process of VLSI, when running time and resource occupancy problems are encountered, adjustments can be made based on the suggested information in Table 1 below. However, for the recommended information in Table 1, either increase the R&D cost or affect the optimization of performance, power consumption and area.

Table 1

Suggest	influences
Continuously update the software version	Subject to supplier
Use the fastest machine	Deployment of project resources
Make the module smaller	A dimension of module division
Avoid unfriendly code style for formal verification	Valuable for some modules
Use a comprehensive strategy that facilitates formal verification	Optimizations affecting performance, power consumption and area

In the following, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. As long as there is no conflict between the embodiments, the following embodiments and the features in the embodiments can be combined with each other.

FIG. 1 is a schematic flow chart of a method for formal verification of a chip provided by an embodiment of the present invention; referring to FIG. 1, this embodiment provides a method for formal verification of a chip, and the execution body of the method is a formal verification device. It is understandable that the formal verification device can be implemented as software or a combination of software and hardware. Specifically, the formal verification method may include:

Step S101: Obtain a comprehensive netlist corresponding to the chip design code.

Step S102: Divide the comprehensive netlist into multiple functional modules according to the design function, where each functional module has boundary and level information, and the division method of multiple functional modules does not change the logic level of the register transfer level corresponding to the comprehensive netlist structure.

Step S103: Perform formal verification on the integrated netlist based on multiple functional modules.

The following is a detailed description of the above steps:

Step S101: Obtain a comprehensive netlist corresponding to the chip design code.

Specifically, after the chip design code is obtained, an electronic design automation (Electronics Design Automation, EDA) tool can be used to perform logic synthesis processing on the chip design code to obtain a comprehensive netlist corresponding to the chip design code.

Step S102: Divide the comprehensive netlist into multiple functional modules according to the design function, where each functional module has boundary and level information, and the division method of multiple functional modules does not change the logic level of the register transfer level corresponding to the comprehensive netlist structure. The comprehensive netlist division is based on the module structure and hierarchy in the register conversion level circuit. It should be noted that although the multiple functional modules divided by the comprehensive netlist are based on the initial division of the modules in the register conversion level circuit, the multiple functional modules divided by the comprehensive netlist are the initial divisions in the register conversion level circuit. Re-divided based on the divided modules.

After the integrated netlist is obtained, the register units included in the integrated netlist can be analyzed and processed, so that multiple design functions corresponding to the integrated netlist can be obtained, and then the integrated netlist can be divided into multiples according to the design functions. Each functional module has boundary and level information, and the existing boundary and level information is used to facilitate the identification of the functional modules included in the integrated netlist. In addition, when the integrated netlist is divided into modules, the division of multiple functional modules does not change the logical hierarchical structure of the register transfer level corresponding to the integrated netlist. According to an embodiment of the present invention, the division of multiple functional modules is only used in the formal verification stage.

For example, as shown in Figure 2, after the comprehensive netlist is obtained, the comprehensive netlist can be analyzed and identified, and the design functions corresponding to the comprehensive netlist can be determined including design function a, design function b, design function c, and design Function d, after obtaining the design function, the multiple register units included in the comprehensive netlist can be divided into four function modules according to the above design function, namely function module A, function module B, function module C and function module D , Among them, the function module A corresponds to the design function a, the function module B corresponds to the design function b, the function module C corresponds to the design function c, and the function module D corresponds to the design function d.

It can be understood that a divided functional module can correspond to one or more design functions, and those skilled in the art can set it according to specific design requirements and application scenarios. For example: when analyzing and identifying the comprehensive netlist, it can be determined that the corresponding design functions of the comprehensive netlist include design function a, design function b, design function c, design function d, design function e, and design function f. After the above-mentioned design function, the multiple register units included in the integrated netlist can be divided into four function modules according to the above-mentioned design function, namely, function module A, function module B, function module C, and function module D. Among them, function module A may correspond to design function a, function module B may correspond to design function b and design function c, function module C may correspond to design function d, and function module D may correspond to design function e and design function F corresponds. Of course, the corresponding relationship between the function modules and the design functions is not limited to the above examples, and those skilled in the art can make arbitrary settings according to specific application requirements and design requirements, which will not be repeated here.

In addition, the function module A may include one or more register units. Similarly, the function module B, the function module C, and the function module D may all include one or more register units. It should be noted that regardless of whether the multiple register units in the comprehensive netlist are divided into multiple functional modules according to the design function, for each register unit in the comprehensive netlist, the input and output relationship and the multiple functional modules after division The input and output relationship of each register unit is the same, that is, the division method of multiple functional modules does not change the logical hierarchical structure of the register transfer level corresponding to the integrated netlist.

Step S103: Perform formal verification on the integrated netlist based on multiple functional modules.

After obtaining multiple functional modules, the comprehensive netlist can be formally verified based on multiple functional modules; specifically, the formal verification of the comprehensive netlist based on multiple functional modules may include at least one of the following: At least one of the functional modules in the module is formally verified separately; at least one functional module unit including at least two functional modules is formally verified; and the whole composed of all functional modules is formally verified.

According to an embodiment of the present invention, since the integrated netlist is divided into multiple functional modules according to design functions, formal verification of multiple functional modules can be performed at the same time, so as to improve the efficiency of formal verification. In other words, since the integrated netlist is divided into multiple functional modules according to the design function, multiple functional modules can be processed in parallel, thereby improving the efficiency of formal verification. In addition, it should be noted that, due to different division schemes, the integrated netlist can be divided into different types of functional module sets, where each functional module set corresponds to a division scheme. Further, the comprehensive netlist can be formally verified separately according to each division scheme, thereby improving the quality of formal verification. In addition, the integrated netlist can be divided into different functional module sets according to different priorities, so that the division of formal verification is more flexible. For example, the integrated netlist includes four functional modules, which are functional module A, functional module B, functional module C, and functional module D. If the priority of functional module A and functional module B is higher than other functional modules, functional module A and functional module B may be preferably verified. In one embodiment, if a certain functional module is modified, the priority of this functional module can be set higher than the priority of other functional modules.

For example, after obtaining the four functional modules (functional module A, functional module B, functional module C, and functional module D) included in the integrated netlist, the integrated netlist can be performed based on the four functional modules obtained. The operation of formal verification. Specifically, when performing formal verification on a comprehensive netlist based on multiple functional modules, one possible way is to perform separate formal verification operations on functional module A, functional module B, functional module C, and functional module D respectively; Another achievable way is to perform formal verification operations on the whole constituted by all functional modules. In general, in order to ensure the stability and reliability of the formal verification operation, the functional modules can be individually verified. After the four functional modules have passed the formal verification operations, the overall structure of the four functional modules can be performed. Formal verification operations.

There is another achievable way to perform formal verification on at least one functional module unit that includes at least two functional modules. For example, formal verification is performed on functional module unit 1 composed of functional module A and functional module B. The functional module unit two composed of functional module C and functional module D performs formal verification. In general, in order to ensure the stability and reliability of the formal verification operation, at least one functional module unit including at least two functional modules can be formally verified. After at least one functional module unit passes the formal verification operation, the four The function module constitutes a formal verification operation.

The method for formal verification of the chip provided in this embodiment is to obtain the integrated netlist corresponding to the chip design code, divide the integrated netlist into multiple functional modules according to the design function, and then form the integrated netlist based on the multiple functional modules. Verification effectively guarantees the quality and efficiency of formal verification, and when iterative modification operations on the integrated netlist are encountered, the functional modules that perform iterative modification operations can be accurately performed based on the boundary and level information of the functional modules. Positioning, in turn, is convenient to ensure the accuracy of iterative modification of the integrated netlist and rapid iterative operations, further ensures the accuracy of formal verification, and effectively ensures the stability and reliability of the method.

In some instances, when performing formal verification on the integrated netlist based on multiple functional modules, the method in this embodiment may further include:

Step S200: For a plurality of functional modules, it is detected whether the state of formal verification performed by the functional module is a normal state.

After obtaining multiple functional modules, formal verification can be performed based on multiple functional modules. During the formal verification operation of the functional module, the working state of the functional module for formal verification can include normal state and abnormal state. The state is used to identify the functional module performing normal formal verification operations, and the abnormal state is used to identify the functional module cannot perform normal formal verification operations. The abnormal state can be caused by the logic of the functional module being too complex, the formal verification time is long, and the formal verification Caused by abnormal operation and so on. For example, the abnormal state is inclusive, abnormal end, or verification timeout. In order to ensure the quality and efficiency of formal verification, after obtaining multiple functional modules, it is possible to detect whether the state of the functional module undergoing formal verification is normal; specifically, refer to Figure 3 for the formal verification of the functional module. Whether the status is normal can include:

Step S301: Obtain the verification time corresponding to the functional module.

Step S302: Check whether the state of the formal verification performed by the functional module is a normal state according to the verification time.

In the process of formal verification of the functional module, the verification time corresponding to the functional module can be obtained, and then the verification time can be analyzed and processed according to the verification time to realize whether the state of the formal verification of the functional module is normal according to the verification time. Specifically, detecting whether the state of the formal verification performed by the functional module according to the verification time is a normal state may include:

Step S3021: When the verification time is less than the preset time threshold, it is determined that the state of the functional module performing formal verification is a normal state.

Step S3022: When the verification time is greater than or equal to the preset time threshold, it is determined that the state of the functional module performing formal verification is an abnormal state.

Specifically, the preset time threshold is pre-configured time information, and the preset time threshold is used as the maximum time limit for determining that the state of the functional module for formal verification is the normal state. The time information of the time threshold is not limited, and those skilled in the art can set it according to specific application scenarios and design requirements. For example, the preset time threshold can be 10min, 15min or 20min, etc. After the verification time is obtained, the The verification time is analyzed and compared with the preset time threshold. If the verification time is less than the preset time threshold, it means that the functional module at this time has obtained the corresponding formal verification result within the preset time threshold, and then the functional module can be determined for formal verification The status is normal. If the verification time is greater than or equal to the preset time threshold, it means that the functional module at this time has not obtained the corresponding formal verification result within the preset time threshold, and it can be determined that the state of the functional module performing formal verification is an abnormal state.

In this embodiment, by obtaining the verification time corresponding to the functional module, according to the verification time, it is detected whether the state of the formal verification performed by the functional module is a normal state, which effectively realizes the accurate detection of whether the state of the formal verification performed by the functional module is a normal state. , So as to facilitate the realization of the state of formal verification through the functional module to determine the state of formal verification of the integrated netlist, and further improve the quality and efficiency of the formal verification operation.

Fig. 4 is a schematic flow chart of another method for formal verification of a chip provided by an embodiment of the present invention; on the basis of the foregoing embodiment, referring to Fig. 4, after determining that the state of the functional module performing formal verification is an abnormal state , The method in this embodiment may further include:

Step S401: Divide the functional module into multiple sub-functional modules, where each sub-functional module has boundary and level information.

Step S402: Perform formal verification on the functional module based on multiple sub-functional modules.

In some instances, dividing the functional module into multiple sub-functional modules may include:

Step S4011: Obtain module design information corresponding to the functional module.

Step S4012: Divide the function module into multiple sub-function modules according to the module design information.

Among them, when the state of the functional module undergoing formal verification is abnormal, in order to improve the quality and efficiency of formal verification of the integrated netlist and shorten the time required for formal verification, the functional module in the abnormal state can be directly re-moduled Division operation, that is, the functional module is divided into multiple sub-functional modules. Each sub-functional module has boundary and level information. Among them, the boundary and level information of each sub-functional module is used to facilitate the identification of the sub-functional modules included in the functional module. functional module. Moreover, when the functional module is divided into multiple sub-functional modules, the division method of the multiple sub-functional modules does not change the logical hierarchical structure of the register transfer level corresponding to the functional module. After multiple sub-function modules are obtained, the formal verification operation of the function modules can be implemented based on the multiple sub-function modules, thereby improving the quality and efficiency of formal verification.

For example, as shown in Figure 5, when the state of functional module A undergoing formal verification is an abnormal state, the module design function corresponding to the functional module A can be obtained. It is assumed that the module design function includes module design function a, module Design function b, module design function c, and module design function d. After obtaining the above-mentioned module design function, the multiple register units included in function module A can be divided into four sub-function modules according to the above-mentioned module design function, namely Function module A is divided into: sub-function module A1, sub-function module A2, sub-function module A3, and sub-function module A4. Among them, sub-function module A1 can correspond to module design function a, and sub-function module A2 can correspond to module design function b. Correspondingly, the sub-function module A3 may correspond to the module design function c, and the sub-function module A4 may correspond to the module design function d.

Similarly, when the state of functional module B undergoing formal verification is abnormal, the module design function corresponding to functional module B can be obtained. It is assumed that when the module design function includes four module design functions, the above four can be used. A modular design function divides functional module B into sub-functional module B1, sub-functional module B2, sub-functional module B3, and sub-functional module B4. When the state of the functional module C undergoing formal verification is abnormal, the corresponding module design function of the functional module C can be obtained. If the module design function includes two module design functions, the above two module design can be used The function divides the function module C into a sub-function module C1 and a sub-function module C2. When the state of the functional module D undergoing formal verification is abnormal, the module design function corresponding to the functional module D can be obtained. If the module design function includes two module design functions, the above two module design functions can be used The function divides the function module D into a sub-function module D1 and a sub-function module D2.

In this embodiment, after determining that the state of the functional module performing formal verification is an abnormal state, the functional module is divided into multiple sub-functional modules, and then the functional module is formally verified based on the multiple sub-functional modules. When there is a problem in the formal verification process, the functional module is divided into multiple sub-functional modules by layering again, and then the functional module is formally verified based on the sub-functional modules, which not only guarantees the formal verification of the functional modules Stable and reliable, and effectively shorten the running time of formal verification, and further improve the quality and efficiency of formal verification.

FIG. 6 is a schematic flowchart of another method for formal verification of a chip provided by an embodiment of the present invention; on the basis of any of the foregoing embodiments, and with continued reference to FIG. 6, the method in this embodiment may further include:

Step S601: Detect whether the integrated netlist is updated.

Step S602: When the integrated netlist is updated, determine the updated part of the netlist corresponding to the integrated netlist.

Step S603: Obtain at least one update function module corresponding to the update part of the netlist.

Step S604: Perform formal verification on only at least one update function module.

During the chip design process, the integrated netlist can be updated and optimized according to design requirements or formal verification results. At this time, in order to ensure the quality and efficiency of the formal verification of the updated integrated netlist, the integrated netlist can be detected and analyzed to detect whether the integrated netlist is updated, specifically, when the integrated netlist is updated One achievable way is to detect whether the integrated netlist is updated according to a preset detection cycle; or, another achievable way is to detect whether the integrated netlist is updated in real time.

Specifically, the process of detecting whether the comprehensive netlist has been updated may include: obtaining the current comprehensive netlist, and then analyzing and comparing the current comprehensive netlist with the historical comprehensive netlist, and when the current comprehensive netlist is the same as the historical comprehensive netlist, then It can be determined that the comprehensive netlist has not been updated; when the current comprehensive netlist is different from the historical comprehensive netlist, it can be determined that the comprehensive netlist is updated, that is, the comprehensive netlist is updated from the historical comprehensive netlist to the current comprehensive netlist. Of course, those skilled in the art can also use other methods to detect whether the integrated netlist has been updated, as long as the accuracy and reliability of the detection of whether the integrated netlist has been updated can be guaranteed.

Further, when the detection result is that the integrated netlist is updated, the update part of the netlist corresponding to the integrated netlist can be determined, and then at least one update function module corresponding to the update part of the netlist can be obtained. After the functional modules are updated, formal verification may be performed on only at least one updated functional module.

For example, there are integrated netlist one and integrated netlist two. The integrated netlist one includes: netlist part W1, netlist part W2, netlist part W3, and netlist part W4. Integrated netlist two includes There are netlist part W1, netlist part W2, netlist part W`3 and netlist part W`4. By analyzing and comparing the above two comprehensive netlists, it can be determined that the netlist update part is the second comprehensive netlist. The included netlist part W`3 and netlist part W`4. After the update part of the netlist is obtained, at least one update function module corresponding to the update part of the netlist can be determined. For example, the update function module includes a function module C and a function module D. At this time, the integrated netlist corresponds to When the other functional modules of the system pass the formal verification, the formal verification can only be performed on at least one updated functional module, thereby effectively improving the quality and efficiency of the formal verification operation.

In this embodiment, by detecting whether the comprehensive netlist is updated, when the comprehensive netlist is updated, the netlist update part corresponding to the comprehensive netlist is determined; then at least one update function module corresponding to the netlist update part is obtained , And only perform formal verification on at least one update function module, which effectively realizes that when encountering the modification and iteration of the integrated netlist, the update function module corresponding to the modification iteration operation can be quickly iterated. In the case that other functional modules pass the formal verification operation, formal verification can only be performed on the updated functional module, which further ensures the quality and efficiency of formal verification.

Fig. 7 is a schematic flow chart of another method for formal verification of a chip provided by an embodiment of the present invention; on the basis of any of the foregoing embodiments, referring to Fig. 7, in the process of formal verification of the integrated netlist It is possible to iteratively modify the integrated netlist, and the process of modifying iterative is often only a part of the integrated netlist. At this time, in order to improve the quality and efficiency of the formal verification of the integrated netlist, the functional modules in the integrated netlist that have passed the formal verification and have not undergone iterative modification do not need to perform formal verification again. Specifically, in order to be able to implement the above technical solution, before performing formal verification on the integrated netlist based on multiple functional modules, the method in this embodiment may further include:

Step S701: Identify whether the functional module passes the formal verification.

Step S702: When the functional module passes the formal verification, the functional module is set as a black box module that is used to identify the formal verification.

Specifically, before performing formal verification on the integrated netlist based on multiple functional modules, it can be identified whether the functional module has passed the formal verification. If the functional module has passed the formal verification, the functional module can be set to identify that it has passed the formal verification. In order to perform formal verification operations on the integrated netlist again next time, there is no need to perform formal verification operations on the black box module again, and only need to perform formal verification on other functional modules that have not passed the formal verification, which effectively shortens The time required for formal verification is improved, and the quality and efficiency of formal verification are further improved.

For example, after the integrated netlist is divided into functional module A, functional module B, functional module C, and functional module D, the above functional modules can be analyzed and identified to identify whether the functional modules pass formal verification, assuming that the functional modules A and functional module D pass formal verification, while functional module B and functional module C fail formal verification. At this time, functional module A and functional module D are set as black box modules. Specifically, functional module A and functional module D can be set The identification information of the black box module is added to the top, so that the black box module can be quickly distinguished from other functional modules, and it is convenient to perform formal verification operations on other functional modules.

Fig. 8 is a schematic flow chart of another method for formal verification of a chip provided by an embodiment of the present invention; on the basis of the above-mentioned embodiment, referring to Fig. 8, the integrated network based on multiple functional modules in this embodiment Formal verification of tables can include:

Step S801: Identify whether a black box module that has passed formal verification is included in the plurality of functional modules.

Step S802: If the multiple functional modules include a black box module, perform formal verification on the functional modules other than the black box module in the multiple functional modules.

Specifically, when performing formal verification on multiple functional modules, in order to further improve the quality and efficiency of formal verification, it can be identified whether the multiple functional modules include black box modules that have passed formal verification, and the multiple functional modules include black boxes. In the case of box modules, formal verification can be performed on other functional modules among multiple functional modules except for the black box module.

For example, multiple functional modules include functional module A, functional module B, functional module C, and functional module D. Then, by analyzing and identifying the aforementioned multiple functional modules, it can be known that the aforementioned functional module B and functional module C have been For black box modules that pass formal verification, at this time, when performing formal verification on multiple functional modules, you can only perform formal verification on functional module A and functional module D, without formal verification on functional module B and functional module C verification. This effectively shortens the time required for formal verification and further improves the quality and efficiency of formal verification.

Fig. 9 is a schematic flow chart of another method for formal verification of a chip provided by an embodiment of the present invention; on the basis of any of the above embodiments, referring to Fig. 9, the integrated netlist includes in addition to multiple functional modules At this time, the method in this embodiment may also include:

Step S901: Obtain a verification request for the register transfer level code.

Step S902: Perform formal verification on the register transfer level code according to the verification request.

Among them, as shown in Figure 10, the integrated netlist may include multiple functional modules and other areas. The other areas are set around the functional modules, and other areas may include register transfer stages other than the functional modules. For codes, users can not only put forward formal verification requirements for functional modules, but also put forward formal verification requirements for register transfer-level codes in other areas. When the user's verification request for the register transfer level code in other areas is obtained, the register transmitter code in other areas can be formally verified according to the verification request. The specific implementation of the formal verification operation is the same as the above-mentioned pair of functional modules. The specific implementation of formal verification is similar. For details, please refer to the above statement, which will not be repeated here.

In specific applications, this application embodiment provides a formal verification method, which divides the comprehensive netlist into multiple logical combination modules, and then implements the formal verification operation on the comprehensive netlist based on the multiple logical combination modules, thereby ensuring The stability and reliability of the formal verification of the integrated netlist is achieved. Specifically, when the integrated netlist is divided into modules, the resources and time required for formal verification are comprehensively considered. After the logical combination module is divided and fixed, the formal verification operation can be performed on the logical combination module. If there is a problem in the formal verification process of the logical combination module, the logical combination module can be hierarchically divided again, and then the logical combination module can be processed based on the hierarchical division operation. The subsequent multiple sub-logic combination modules perform formal verification operations again, which effectively shortens the running time required for formal verification operations. At the same time, when it is necessary to modify and iterate the integrated netlist, you can only modify the iterative part The corresponding module performs formal verification operations.

Specifically, as shown in Fig. 2, the comprehensive netlist is divided into functional module A, functional module B, functional module C, and functional module D as an example for description:

Application scenario 1, formal verification methods can include:

Step 1: Perform formal verification on function module A, function module B, function module C and function module D separately.

Step 2: After functional module A, functional module B, functional module C, and functional module D pass the formal verification, formal verification can be performed on the whole composed of functional module A, functional module B, functional module C, and functional module D.

Application scenario two, formal verification methods can include:

Step 11: Perform formal verification on functional module unit one composed of functional module A and functional module B, and functional module unit two composed of functional module C and functional module D.

Step 12: After the above-mentioned functional module unit 1 and functional module unit 2 pass the formal verification, formal verification can be performed on the whole constituted by the functional module A, the functional module B, the functional module C, and the functional module D.

Application scenario three, formal verification methods can include:

Step 111: Perform formal verification on function module A, function module B, function module C, and function module D separately.

Step 112: After the functional module A and the functional module C have not been formally verified, and the functional module B and the functional module D have passed the formal verification, the functional module A and the functional module C can be divided again according to the designed function.

For example: functional module A can be divided into sub functional module A1 and sub functional module A2, functional module C can be divided into sub functional module C1, sub functional module C2 and sub functional module C3, etc., while functional module B and functional module D can be Identified as a verified black box module.

Step 113: Perform formal verification on functional module A and functional module C based on the sub-functional modules. After functional module A and functional module C pass the formal verification, functional module A, functional module B, functional module C, and functional module The whole constituted by D is formally verified.

Application scenario 4: In this application embodiment, there is an update operation on the integrated netlist. In this case, the formal verification method may include:

Step 1111: Based on the update operation performed on the integrated netlist, determine the update function module corresponding to the update operation.

Step 1112: Assume that the updated functional module is functional module D. At this time, when the aforementioned functional module A, functional module B, and functional module C are all black box modules, only functional module D can be formally verified.

Step 1113: After the functional module D passes the formal verification, formal verification can be performed on the whole constituted by the functional module A, the functional module B, the functional module C, and the functional module D.

It should be noted that in any of the above application scenarios, when the integrated netlist or functional module is divided into modules, the divided modules may or may not have boundary and level information. Or when the sub-function module does not have boundary and hierarchical information, it will affect the integrated optimization of area, power consumption and performance. Therefore, preferably, the divided modules or sub-modules can have boundary and level information.

The formal verification method provided by this application embodiment realizes a friendly comprehensive configuration of the comprehensive netlist (that is, the module division operation on the comprehensive netlist), which greatly improves the efficiency of formal verification and facilitates the automation of formal verification operations; In addition, after the integrated netlist is divided into modules, the formal verification operation of the integrated netlist is realized through the divided modules, which effectively reduces the verification time and resources required for the formal verification operation from the design code to the integrated netlist. , And then achieve the efficiency of formal verification and reduce resource occupation; at the same time, it can also ensure that the comprehensive area, power consumption and performance optimization are not excessively affected, thereby effectively reducing the need to modify the RTL code in the later stage of the chip design project. Affected the iteration time required for formal verification operations.

FIG. 11 is a schematic structural diagram of a formal verification device for a chip provided by an embodiment of the present invention. Referring to FIG. 11, this embodiment provides a chip formal verification device, which can execute the formal verification method shown in FIG. 1 above. Specifically, the formal verification device may include:

The memory 12 is used to store computer programs;

The processor 11 is configured to run a computer program stored in the memory 12 to realize:

Obtain a comprehensive netlist corresponding to the chip design code;

Divide the comprehensive netlist into multiple functional modules according to design functions, where each functional module has boundary and level information, and the division of multiple functional modules does not change the logical hierarchical structure of the register transfer level corresponding to the comprehensive netlist;

Formal verification of the integrated netlist based on multiple functional modules.

The structure of the formal verification device may also include a communication interface 13 for the electronic device to communicate with other devices or a communication network.

In some instances, when the processor 11 performs formal verification on the integrated netlist based on multiple functional modules, the processor 11 is configured to perform at least one of the following: perform formal verification on at least one of the multiple functional modules separately; Perform formal verification on at least one functional module unit including at least two functional modules; perform formal verification on the whole constituted by all functional modules.

In some instances, when the processor 11 performs formal verification on the integrated netlist based on multiple functional modules, the processor 11 is further configured to: for multiple functional modules, detect whether the state of the functional modules performing formal verification is a normal state.

In some instances, when the processor 11 detects whether the state of the functional module performing formal verification is normal, the processor 11 is also used to: obtain the verification time corresponding to the functional module; and detect the formal verification of the functional module according to the verification time. Whether the status is normal.

In some instances, when the processor 11 detects whether the state of the functional module performing formal verification is normal according to the verification time, the processor 11 is further configured to: when the verification time is less than a preset time threshold, determine that the functional module performs formal verification When the verification time is greater than or equal to the preset time threshold, it is determined that the state of the functional module for formal verification is an abnormal state.

In some instances, after determining that the state of the functional module performing formal verification is an abnormal state, the processor 11 is further configured to: divide the functional module into multiple sub-functional modules, where each sub-functional module has boundary and level information; A sub-function module performs formal verification on the function module.

In some instances, when the processor 11 divides the functional module into multiple sub-functional modules, the processor 11 is used to: obtain module design information corresponding to the functional module; and divide the functional module into multiple sub-functional modules according to the module design information .

In some instances, the processor 11 is also used to: detect whether the integrated netlist is updated; when the integrated netlist is updated, determine the update part of the netlist corresponding to the integrated netlist; obtain the update part corresponding to the netlist At least one update function module; only perform formal verification on at least one update function module.

In some instances, before performing formal verification on the integrated netlist based on multiple functional modules, the processor 11 is also used to: identify whether the functional module passes the formal verification; when the functional module passes the formal verification, set the functional module to be used for Identifies black box modules that have passed formal verification.

In some instances, when the processor 11 performs formal verification on the integrated netlist based on multiple functional modules, the processor 11 is also used to: identify whether the multiple functional modules include black box modules that have passed formal verification; When the black box module is included in the functional module, formal verification is performed on the functional modules other than the black box module among the multiple functional modules.

In some instances, the comprehensive netlist includes register transfer-level codes in addition to multiple functional modules, and the processor 11 is also used to: obtain a verification request for the register transfer-level code; form the register transfer-level code according to the verification request verification.

The device shown in Fig. 11 can execute the methods of the embodiments shown in Figs. For the implementation process and technical effects of this technical solution, please refer to the description in the embodiment shown in FIG.

In addition, an embodiment of the present invention provides a computer storage medium for storing computer software instructions used by an electronic device, which includes instructions for executing the formal verification method of the chip in the method embodiments shown in FIGS. 1 to 10 above. program.

The technical solutions and technical features in each of the above embodiments can be singly or combined in case of conflict with the present invention, as long as they do not exceed the cognitive scope of those skilled in the art, they all belong to the equivalent embodiments within the protection scope of this application. .

In the several embodiments provided in the present invention, it should be understood that the method disclosed in the present invention can be implemented in other ways. For example, the above-described embodiments of the formal verification method, device, and storage medium for a chip are only illustrative. For example, multiple units or components can be combined or integrated into another system, or some features can be omitted or not implemented.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present invention essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. , Including several instructions to make a computer processor (processor) execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage media include: U disk, mobile hard disk, Read-Only Memory (ROM), Random Access Memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes.

The above are only the embodiments of the present invention, which do not limit the scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the description and drawings of the present invention, or directly or indirectly applied to other related technologies In the same way, all fields are included in the scope of patent protection of the present invention.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention. range.

Claims (23)

1. A method for formal verification of a chip, which is characterized in that it comprises:

   Obtain a comprehensive netlist corresponding to the chip design code;

   Divide the comprehensive netlist into multiple functional modules according to design functions, where each functional module has boundary and level information, and the division of multiple functional modules does not change the register corresponding to the comprehensive netlist The logical hierarchy of the transmission level;

   Perform formal verification on the integrated netlist based on a plurality of the functional modules.
2. The method according to claim 1, wherein the formal verification of the integrated netlist based on a plurality of the functional modules includes at least one of the following:

   Performing formal verification on at least one of the plurality of functional modules separately;

   Perform formal verification on at least one functional module unit including at least two functional modules;

   Perform formal verification on the whole composed of all functional modules.
3. The method according to claim 1, wherein when performing formal verification on the integrated netlist based on a plurality of the functional modules, the method further comprises:

   For a plurality of functional modules, it is detected whether the state in which the functional module performs formal verification is a normal state.
4. The method according to claim 3, wherein the detecting whether the state of the formal verification performed by the functional module is a normal state comprises:

   Obtaining the verification time corresponding to the functional module;

   According to the verification time, it is detected whether the state of the functional module performing the formal verification is a normal state.
5. The method according to claim 4, wherein detecting whether the state of the functional module performing formal verification is a normal state according to the verification time comprises:

   When the verification time is less than a preset time threshold, it is determined that the state in which the functional module performs formal verification is a normal state;

   When the verification time is greater than or equal to the preset time threshold, it is determined that the state in which the functional module performs formal verification is an abnormal state.
6. The method according to claim 3, wherein after determining that the state of the functional module performing formal verification is an abnormal state, the method further comprises:

   Dividing the functional module into a plurality of sub-functional modules, wherein each of the sub-functional modules has boundary and level information;

   Perform formal verification on the functional module based on a plurality of the sub-functional modules.
7. The method according to claim 6, wherein dividing the functional module into a plurality of sub-functional modules comprises:

   Acquiring module design information corresponding to the functional module;

   The functional module is divided into multiple sub-functional modules according to the module design information.
8. The method according to any one of claims 1-7, wherein the method further comprises:

   Detecting whether the comprehensive netlist is updated;

   When the integrated netlist is updated, determine the updated part of the netlist corresponding to the integrated netlist;

   Acquiring at least one update function module corresponding to the netlist update part;

   Only perform formal verification on at least one of the update function modules.
9. The method according to any one of claims 1-7, characterized in that, before performing formal verification on the integrated netlist based on a plurality of the functional modules, the method further comprises:

   Identify whether the functional module passes formal verification;

   When the functional module passes the formal verification, the functional module is set as a black box module that is used to identify the formal verification.
10. The method according to claim 9, wherein the formal verification of the integrated netlist based on a plurality of the functional modules comprises:

    Identifying whether a black box module that has passed formal verification is included in the plurality of functional modules;

    When a black box module is included in the plurality of functional modules, formal verification is performed on the functional modules other than the black box module in the plurality of functional modules.
11. The method according to any one of claims 1-7, wherein the comprehensive netlist includes register transfer level codes other than a plurality of functional modules, and the method further comprises:

    Obtaining a verification request for the register transfer-level code;

    Perform formal verification on the register transfer level code according to the verification request.
12. A formal verification device for a chip, characterized in that it comprises:

    Memory, used to store computer programs;

    The processor is configured to run a computer program stored in the memory to realize:

    Obtain a comprehensive netlist corresponding to the chip design code;

    Divide the comprehensive netlist into multiple functional modules according to design functions, where each functional module has boundary and level information, and the division of multiple functional modules does not change the register corresponding to the comprehensive netlist The logical hierarchy of the transmission level;

    Perform formal verification on the integrated netlist based on a plurality of the functional modules.
13. The device according to claim 12, wherein when the processor performs formal verification on the integrated netlist based on a plurality of the functional modules, the processor is configured to perform at least one of the following:

    Performing formal verification on at least one of the plurality of functional modules separately;

    Perform formal verification on at least one functional module unit including at least two functional modules;

    Perform formal verification on the whole composed of all functional modules.
14. The device according to claim 12, wherein when the processor performs formal verification on the integrated netlist based on a plurality of the functional modules, the processor is further configured to:

    For a plurality of functional modules, it is detected whether the state in which the functional module performs formal verification is a normal state.
15. The device according to claim 14, wherein when the processor detects whether the state of the functional module performing formal verification is a normal state, the processor is further configured to:

    Obtaining the verification time corresponding to the functional module;

    According to the verification time, it is detected whether the state of the functional module performing the formal verification is a normal state.
16. The device according to claim 15, wherein when the processor detects whether the state of the functional module performing formal verification is a normal state according to the verification time, the processor is further configured to:

    When the verification time is less than a preset time threshold, it is determined that the state in which the functional module performs formal verification is a normal state;

    When the verification time is greater than or equal to the preset time threshold, it is determined that the state in which the functional module performs formal verification is an abnormal state.
17. The device according to claim 14, wherein after determining that the state of the functional module performing formal verification is an abnormal state, the processor is further configured to:

    Dividing the functional module into a plurality of sub-functional modules, wherein each of the sub-functional modules has boundary and level information;

    Perform formal verification on the functional module based on a plurality of the sub-functional modules.
18. The device according to claim 17, wherein when the processor divides the functional module into multiple sub-functional modules, the processor is further configured to:

    Acquiring module design information corresponding to the functional module;

    The functional module is divided into multiple sub-functional modules according to the module design information.
19. The device according to any one of claims 12-18, wherein the processor is further configured to:

    Detecting whether the comprehensive netlist is updated;

    When the integrated netlist is updated, determine the updated part of the netlist corresponding to the integrated netlist;

    Acquiring at least one update function module corresponding to the netlist update part;

    Only perform formal verification on at least one of the update function modules.
20. The device according to any one of claims 12-18, wherein, before performing formal verification on the integrated netlist based on a plurality of the functional modules, the processor is further configured to:

    Identify whether the functional module passes formal verification;

    When the functional module passes the formal verification, the functional module is set as a black box module that is used to identify the formal verification.
21. The device according to claim 20, wherein when the processor performs formal verification on the integrated netlist based on a plurality of the functional modules, the processor is further configured to:

    Identifying whether a black box module that has passed formal verification is included in the plurality of functional modules;

    When a black box module is included in the plurality of functional modules, formal verification is performed on the functional modules other than the black box module in the plurality of functional modules.
22. The device according to any one of claims 12-18, wherein the comprehensive netlist includes register transfer-level code in addition to multiple functional modules, and the processor is further configured to:

    Obtaining a verification request for the register transfer-level code;

    Perform formal verification on the register transfer level code according to the verification request.
23. A computer-readable storage medium, wherein the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used to implement any one of claims 1-11 The method of formal verification of the chip described in item.

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