CN105867878A

CN105867878A - High-speed parallel true random number generator

Info

Publication number: CN105867878A
Application number: CN201610268917.9A
Authority: CN
Inventors: 史久根; 邾伟; 贾坤荥; 徐颖; 许辉亮; 陆立鹏
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2016-04-26
Filing date: 2016-04-26
Publication date: 2016-08-17

Abstract

The invention discloses a high-speed parallel true random number generator. The generator comprises a random source, a collector and a data processing part. The generator is characterized in that the random source uses oscillation ring shaking generated in an FPGA (field programmable gate array), and the collector collects shaking random signals; the data processing part processes collected random signals and generates high-speed and parallel true random numbers. The method is based on an FPGA system, oscillation ring collecting system clock shaking in the FPGA is used as original random number signals, high-speed and parallel random numbers with good randomness are obtained through correction and parallel processing, and the generator has good randomness and reliability.

Description

A kind of high-speed parallel real random number generator

Technical field

The present invention relates to a kind of truly random generator and method for generation, send out particularly to a kind of high-speed parallel true random number Raw device and production method.

Background technology

Along with making rapid progress of science and technology, randomizer (RNG) has a wide range of applications in many aspects, as logical Letter safety, amusement, music, image multimedia, simulate and test, mathematics, ecommerce E-Government etc..This project just should A kind of realization for the randomizer of image procossing.Owing to hardware real random number generator (TRNG) is on randomness There is the advantage that software pseudorandom number generator (PRNG) is impassable.The design generates high-speed parallel random number based on FPGA, Velocity-stabilization, meets random number requirement.

Summary of the invention

It is an object of the invention to the FPGA inherent character utilized, a kind of hardware of design realizes simple, the good height of randomness with Parallel random number generation equipment.

The present invention solves technical problem and adopts the following technical scheme that

A kind of for high-speed parallel real random number generator system, including stochastic source, data acquisition unit, data processor；It is special Levy and be: described stochastic source provides original stochastic signal based on FPGA clock source, and described data acquisition unit is by multiple concussions Ring and XOR gate composition, the plurality of concussion ring gathers original stochastic signal respectively, after XOR gate processes, obtains random The more preferable continuous print serial stochastic signal of property, continuous print serial stochastic signal is after the correction, serioparallel exchange of data processor Obtain parallel random data signal, as random number seed；

Described stochastic source provides original stochastic signal based on FPGA clock source, and described FPGA clock source includes high-speed clock source CLK0, low-speed clock source CLK1；Described data acquisition unit 2 is made up of 3 concussion rings and XOR gate, described each shake Swinging ring to include and door, buffer chain, phase inverter and d type flip flop, high-speed clock source CLK0 accesses the input with door, defeated with door Going out to terminate into buffer chain, the outfan of buffer chain accesses phase inverter, the outfan output feedback of phase inverter respectively with door input With d type flip flop input；Meanwhile, low-speed clock source CLK1, as the clock signal of d type flip flop, gathers the output knot of phase inverter Really, original stochastic signal is obtained；

Described buffer chain includes the buffer that three head and the tail are sequentially connected, respectively buffer 0, buffer 1, buffer 2.

Described data processing section includes Feng's. Nuo Yiman corrector, FIFO, LSFR, before described Feng's. Nuo Yiman corrector End connects XOR gate, and described XOR gate carries out XOR process to described multichannel stochastic signal, generates a bit binary data；Two enter Data processed process through von Neumann corrector, form the random bit string that randomness is good；Described random bit string inputs extremely After FIFO going here and there and converting FIFO output speed stable, at a high speed, parallel random number sequence, described random number sequence conduct Random number seed inputs in described LFSR, for subsequent treatment.

High-speed parallel real random number generator of the present invention produces the method for high-speed parallel true random number and comprises the following steps:

(1) described high-speed clock source CLK0 is as in described stochastic source input signal to described concussion ring；

(2) described concussion ring output stochastic signal, after XOR gate processes, generates 0 or 1 random number, and this random number inputs extremely Described von Neumann corrector；

(3) random number is corrected by described von Neumann corrector, and well but speed shakiness needs to carry out to obtain randomness The bit string that string turns and processes；

(4) randomness is good but speed shakiness needs to carry out string and turns and the bit string input that processes carries out serioparallel exchange to FIFO；

(5) the parallel random number of the output of described FIFO is as random seed, after utilizing LFSR algorithm process, for actually used；

(6) random seed of input is processed by described LSFR, without new random number seed input, the most described LFSR By current output feedback result as the input of LSFR, carry out random number process next time；If there being new random number seed Input, then process new random number seed and generate random number sequence；Constantly change the input random seed of LSFR, obtain random The good high speed of property, parallel true random number sequence.

The present invention provides the benefit that against existing technologies:

1, hardware realizes simple

Utilize FPGA clock to produce stochastic source, stochastic source sampling is produced and organizes random number more, random number is carried out XOR, correction etc. Process, produce and stablize parallel random number at a high speed；

2, random quality is good

This programme, gathers multichannel stochastic signal, multichannel stochastic signal is carried out XOR process, utilizes von Neumann corrector to enter Row correction, it is ensured that the random number of generation has more preferable stochastic behaviour compared with similar scheme.

3, parallel, stable

Utilize the inherent characteristics of FIFO, the parallelization to serial data can be realized simultaneously and process and stable output.

4, at a high speed

Constantly change the input seed of LSFR, the good high speed of randomness, parallel true random number sequence can be obtained.

Accompanying drawing explanation

Fig. 1 is the system entire block diagram of the present invention；

Fig. 2 is the system logic structure figure of the present invention；

Fig. 3 is the data acquisition schematic diagram of the present invention；

Fig. 4 is the concussion ring schematic diagram of the present invention；

Fig. 5 is that the data of the present invention process schematic diagram.

Detailed description of the invention

As shown in Figure 1-2, a kind of for high-speed parallel real random number generator system, including stochastic source, data acquisition unit, Data processor；It is characterized in that: described stochastic source provides original stochastic signal, described data acquisition based on FPGA clock source Device is made up of multiple concussion rings and XOR gate, and the plurality of concussion ring gathers original stochastic signal, respectively through XOR gate After process, obtaining randomness more preferable continuous print serial stochastic signal, continuous print serial stochastic signal is through data processor 3 Parallel random data signal is obtained, as random number seed after correction, serioparallel exchange；

As in Figure 3-5, described stochastic source provides original stochastic signal based on FPGA clock source, and described FPGA clock source includes High-speed clock source CLK0, low-speed clock source CLK1；Described data acquisition unit is made up of 3 concussion rings and XOR gate, institute The each concussion ring stated includes and door, buffer chain, phase inverter and d type flip flop, and high-speed clock source CLK0 accesses the input with door End, accesses buffer chain with the outfan of door, and the outfan of buffer chain accesses phase inverter, and the outfan output feedback of phase inverter is respectively With door input and d type flip flop input；Meanwhile, low-speed clock source CLK1, as the clock signal of d type flip flop, gathers phase inverter Output result, obtain original stochastic signal；

As it is shown in figure 5, described data processor includes Feng's. Nuo Yiman corrector, FIFO, LSFR, described Feng. Nuo Yiman school Positive device front end connects XOR gate, and described XOR gate carries out XOR process to described multichannel stochastic signal, generates a bit According to；Binary data processes through von Neumann corrector, forms the random bit string that randomness is good；Described random bit string is defeated Enter after going here and there to FIFO and converting, FIFO output speed is stable, at a high speed, parallel random number sequence, described random number sequence Arrange and input in described LFSR as random number seed, for subsequent treatment.

Described Feng's. Nuo Yiman corrector is as follows with the combination of output to the input of binary data timing:

(1) input is combined as " 01 ", is output as 0；

(2) input is combined as " 10 ", is output as 1；

(3) input is combined as " 00 ", without output；

(4) input is combined as " 11 ", without output；

After described Feng's. Nuo Yiman corrector processes, obtain that the higher serial of randomness is non-at the uniform velocity exports random bit string, will be with Seat in the plane string inputs to FIFO, obtains 32 stable parallel-by-bit random number seeds.

The process that described FIFO processes random bit string is as follows:

(1) during random bit string is input to FIFO, and it is buffered in the RAM of described FIFO；

(2) described FIFO has two input states to external world, EMPTY and FULL, when the RAM within FIFO is empty, the most defeated Go out for " EMPTY=1, FULL=0 ", after FIFO internal data is full, be externally output as " EMPTY=0, FULL=1 "；

(3) described FIFO constantly receives continuous print random bit string, exports 32 stable parallel-by-bit randoms number；

Parallel random number through FIFO output can be input to described LSFR locate at random as the random number seed of system Reason, further enhances randomness；The processing procedure that described LSFR degree random number seed carries out random process is as follows:

(1) described LSFR software realizes, and for a random number seed, can obtain organizing random number list entries more；

(2) described LSFR module is operated in fast state, ceaselessly to system input random number combination；

(3) described FIFO ceaselessly inputs original random number seed to described LSFR；

(4) need the regular hour owing to described FIFO processes random bit string, thus its output speed is less than the defeated of described LFSR Go out speed；

(5) the parallel random number of input is processed by described LSFR, without new random number seed input, then described LFSR as the input of LSFR, carries out random number process next time by current output feedback result；If there being new random number Seed inputs, then process new random number seed and generate random number sequence；

(6) constantly change the input seed of LSFR, obtain the good high speed of randomness, parallel true random number sequence.

Claims

1. a high-speed parallel real random number generator, including stochastic source, data acquisition unit, data processor；It is characterized in that: Described stochastic source provides original stochastic signal based on FPGA clock source, and described data acquisition unit is by multiple concussion rings and different Or door composition, the plurality of concussion ring gathers original stochastic signal respectively, after XOR gate processes, obtains randomness more preferable Continuous print serial stochastic signal, continuous print serial stochastic signal obtains after the correction, serioparallel exchange of data processor parallel Random data signal, as random number seed；

Described stochastic source provides original stochastic signal based on FPGA clock source, and described FPGA clock source includes high-speed clock source CLK0, low-speed clock source CLK1；

Described data acquisition unit is made up of 3 concussion rings and XOR gate, and described each concussion ring includes and door, buffering Chain, phase inverter and d type flip flop, high-speed clock source CLK0 accesses the input with door, accesses buffer chain with the outfan of door, slow Rush chain outfan access phase inverter, phase inverter outfan output feedback respectively with door input and d type flip flop input；With Time, low-speed clock source CLK1, as the clock signal of d type flip flop, gathers the output result of phase inverter, obtains original stochastic signal；

Described data processing section includes Feng's. Nuo Yiman corrector, FIFO, LSFR, and described Feng's. Nuo Yiman corrector front end is even Connecing XOR gate, described XOR gate carries out XOR process to described multichannel stochastic signal, generates a bit binary data；Binary number Process according to through von Neumann corrector, form the random bit string that randomness is good；Described random bit string inputs to FIFO After going here and there and converting FIFO output speed stable, at a high speed, parallel random number sequence, described random number sequence is as random number Seed inputs in described LFSR, for subsequent treatment.

High-speed parallel real random number generator the most according to claim 1, it is characterised in that produce high-speed parallel true random number Method comprises the following steps:

3. according to the high-speed parallel real random number generator described in any one of claim 1-2, it is characterised in that: described buffering Chain includes the buffer that three head and the tail are sequentially connected, respectively buffer 0, buffer 1, buffer 2.

4. according to a kind of high-speed parallel real random number generator described in any one of claim 1-2, it is characterised in that: described Parallel true random number sequence width is 32bit.