CN106549578A - Multi-mode power source managing system - Google Patents
Multi-mode power source managing system Download PDFInfo
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- CN106549578A CN106549578A CN201611192092.3A CN201611192092A CN106549578A CN 106549578 A CN106549578 A CN 106549578A CN 201611192092 A CN201611192092 A CN 201611192092A CN 106549578 A CN106549578 A CN 106549578A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- Dc-Dc Converters (AREA)
Abstract
The invention provides a kind of multi-mode power source managing system, it is adaptable to SOC.The multi-mode power source managing system includes digital circuit, analog circuit and converter output stage, wherein described analog circuit is connected to the digital circuit, and which includes simulating PFM control circuit, digital PWM control circuit, a LDO control circuits and the 2nd LDO control circuits；The simulation PFM control circuit, digital PWM control circuit, a LDO control circuits and the 2nd LDO control circuits constitute output driving unit, for providing output drive signal to the converter power output stage, the output drive signal is used to drive the converter power output stage to realize respectively simulating the voltage output of PFM Switching Power Supply output modes, digital PWM Switching Power Supply output mode, Switching Power Supply topology LDO output modes and LDO output modes.
Description
【Technical field】
The present invention relates to power technology, especially, (System on a chip on piece are suitable for SOC to be related to one kind
System) chip multi-mode power source managing system.
【Background technology】
It is well known that SOC generally needs using power-supply management system to carry out stable confession to chip internal circuits
Electricity.
Power-supply management system of the prior art typically adopts analog switched power supply or digital switch power supply.Analog switch
Power supply needs to redesign new backfeed loop, proving period ratio when application conditions change or need to be transferred to new technology
It is longer；Also, feedback control loop there is a possibility that unstable in new design and new technology so that power-supply management system risk compared with
Greatly, product is affected quickly to cut market.
If the power-supply management system in the SOC of prior art uses digital switch power supply, although digital switch
Power supply can adapt to different applications and technological requirement better, but the switch bandwidth ratio of pure digi-tal Switching Power Supply is relatively low,
Load change makes power supply ripple larger soon, therefore its scope of application is relatively limited.On the other hand, switching power supply noise is likely to shadow
Other sensitive circuits to SOC are rung, and efficiency can occur to decline when low-voltage is input into.
In view of this, it is necessary to provide a kind of multi-mode power source managing system suitable for SOC, to solve existing skill
The problems referred to above that art is present.
【The content of the invention】
It is an object of the invention to provide a kind of multi-mode power source managing system that can be solved the above problems.
The present invention provides a kind of multi-mode power source managing system, including digital circuit, analog circuit and converter output stage,
Wherein described analog circuit is connected to the digital circuit, and it include simulating PFM control circuit, digital PWM control circuit, the
One LDO control circuits and the 2nd LDO control circuits；The simulation PFM control circuit, digital PWM control circuit, LDO controls
Circuit processed and the 2nd LDO control circuits constitute output driving unit, drive for providing output to the converter power output stage
Dynamic signal, the output drive signal are used to drive the converter power output stage to realize that simulation PFM Switching Power Supplies are defeated respectively
The voltage of exit pattern, digital PWM Switching Power Supply output mode, Switching Power Supply topology LDO output modes and LDO output modes is defeated
Go out.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating converter power output stage includes the first PMOS switch, the second PMOS switch and nmos switch, wherein, a PMOS is opened
Close, the second PMOS switch and nmos switch are connected to the output driving unit, provide for receiving the output driving unit
Output drive signal；The source ground of wherein described nmos switch, and its drain electrode is connected to the leakage of first PMOS switch
Pole, and export as power stage；The source electrode of first PMOS switch and second PMOS switch is connected to power power-supply；Institute
The drain electrode for stating the second PMOS switch is connected to voltage output end, and described in power stage output is connected to by alternative device
Voltage output end, and the voltage output end is by output capacitance ground connection.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating output drive signal is included for driving PMOS grid control signals of first PMOS switch, described for driving
2nd PMOS grid control signals of the second PMOS switch and the NMOS gate control signal for driving the nmos switch.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment,
The simulation PFM Switching Power Supplies output mode and the digital PWM Switching Power Supply output mode, second PMOS switch are in
Off state, and the simulation PFM control circuit and the digital PWM control circuit by a PMOS grid control signals and
NMOS gate control signal drives first PMOS switch and the nmos switch so which constitutes synchronous complementary switch.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment,
Under the Switching Power Supply topology LDO output modes, first PMOS switch and the nmos switch are off state；It is described
2nd PMOS grids described in 2nd LDO control circuit outputs control letter to drive second PMOS switch to form Switching Power Supply mould
The LDO outputs of formula, wherein, the replaceable components adopts inductance element.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment,
Under the LDO output modes, second PMOS switch and the nmos switch are off state；The first LDO controls
A PMOS grids described in circuit output control letter to drive first PMOS switch to form LDO outputs, wherein, it is described to replace
Change element and adopt Zero-ohm resistor.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating digital circuit includes LDO loop control units, PFM mode parameters control unit and digital PWM loop filtering unit, wherein institute
State LDO loop control units and be connected to a LDO control circuits and the 2nd LDO control circuits, for described
One LDO control circuits and the first bus voltage of the 2nd LDO control circuit outputs and the second bus voltage, the PFM patterns
Parameter control unit is connected to the simulation PFM control circuit, for exporting the 3rd bus electricity to the simulation PFM control circuit
Pressure and the first clock signal；The digital PWM loop filtering unit is connected to the digital PWM control circuit, for described
Digital PWM control circuit exports the 4th bus voltage and second clock signal.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating digital circuit also includes mode of operation select unit, and which is connected to the LDO loops control unit, the PFM mode parameters
Control unit and the digital PWM loop filtering unit, for being configured according to the output of register configuration interface and being input into electricity
Pressure sampled value, optionally carries out LDO loops control enable, the 2nd LDO loops control enable, simulation PFM loop controls
Enable and the control of digital PWM loop is enabled.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating simulation PFM mode control circuits includes the high-speed comparator of introducing hysteresis module, and which is used to compare output feedback voltage with ginseng
Voltage is examined, wherein the hysteresis module includes digital logic unit and 2 selects 1 multiplexer, wherein the output of the high-speed comparator
Described 2 are fed back to by the digital logic unit select 1 multiplexer；When the high-speed comparator is output as low, 2 choosing
1 multiplexer selects the high level signal as the reference voltage output, and when the high-speed comparator is output as high,
Described 2 select 1 multiplexer to select the low level signal as the reference voltage output；And the high-speed comparator also passes through
The digital logic unit and clock synchronization circuit export PFM mode activated clocks to power switch driver circuit, and pass through institute
State power switch driver circuit and produce output drive signal.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating simulation PFM mode control circuits also includes that being connected to digital PFM parameters arithmetic element and described 2 selects the number between 1 multiplexer
Word turns analog converter, and the DAC is used to receive the 2N positions that the digital PFM parameters arithmetic element is provided
Number bus voltage, after the decoding process of N positions decoder forms N and selects two option codes；The N selects two option codes by electricity
The partial pressure value that pressure N selects two Unit selections to carry out partial pressure to reference data power supply using series resistance and produces, and select through ripple N
Unit one exports the high level signal respectively and the low level signal is exported as the analog reference voltage.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating digital PFM parameters arithmetic element includes N positions output ripple setting unit and N positions output voltage setting unit, both is connected to
Comparison voltage arranges ALU, and the comparison voltage arranges ALU and exports the 2N bit digitals bus electricity
Pressure, the digital PFM parameters arithmetic element is for according to output ripple and output voltage setting value, producing ratio is set compared with voltage parameter
Put bus；Wherein, the N positions output voltage setting unit is used to arrange output voltage setting value, and the N is set for output ripple
Unit is put for output voltage ripple arranges value.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating digital PWM mode control circuit includes error sample conversion unit and digital PWM loop filtering unit；The error sampling turns
Changing unit includes that reference power source resistor voltage divider network, voltage N select a unit and non-linear ADC unit, wherein, the reference voltage
Resistor voltage divider network produces 2^N voltage output, and the voltage N selects a unit for the ginseng of register configuration interface output
Examine voltage option code to be decoded, and select corresponding reference voltage output, the non-linear ADC unit is used to receive feedback electricity
Difference between pressure and the reference voltage, and non-linear simulation numeral conversion process is carried out to which, obtain the N positions of output error
Digital error signal.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
State digital PWM loop filtering unit and be mainly used in the application requirement according to loop parameter, adjustment loop parameter simultaneously passes through digital PID
Filter unit carries out digital PID filtering and loop compensation to the digital error signal, and output is to SDM noise shaping units afterwards
Noise shaping is carried out, PWM clock signals are produced by the process of digital PWM comparing unit then.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
It is basic PID loop to state digital PID filter unit, and its signal process includes being taken advantage of the N bit digital error signals of input
Method computing, accumulating operation and regressive computing, and multiplication result, accumulating operation result are added with regressive operation result and are obtained
Filtered error output；The SDM noise shaping units are second-order modulator, and which includes basic adder unit, subtraction list
Unit, multiplying unit, delay cell and K positions quantifying unit；The digital PWM comparing unit is sawed using basic K bit digitals
Tooth wave producer and K bit digital PWM comparators, wherein the K bit digitals saw-toothed wave generator produces sawtooth by accumulator
Ripple, each clock cycle export accumulated value, and the K bit digitals PWM comparator is connected to K positions quantifying unit, for connecing
Receive the K positions quantized signal that the K is quantifying unit output；If the sawtooth waveforms numerical value that the K bit digitals sawtooth waveforms is produced is less than defeated
Enter numerical value, then the digital PWM comparator output 1, on the contrary output 0.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Stating the 2nd LDO control circuits includes operational amplifier and the configurable zero pole point compensated array circuit of register, wherein the fortune
Calculation amplifier is basic amplifier, and its normal phase input end and inverting input receive reference voltage and feedback voltage respectively, and
The output end of the operational amplifier is connected to second PMOS switch to export the 2nd PMOS grid to which by first switch
Pole control signal；The zero pole point compensated array includes that M positions adjustable resistance is connected and N positions shunt capacitance, and the zero pole point of reality
Offset is controlled by voltage bus.
A kind of as the multi-mode power source managing system provided in the present invention improves, in an advantageous embodiment, institute
Operational amplifier and pole-zero compensation circuit that a LDO control circuits are multiplexed the 2nd LDO control circuits are stated, and it is described
The output end of operational amplifier is connected to the grid of first PMOS switch to export a PMOS to which by second switch
Grid control signal；Under the LDO output modes, the actual zero pole point offset of the pole-zero compensation circuit is total by voltage
Line is controlled.
Compared to prior art, the multi-mode entity management system that the application is provided can reach following technique effect：
(1) according to different application, the different mode of operation of controllable power management system, parameter register can be by system
MCU is adjusted so that IP is highly suitable for the transfer of different application occasion, saves the development time；
(2) simulate mode of operation response fast, no stability problem；Closed loop mode digital operation mode Parameter adjustable is whole,
So that IP is highly suitable for the transfer of different process, development-success ratio is improved；
(3) the LDO output modes under integrated Switching Power Supply topology, improve the efficiency under low input；
(4) the LDO output modes of circuit multiplexer, it is adaptable to the demand of low noise power supply.
【Description of the drawings】
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, embodiment will be described below used in
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, can be with other attached according to these accompanying drawings acquisitions
Figure, wherein：
A kind of structural representation of embodiment of multi-mode power source managing system that Fig. 1 is provided for the present invention；
Fig. 2 is that the multi-mode power source managing system shown in Fig. 1 is electric in simulation PFM Switching Power Supplies pattern and digital PWM switch
The output topological circuit figure of source module；
Fig. 3 is output topology electricity of the multi-mode power source managing system shown in Fig. 1 in Switching Power Supply topology LDO output modes
Lu Tu；
Fig. 4 is output topological circuit figure of the multi-mode power source managing system shown in Fig. 1 in LDO output modes；
Fig. 5 is the electrical block diagram of the simulation PFM control circuit of the multi-mode power source managing system shown in Fig. 1；
Fig. 6 is the signal waveform schematic diagram of the simulation PFM control circuit shown in Fig. 5；
Fig. 7 is that the digital PFM parameters arithmetic element and DAC numeral revolving die of the simulation PFM mode control circuits shown in Fig. 5 is intended
The electrical block diagram of converter；
Fig. 8 is the electrical block diagram of the digital PWM control circuit of the multi-mode power source managing system shown in Fig. 1；
Fig. 9 is the error sample conversion unit and digital PWM loop filtering unit of the digital PWM control circuit shown in Fig. 8
Electrical block diagram；
Figure 10 is the electrical block diagram of each internal functional elements of the digital PWM loop filtering unit shown in Fig. 9；
Figure 11 is circuit structure of the multi-mode power source managing system shown in Fig. 1 in Switching Power Supply topology LDO output modes
Schematic diagram；
Figure 12 is electrical block diagram of the multi-mode power source managing system shown in Fig. 1 in LDO output modes；
Figure 13 is that the mode of operation of the multi-mode power source managing system shown in Fig. 1 selects the circuit structure of control unit to illustrate
Figure.
【Specific embodiment】
Technical scheme in the embodiment of the present invention will be clearly and completely described below, it is clear that described enforcement
Example is only a part of embodiment of the present invention, rather than the embodiment of whole.Based on the embodiment in the present invention, this area is common
All other embodiment that technical staff is obtained under the premise of creative work is not made, belongs to the model of present invention protection
Enclose.
To solve the problems, such as prior art, the present invention provides a kind of multi-mode power source managing suitable for SOC
System.The characteristics of multi-mode power source managing system has following：
(1) using flexible Digital Circuit Control power-supply management system in simulation PFM (Pulse Frequency
Modulation, pulse frequency modulated) switch output, digital PWM (Pulse Width Modulation, pulse width modulation)
Switch output, Switching Power Supply topology LDO (Low Dropout Regulator, low pressure difference linear voltage regulator) output and pure LDO are defeated
Go out four kinds of pattern work, System Parameter Registers can configure under various patterns, so that the multi-mode power source managing system
IP be highly suitable for the transfer of different process and different application occasion；
(2) in order to avoid analogue loop stability problem, the multi-mode power source managing system is adopted in simulation mode of operation
The open loop PFM patterns controlled with comparator, energy quick response load change, and no loop stability sex chromosome mosaicism；
(3) the multi-mode power source managing system avoids analog feedback in closed loop mode using customization complete digital PWM control
Loop, therefore the error feedback amplifier and large area electric capacity of simulation can be removed, and loop parameter passes through register configuration
To adapt to different techniques；
(4) the multi-mode power source managing system adopts Digital Circuit Control in low voltage mode or low noise mode
LDO is exported, and can be reduced noise and be improved efficiency.
Fig. 1 is referred to, a kind of its structural representation of embodiment of multi-mode power source managing system provided for the present invention.Institute
State multi-mode power source managing system and illustrate which be integrated with four kind outputs as principle using step-down controller (BUCK Converter)
Pattern, respectively simulate PFM Switching Power Supply patterns, digital PWM Switching Power Supply pattern, Switching Power Supply topology LDO output modes and
LDO output modes.
Specifically, as shown in figure 1, the multi-mode power source managing system mainly includes following three parts：Digital circuit,
Analog circuit and converter power output stage.Also, to coordinate the work of the multi-mode power source managing system, the multi-mode
The external environment condition of power-supply management system can include following two parts, i.e. external component and MCU (microprocessor).Wherein,
The external component includes filter capacitor, and which is mainly used in filtering and produces voltage output；The MCU is mainly used in control system
Parameters.
Wherein, the digital circuit is connected to the microprocessor, and which mainly includes register configuration interface, mode of operation
Select unit, LDO loop control units, PFM mode parameters control unit and digital PWM loop filtering unit.The register
Configuration interface is connected to the MCU, and with the LDO loops control unit, the PFM mode parameters control unit, the number
Word PWM loop filtering units are connected.The mode of operation select unit is connected to the LDO loops control unit, the PFM
Mode parameter control unit, the digital PWM loop filtering unit, for selecting the control LDO loops control unit, described
The working condition of PFM mode parameter control units, the digital PWM loop filtering unit.
The analog circuit include voltage sample converting unit, a LDO control circuits (i.e. LDO1 control circuits), second
LDO control circuits (i.e. LDO2 control circuits), simulation PFM control circuit, digital PWM control circuit, error sample conversion unit
With feedback filtering and compensation circuit.Wherein, a LDO control circuits, the 2nd LDO control circuits, the simulation PFM
Control circuit and the digital PWM control circuit constitute an output control unit, and which can be exported to the converter power
Level provides output drive signal, drives the converter power output stage to realize the voltage output of relevant work pattern.
Specifically, the 2nd LDO control circuits and a LDO control circuits may be coupled to the digital circuit
LDO loop control units, the two is respectively used to receive the first bus voltage vset1 of the LDO loops control unit output
With the second bus voltage vset2.The PFM mode parameters control that the simulation PFM control circuit is connected to the digital circuit is single
Unit, for receiving first clock signal clk1 and the 3rd bus voltage vset3 of the PFM mode parameters control unit output.
The digital PWM control circuit is connected to the digital PWM loop filtering unit, for receiving the PWM loop filtering units
The second clock signal clk2 and the 4th bus voltage vset4 of output.
Also, the error sample conversion unit is connected between the feedback filtering and compensation circuit, and the feedback
Filtering and compensation circuit are also connected to voltage output end VOUT, the mode selecting unit and the register configuration interface.Its
In, the feedback filtering and compensation circuit can receive the 5th bus voltage vset5 from the register configuration interface, and
For the output voltage according to the voltage output end VOUT, to a LDO control circuits, the 2nd LDO control electricity
Road, the simulation PFM control circuit and the digital PWM control circuit export the first feedback voltage vfb1, and to the error
Sample conversion unit exports the second feedback voltage vfb2.The error sample conversion unit is for from digital PWM loop filter
Ripple unit receives reference voltage option code vrefset, and generates corresponding error sampling according to the second feedback voltage vfb2
Signal, and export to the digital PWM loop filtering unit.The voltage sample converting unit is connected to the digital circuit
Mode of operation is selected between control unit and the converter power output stage, and which is mainly used in receiving the mode of operation selection
6th bus voltage vset6 of control unit output, and voltage sample is carried out to the converter power output stage and will be sampled
Signal vi returns to the mode of operation and selects control unit.
The conversion power output stage adopts large scale device for power switching, and which mainly includes the first PMOS switch (PMOS
Switch 1), the second PMOS switch (PMOS switch 2) and nmos switch.Wherein, first PMOS switch, the 2nd PMOS are opened
The grid of pass and the nmos switch is connected to the output driving unit of the analog circuit, for receiving the output driving list
A PMOS grid control signal PGATE1, the 2nd PMOS grid control signals PGATE2 and NMOS gate control letter that unit provides
Number NGATE.Wherein, the source ground PGND of the nmos switch, and its drain electrode is connected to the drain electrode of first PMOS switch,
And VLX is exported as power stage, the source electrode of first PMOS switch is connected to power power-supply PVDD.Wherein, the power stage
Output VLX can also be connected to voltage output by the alternative device (such as inductance or 0 Ohmic resistance) of external component
End VOUT.The source electrode of second PMOS switch is connected to the power power-supply PVDD, and is also connected to the analog circuit
Voltage sample converting unit, and its drain electrode is connected to the voltage output end VOUT.Also, the voltage output end VOUT is also
PGND can be grounded by output capacitance.
In specific works, the conversion power output stage, can be using following configuration in different working modes：
(1) PFM Switching Power Supplies pattern and digital PWM Switching Power Supply pattern are simulated：
The electric source topology output of the simulation PFM Switching Power Supplies pattern and the digital PWM Switching Power Supply pattern can be with letter
Chemical conversion output topological circuit as shown in Figure 2, under above-mentioned mode of operation, the second PMOS switch shut-off, and the simulation
PFM control circuit and digital PWM control circuit control the driving input of the converter power output stage, i.e., by a PMOS
Grid control signal PGATE1 and NMOS gate control signal NGATE drive first PMOS switch and the nmos switch,
So that first PMOS switch and the nmos switch constitute synchronous complementary switch, as shown in Figure 2.
(2) Switching Power Supply topology LDO output modes：
The electric source topology output of the Switching Power Supply topology LDO output modes can be simplified to output as shown in Figure 3 and open up
Flutter circuit.Under this mode of operation, first PMOS switch and the nmos switch are turned off, and are opened by the 2nd PMOS
Close to constitute power output stage.Now, the driving input of the converter power output stage is come by the 2nd LDO control circuits
Produce, i.e., described 2nd LDO control circuits provide and export the 2nd PMOS grid control signals PGATE2 to control described second
PMOS switch, forms the LDO outputs of DC-DC Switching Power Supply patterns.In this operating mode, the external component can be with
Replaceable components and parts can adopt inductance, as shown in Figure 3.
(3) LDO output modes：
The electric source topology output of the LDO output modes can be simplified to output topological circuit as shown in Figure 4.In this work
Under operation mode, second PMOS switch and nmos switch shut-off, and by first PMOS switch constituting power
Output stage.Now, the driving of the converter power output stage is input into by a LDO control circuits to produce, i.e., described
First LDO control circuits are provided and export a PMOS grid control signals PGATE1 carrys out shape controlling first PMOS switch
Export into LDO.In this operating mode, the replaceable components and parts of the external component can adopt 0 Ohmic resistance, such as scheme
Shown in 4.
To more fully understand multi-mode power source managing system that the application is provided, below in conjunction with corresponding circuit diagram place of matchmakers
The various power supply output modes for stating multi-mode power source managing system are implemented.
(1) PFM Switching Power Supply patterns are simulated
The control circuit of the simulation PFM Switching Power Supply patterns mainly includes the digital control circuit and the simulation
PFM control circuit, concrete principle are as follows：
The digital control circuit configures first clock signal clk1 and described the according to input and the demand for exporting
Three control voltages vset3 (voltage bus), and one group of reference clock and two groups of reference voltages are produced, control as the simulation PFM
The input of circuit processed.
The simulation PFM control circuit can adopt pulse frequency modulated (PFM) mode, and its physical circuit can be such as Fig. 5
It is shown.The simulation PFM control circuit includes that 1 multiplexer (MUX), high-speed comparator, number are selected in DAC DACs, 2
Word logical block and clock synchronization circuit, power switch driver circuit.Wherein, the DAC DACs are connected to
Digital PFM parameters arithmetic element and described 2 is selected between 1 multiplexer, for receiving the 3rd bus voltage vset3, and is passed through
Digital-to-analogue conversion selects 1 multiplexer output high level signal High_vout or low level signal Low_vout to described 2.Institute
State 2 and 1 multiplexer is selected for optionally exporting high level signal High_vout or low level signal Low_vout, be used as
The reference voltage Ref of its output.The digital PFM parameters arithmetic element is also to the digital logic unit and clock synchronization circuit
Export the first clock signal clk1.
The core cell of the simulation PFM mode control circuits is the high-speed comparator for introducing hysteresis module, and which is mainly used
In output feedback voltage vfb and reference voltage Ref is compared, wherein the hysteresis module mainly selects 1 including digital logic unit and 2
Multiplexer, wherein the output of the high-speed comparator feeds back to described 2 by the digital logic unit and clock synchronization circuit
Select 1 multiplexer.The concrete logic of the core cell of the simulation PFM mode control circuits is as follows：When the high-speed comparator
When being output as low, described 2 select 1 multiplexer to select the high level signal High_vout to export as the reference voltage Ref；
And when the high-speed comparator is output as high, described 2 select 1 multiplexer to select the low level signal Low_vout as institute
State reference voltage Ref outputs.Also, the high-speed comparator passes through the digital logic unit and clock synchronization circuit to described
Power switch driver circuit exports PFM mode activated clock PFM_CLK, and is produced by the power switch driver circuit described
First PMOS grid control signals PGATE1 and NMOS gate control signal NGATE, are used as first PMOS switch
With the drive signal of the nmos switch.And now second PMOS switch is off state.The simulation PFM controls
The signal waveform of circuit can be as shown in Figure 6.
In simulation PFM mode control circuits, the major function of the DAC DACs unit is mapping number
Number bus voltage output vset3 of word PFM parameter arithmetic elements exports Ref to analog reference voltage.Fig. 7 is referred to, it is described
The implementation method of DAC DAC units is as follows：The DAC DACs are received from the numeral
The 2N positions vset3 buses of PFM parameters arithmetic element input, after the decoding process of N positions decoder form N and select two selections
Code；The N selects two option codes to select two Unit selections to carry out partial pressure to reference data power supply using series resistance by voltage N and produce
Raw partial pressure value, and select a unit to export high level signal High_vout and low level signal Low_vout respectively through ripple N
Export as the reference voltage.Wherein, the reference data power supply can adopt band gap reference.
As shown in fig. 7, the digital PFM parameters arithmetic element in the simulation PFM mode control circuits includes N positions output line
Ripple setting unit and N positions output voltage setting unit, both are connected to comparison voltage and arrange ALU, and the comparison
Voltage arranges ALU and exports the 2N positions vset3 buses.The specific algorithm of the digital PFM parameters arithmetic element is
According to output ripple and the arranges value of output voltage, producing ratio arranges bus compared with voltage parameter；Wherein, the digital PFM parameters
Arithmetic element can arrange output dc voltage value by the N positions output voltage setting unit, and export line by the N positions
Ripple setting unit carrys out output voltage ripple arranges value.
The voltage N of the DAC DACs selects the major function of Unit two to be used to select N positions binary code defeated
Go out and add 1 and be output as border high reference voltage High_ for the low reference voltage Low_vout1 in border, and selection N positions binary code
Vout1, wherein the low reference voltage Low_vout1 in the border and the border high reference voltage High_vout1 can be by 2^N
Individual resistant series partial pressure is obtained.The ripple N selects the major function of a unit to select N positions binary code to be output as high reference electricity
Pressure output (i.e. described high level signal High_vout), and mirror image to select N positions binary code to be output as low reference voltage defeated
Go out (i.e. described low level signal Low_vout)；Wherein, the high reference voltage output and the low reference voltage output are same
Can be obtained by 2^N resistant series partial pressure of 2 groups of mirror images.
By taking 4 BITBUS networks as an example, in the case of N=4：
(1) output voltage 1.8V, arranges 4 ' b0111 of output voltage register value；
(2) output ripple is 14mv, arranges 4 ' b0111 of output ripple register value；
(3) voltage register values are moved to left 4 by comparison voltage ALU, along with output ripple register value,
Obtain the 8 ' b01110111 of vset3 bus values of 2N positions；
(4) high 4 of vset3 bus values select Unit two through 4 decoders feeding voltage N, obtain voltage and arrange border height
Reference voltage High_vout1 is 1.815V, and the low reference voltage Low_vout1 in border is output as 1.785V；
(5) low 4 of vset3 bus values select Unit two to obtain high reference voltage output through 4 decoders feeding ripple N
High_vout is 1.807V and low reference voltage output Low_vout is 1.793V.
(2) digital PWM Switching Power Supply pattern
The control circuit of the digital PWM Switching Power Supply pattern mainly includes the digital PWM control circuit, concrete principle
It is as follows：
Fig. 8 is referred to, output voltage VO UT of voltage output end feeds back to institute through the feedback filtering and compensation circuit
Error sample conversion circuit is stated, and is data signal vod by the error sample conversion circuit conversion.Data signal vod
The duty cycle signals vset4 (i.e. above-mentioned 4th control voltage) of PWM mode and synchronization are produced through digital PWM loop filtering unit
Clock signal clk2 (i.e. above-mentioned second clock signal), and export and give digital PWM control logical block.The PWM mode is accounted for
When sky produces real PWM drivings after the logic control of the digital PWM control logical block is processed than signal vset4
Clock PWM_CLK, and a PMOS grid control signals PGATE1 and NMOS gate control are produced by power switch driver circuit
Signal NGATE1, and export to the converter power output stage to drive first PMOS switch and the nmos switch.
On the other hand, now second PMOS switch is off state.
Fig. 9 is referred to, the core cell of the digital PWM mode control circuit includes error sample conversion unit and numeral
PWM loop filtering units.The error sample conversion unit include reference power source resistor voltage divider network, voltage N select a unit and
Non-linear ADC unit.
Wherein, the reference voltage resistor voltage divider network produces 2^N voltage output, according to the setting of output voltage VO UT
Demand, the register configuration interface is by its output parameter setting unit output reference voltage option code vrefset, the electricity
Pressure N is decoded to reference voltage option code vrefset in selecting a unit, and selects corresponding reference voltage vref defeated
Go out.As an example it is assumed that half of the second feedback voltage vfb2 equal to output voltage VO UT, i.e. vfb2=VOUT/2, and
Reference data power supply is 1.5V, and vrefset is 4 voltage bus；Also, 16 altogether in the error sample conversion unit
Step is selected, and each reference voltage option code is represented as 0.1V step-lengths, then 4 ' b0111 of reference voltage option code is corresponding defeated
The reference voltage vref for going out should be Vref=0.7Vx2=1.4V.
The non-linear ADC unit is used to receive between the second feedback voltage vfb2 and the reference voltage vref
Difference, and Nonlinear A/D conversion process is carried out to which, obtains N bit digitizing signal ved (the i.e. digital error letters of output error
Number ved).Assume that the non-linear ADC unit is 4 non-linear ADCs, then its conversion is as shown in table 1：
| The margin of error (mV) | Output code | The margin of error (mV) | Output code |
| 64 | 0111 | -2 | 1111 |
| 48 | 0110 | -4 | 1110 |
| 32 | 0101 | -6 | 1101 |
| 16 | 0100 | -8 | 1100 |
| 8 | 0011 | -16 | 1011 |
| 6 | 0010 | -32 | 1010 |
| 4 | 0001 | -48 | 1001 |
| 2 | 0000 | -64 | 1000 |
Table 1
The major function of the digital PWM loop filtering unit is the application requirement according to loop parameter, adjustment loop ginseng
Counting and pass through digital PID filter unit carries out digital PID filtering and loop compensation to the digital error signal ved, defeated afterwards
Going out to Sigma-Delta modulation (SDM) noise shaping units carries out noise shaping, then by the place of digital PWM comparing unit
Reason produces PWM clock signals PWM_CLK.As shown in figure 9, the digital PID filter unit, the SDM noise shaping units and
The digital PWM comparing unit is sequentially connected；The register configuration interface includes pid parameter setting unit, SDM parameter settings
Unit and PWM parameter set units, are connected respectively to the digital PID filter unit, SDM noise shaping units and described
Digital PWM comparing unit, for corresponding pid parameter setting, SDM parameter settings and PWM parameter settings are carried out to which.
See also Figure 10, each internal element of the digital PWM loop filtering unit is implemented as follows：
Wherein, the digital PID filtering and loop compensation unit are basic PID loop, and its signal process includes will be defeated
The N bit digitizing error signal ved [N for entering:0] multiplying, accumulating operation and regressive computing are carried out, finally multiplying is tied
Really, accumulating operation result is added with regressive operation result and obtains filtered error output PID [M:0], wherein, loop filter
Wave parameter is set by the pid parameter setting unit of the register configuration interface, in the present embodiment using M=16 as tool
Style is designed.
The SDM noise shaping units are second-order modulator, and which includes basic adder unit, subtrator, multiplication fortune
Unit, delay cell and K positions quantifying unit are calculated, wherein the delay cell is the delay cell of 1 clock.The SDM noises
The signal stream of shaping unit can be refering to shown in Figure 10, and the present embodiment is set to 2, L and K with gain coefficient and is respectively set to 16 Hes
4 are designed as specific example.
The digital PWM comparing unit adopts basic K bit digitals saw-toothed wave generator and K bit digital PWM comparators, its
In, the K bit digitals saw-toothed wave generator produces sawtooth waveforms by accumulator, and each clock cycle exports accumulated value.Institute
State K bit digital PWM comparators and be connected to K positions quantifying unit, quantify for the K positions that quantifying unit is exported for receiving the K
Signal SDM [K:0]；If the sawtooth waveforms numerical value that the K bit digitals sawtooth waveforms is produced is less than input numerical value, the digital PWM ratio
Compared with device output 1, otherwise export 0.As described above, the present embodiment is designed using K=4 as specific example.
(3) Switching Power Supply topology LDO output modes：
When input voltage is close to output voltage, the efficiency of Switching Power Supply will occur to decline, therefore for raising efficiency,
With closing switch electric source modes, and the 2nd LDO controls can be opened in the multi-mode power source managing system that the application is provided
Circuit, now first PMOS switch and the nmos switch be off state, and the 2nd LDO control circuits can
To drive second PMOS switch to be operated by the 2nd PMOS grid control signals.
The circuit that implements of the Switching Power Supply topology LDO output modes can be as shown in figure 11, specifically, described
2nd LDO control circuits include operational amplifier and the configurable zero pole point compensated array circuit of register, wherein, the computing
Amplifier is basic amplifier, and its normal phase input end and inverting input can receive reference voltage Vref and the first feedback respectively
Voltage vfb1, also, the output end of the operational amplifier can be connected to described second by first switch (switching 1)
The grid of PMOS switch, for exporting the 2nd PMOS grid control signal PGATE2 to second PMOS switch.
In a particular embodiment, the 2nd LDO control circuits can be tied using basic cascode one-levels operational amplifier
Structure, its zero pole point compensation can be realized by the zero pole point compensated array circuit.Such as, the zero pole point compensated array can
To connect and N positions shunt capacitance including M positions adjustable resistance, and the zero pole point offset of reality is by voltage bus Vset [K:1] enter
Row control, to adapt to the stability under the conditions of different application.Embodiment shown in Figure 11 is set using K=8 as specific example
Meter, wherein high 4 are used for resistance selection, and low 4 are used for capacitance selection.
(4) LDO output modes：
It is when its power-supply management system of application requirement of SOC is using low noise power supply, for improving performance, described many
Mode power management system with closing switch electric source modes, and can open a LDO control circuits.Now, described second
PMOS switch and the nmos switch are off state, and the alternative device could be arranged to Zero-ohm resistor, separately
Outward, a LDO control circuits can drive first PMOS switch to carry out by a PMOS grid control signals
Work.
The circuit that implements of the LDO output modes of the multi-mode power source managing system can be as shown in figure 12.Specifically
For, after the LDO output modes of the multi-mode power source managing system are enabled, a LDO control circuits can be answered
With the operational amplifier and pole-zero compensation circuit of the 2nd LDO control circuits, also, the output end of the operational amplifier
The grid of first PMOS switch is connected to by second switch (switching 2), for exporting to first PMOS switch
The first PMOS grid control signal PGATE1.In addition, under the LDO output modes, the pole-zero compensation circuit
Actual zero pole point offset is controlled by voltage bus vset1, to adapt to the stability under the conditions of different application.
Finally, the switching of four kinds of power supply output modes of the multi-mode power source managing system, i.e., described simulation PFM switches
Power supply output mode, the digital PWM Switching Power Supply output mode, Switching Power Supply topology LDO output modes and the LDO
Output mode can select control unit by the mode of operation of the digital circuit and coordinate the voltage of the analog circuit to adopt
Sample converting unit is realizing.Specifically, the circuit that implements of the output mode switching of the multi-mode power source managing system can
With as shown in figure 13.
Wherein, the voltage sample converting unit includes gradually-appoximant analog-digital converter (SAR ADC), the SAR ADC
Can be basic K positions successive approximation analog to digital C, which is used to realize the detection to input voltage PVDD, is made with K=4 in the present embodiment
It is designed for specific example.The SAR ADC may be coupled to the input voltage ratio that the mode of operation selects control unit
Compared with unit, its Approach by inchmeal code SAR CODE that can be provided according to the input voltage comparing unit, by the input voltage
PVDD is converted to numeral input voltage VI [K:1], and export to the input voltage comparing unit.The input voltage is more single
Unit is for by the numeral input voltage VI [K:1] the output voltage VO UT arranges value provided with the register configuration interface is entered
Row compares.
As shown in figure 13, the mode of operation selects control unit include Switching Power Supply topology control unit, open
Close the LDO control units under electric source topology, LDO pattern configurations units, simulate PFM pattern configurations units, digital PWM pattern configurations
LDO dispensing units under unit and Switching Power Supply topology.Wherein, the Switching Power Supply topology control unit is connected to the deposit
Device configures the lower LDO control units of interface and Switching Power Supply topology, and the topological control unit of the Switching Power Supply and described
LDO control units under Switching Power Supply topology are all connected to the output end of the input voltage comparing unit.The LDO patterns are matched somebody with somebody
Put under unit, the simulation PFM pattern configurations units, the digital PWM pattern configurations unit and Switching Power Supply topology
LDO dispensing units are respectively used to realize that LDO loops control is enabled, the control of PFM mode parameters is enabled, the filter of digital PWM loop
Ripple is enabled and the control of the 2nd LDO loops is enabled.Wherein, the LDO pattern configurations unit is directly connected to the register configuration
Interface, the simulation PFM pattern configurations unit and the digital PWM pattern configurations unit are connected to the Switching Power Supply topology control
The LDO controls that LDO dispensing units under unit processed, and Switching Power Supply topology are connected under the Switching Power Supply topology are single
Unit.
Based on foregoing circuit structure, it is described many that the mode of operation selects control unit be accomplished by
The output mode switching of mode power management system.
(1) if it is LDO output modes that the register configuration interface arranges multi-mode power source managing system application,
The LDO pattern configurations unit will realize that LDO loops control is enabled, now the multi-mode power source managing system
Other control models are turned off, then the multi-mode power source managing system will enable LDO loops application setting.
(2) if it is Switching Power Supply mould that the register configuration interface arranges multi-mode power source managing system application
Formula, and by voltage ratio, the input voltage comparing unit relatively judges that the input voltage is set less than the output voltage
Value, then the LDO control units under the Switching Power Supply is topological can control the LDO dispensing units under the Switching Power Supply topology, with
The LDO dispensing units under the Switching Power Supply topology are made to realize that the control of the 2nd LDO loops is enabled, now the multi-mode electrically source capsule
Other control models of reason system are turned off.Therefore, the multi-mode power source managing system will start the 2nd LDO loop applications
Arrange.In the present embodiment, the output voltage setting value specifically can add 200mV to be set as an example using output voltage
Meter.
(3) if it is Switching Power Supply mould that the register configuration interface arranges multi-mode power source managing system application
Formula, and by voltage ratio, the input voltage comparing unit relatively judges that the input voltage is set less than the output voltage
It is worth, now the multi-mode power source managing system default is initialized into simulating PFM Switching Power Supply output modes.As described above,
In the present embodiment, the output voltage setting value specifically can add 200mV to be designed as an example using output voltage.
(4) if it is Switching Power Supply pattern that the register configuration interface arranges multi-mode power source managing system application
Simulation PFM Switching Power Supply output modes, now the multi-mode power source managing system will be in simulation PFM Switching Power Supplies output
Pattern, the simulation PFM pattern configurations unit can realize that simulating the control of PFM loops enables, the multi-mode power source managing system
Other control models of system are turned off.Therefore, the multi-mode power source managing system will start the PFM mode switch electric source topology
Using setting.
(5) if it is Switching Power Supply pattern that the register configuration interface arranges multi-mode power source managing system application
Digital PWM Switching Power Supply output mode, the multi-mode power source managing system will be exported in the digital PWM Switching Power Supply
Pattern.The digital PWM pattern configurations unit can realize that the control of digital PWM loop is enabled, the multi-mode power source managing system
Other control models of system are turned off.Therefore, the multi-mode power source managing system will start digital PWM mode switch electric source topology
Using setting.
Based on above-mentioned concrete technical scheme, compared to prior art, the multi-mode entity management system that the application is provided can
To reach following technique effect：
(1) according to different application, the different mode of operation of controllable power management system, parameter register can be by system
MCU is adjusted so that IP is highly suitable for the transfer of different application occasion, saves the development time；
(2) simulate mode of operation response fast, no stability problem；Closed loop mode digital operation mode Parameter adjustable is whole,
So that IP is highly suitable for the transfer of different process, development-success ratio is improved；
(3) the LDO output modes under integrated Switching Power Supply topology, improve the efficiency under low input；
(4) the LDO output modes of circuit multiplexer, it is adaptable to the demand of low noise power supply.
Above-described is only embodiments of the present invention, it should be noted here that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
Enclose.
Claims (16)
1. a kind of multi-mode power source managing system, it is characterised in that including digital circuit, analog circuit and converter output stage,
Wherein described analog circuit is connected to the digital circuit, and it include simulating PFM control circuit, digital PWM control circuit, the
One LDO control circuits and the 2nd LDO control circuits；The simulation PFM control circuit, digital PWM control circuit, LDO controls
Circuit processed and the 2nd LDO control circuits constitute output driving unit, drive for providing output to the converter power output stage
Dynamic signal, the output drive signal are used to drive the converter power output stage to realize that simulation PFM Switching Power Supplies are defeated respectively
The voltage of exit pattern, digital PWM Switching Power Supply output mode, Switching Power Supply topology LDO output modes and LDO output modes is defeated
Go out.
2. multi-mode power source managing system according to claim 1, it is characterised in that the converter power output stage bag
Include the first PMOS switch, the second PMOS switch and nmos switch, wherein, first PMOS switch, the second PMOS switch and
Nmos switch is connected to the output driving unit, for receiving the output drive signal that the output driving unit is provided；Its
Described in nmos switch source ground, and its drain electrode is connected to the drain electrode of first PMOS switch, and defeated as power stage
Go out；The source electrode of first PMOS switch and second PMOS switch is connected to power power-supply；Second PMOS switch
Drain electrode is connected to voltage output end, and power stage output is connected to the voltage output end, and institute by alternative device
State voltage output end to be grounded by output capacitance.
3. multi-mode power source managing system according to claim 2, it is characterised in that the output drive signal includes using
In drive first PMOS switch a PMOS grid control signals, for drive second PMOS switch second
PMOS grid control signals and the NMOS gate control signal for driving the nmos switch.
4. multi-mode power source managing system according to claim 3, it is characterised in that in the simulation PFM Switching Power Supplies
Under output mode and the digital PWM Switching Power Supply output mode, second PMOS switch is off state, and the mould
Intend PFM control circuit and the digital PWM control circuit passes through a PMOS grid control signals and NMOS gate control signal
First PMOS switch and the nmos switch are driven so which constitutes synchronous complementary switch.
5. multi-mode power source managing system according to claim 3, it is characterised in that in Switching Power Supply topology LDO
Under output mode, first PMOS switch and the nmos switch are off state；The 2nd LDO control circuit outputs
The 2nd PMOS grids control letter is exported come the LDO for driving second PMOS switch to form Switching Power Supply pattern, wherein, institute
State replaceable components and adopt inductance element.
6. multi-mode power source managing system according to claim 3, it is characterised in that under the LDO output modes, institute
State the second PMOS switch and the nmos switch is off state；A PMOS described in the first LDO control circuit outputs
Grid controls letter to drive first PMOS switch to form LDO outputs, wherein, the replaceable components is electric using zero ohm
Resistance.
7. multi-mode power source managing system according to claim 1, it is characterised in that the digital circuit includes LDO rings
Road control unit, PFM mode parameters control unit and digital PWM loop filtering unit, wherein the LDO loops control unit connects
A LDO control circuits and the 2nd LDO control circuits are connected to, for LDO control circuits and described
2nd the first bus voltage of LDO control circuit outputs and the second bus voltage, the PFM mode parameters control unit are connected to institute
Simulation PFM control circuit is stated, for the 3rd bus voltage and the first clock signal being exported to the simulation PFM control circuit；Institute
State digital PWM loop filtering unit and be connected to the digital PWM control circuit, for exporting to the digital PWM control circuit
4th bus voltage and second clock signal.
8. multi-mode power source managing system according to claim 7, it is characterised in that the digital circuit also includes work
Mode selecting unit, which is connected to the LDO loops control unit, the PFM mode parameters control unit and the digital PWM
Loop filtering unit, for the output configuration according to register configuration interface and input voltage sampled value, is optionally carried out
The control of first LDO loops is enabled, the control of the 2nd LDO loops is enabled, simulation PFM loop controls are enabled and the control of digital PWM loop
Enable.
9. multi-mode power source managing system according to claim 1, it is characterised in that the simulation PFM Schema controls electricity
Road includes the high-speed comparator for introducing hysteresis module, and which is used to compare output feedback voltage and reference voltage, wherein the sluggishness
Module includes digital logic unit and 2 selects 1 multiplexer, wherein the output of the high-speed comparator passes through the digital logic unit
Feed back to described 2 and select 1 multiplexer；When the high-speed comparator is output as low, described 2 select 1 multiplexer to select the high electricity
Ordinary mail number is used as the reference voltage output, and when the high-speed comparator is output as high, described 2 select 1 multiplexer to select
The low level signal is used as the reference voltage output；And the high-speed comparator also pass through the digital logic unit and
Clock synchronization circuit exports PFM mode activated clocks to power switch driver circuit, and passes through the power switch driver circuit
Produce output drive signal.
10. multi-mode power source managing system according to claim 9, it is characterised in that the simulation PFM Schema controls electricity
Road also includes that being connected to digital PFM parameters arithmetic element and described 2 selects DAC between 1 multiplexer, described
DAC is used to receive the 2N bit digital bus voltages that the digital PFM parameters arithmetic element is provided, through N positions
N is formed after the decoding process of decoder and selects two option codes；The N selects two option codes to select two Unit selections to adopt by voltage N
The partial pressure value that series resistance carries out partial pressure to reference data power supply and produces, and it is described to select a unit to export respectively through ripple N
High level signal and the low level signal are exported as the analog reference voltage.
11. multi-mode power source managing systems according to claim 10, it is characterised in that the digital PFM parameters computing
Unit includes N positions output ripple setting unit and N positions output voltage setting unit, both is connected to comparison voltage and arranges logic fortune
Unit is calculated, and the comparison voltage arranges ALU and exports the 2N bit digitals bus voltage, the digital PFM parameters
Arithmetic element is for according to output ripple and output voltage setting value, producing ratio arranges bus compared with voltage parameter；Wherein, the N
Position output voltage setting unit is used to export electricity for output ripple setting unit for arranging output voltage setting value, and the N
Embossing ripple arranges value.
12. multi-mode power source managing systems according to claim 1, it is characterised in that the digital PWM Schema control electricity
Road includes error sample conversion unit and digital PWM loop filtering unit；The error sample conversion unit includes reference power source
Resistor voltage divider network, voltage N select a unit and non-linear ADC unit, wherein, the reference voltage resistor voltage divider network produces 2^
N number of voltage output, the reference voltage option code that the voltage N selects a unit and exports for register configuration interface are solved
Code, and selects corresponding reference voltage output, the non-linear ADC unit be used to receiving feedback voltage and the reference voltage it
Between difference, and which is carried out non-linear simulation numeral conversion process, obtain the N bit digital error signals of output error.
13. multi-mode power source managing systems according to claim 12, it is characterised in that the digital PWM loop filtering
Unit is mainly used in the application requirement according to loop parameter, and adjustment loop parameter simultaneously passes through digital PID filter unit to the number
Word error signal carries out digital PID filtering and loop compensation, and output afterwards carries out noise shaping to SDM noise shaping units, so
PWM clock signals are produced by the process of digital PWM comparing unit afterwards.
14. multi-mode power source managing systems according to claim 13, it is characterised in that the digital PID filter unit
For basic PID loop, its signal process include by the N bit digitals error signal of input carry out multiplying, accumulating operation and
Regressive computing, and multiplication result, accumulating operation result and regressive operation result are added obtain the output of filtered error；
The SDM noise shaping units are second-order modulator, and which includes basic adder unit, subtrator, multiplying unit, prolongs
Slow unit and K positions quantifying unit；The digital PWM comparing unit adopts basic K bit digitals saw-toothed wave generator and K bit digitals
PWM comparators, wherein the K bit digitals saw-toothed wave generator produces sawtooth waveforms by accumulator, each clock cycle is defeated
Go out accumulated value, the K bit digitals PWM comparator is connected to K positions quantifying unit, be that quantifying unit is defeated for receiving the K
The K positions quantized signal for going out；If the sawtooth waveforms numerical value that the K bit digitals sawtooth waveforms is produced is less than input numerical value, the digital PWM
Comparator output 1, otherwise output 0.
15. multi-mode power source managing systems according to claim 2, it is characterised in that the 2nd LDO control circuit bags
Operational amplifier and the configurable zero pole point compensated array circuit of register are included, wherein the operational amplifier is basic amplification
Device, its normal phase input end and inverting input receive reference voltage and feedback voltage respectively, and the operational amplifier is defeated
Go out end to be connected to second PMOS switch to export the 2nd PMOS grid control signals to which by first switch；Zero pole
Point compensated array includes the adjustable resistance series connection of M positions and N positions shunt capacitance, and the zero pole point offset of reality is carried out by voltage bus
Control.
16. multi-mode power source managing systems according to claim 15, it is characterised in that a LDO control circuits
It is multiplexed the operational amplifier and pole-zero compensation circuit of the 2nd LDO control circuits, and the output of the operational amplifier
Holding, the grid of first PMOS switch is connected to a PMOS grid control signals are exported to which by second switch；Institute
State under LDO output modes, the actual zero pole point offset of the pole-zero compensation circuit is controlled by voltage bus.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1367583A (en) * | 2001-01-20 | 2002-09-04 | 盛群半导体股份有限公司 | Resistor string D/A converter with pulse width modulation output |
| CN1797952A (en) * | 2004-12-29 | 2006-07-05 | 旺玖科技股份有限公司 | System and method of ultra sampling high speed time pulse / data recovery |
| CN101136591A (en) * | 2006-09-01 | 2008-03-05 | 株式会社理光 | Power supply device and operations control method thereof |
| CN101540542A (en) * | 2009-03-18 | 2009-09-23 | 浙江大学 | Single-inductor switch direct current voltage converter and 4-mode control method |
| CN101847028A (en) * | 2010-04-14 | 2010-09-29 | 广州市广晟微电子有限公司 | Dynamic compensation circuit with ultra-low power consumption and linear regulator with the same |
| CN102065254A (en) * | 2009-11-17 | 2011-05-18 | 无锡华润矽科微电子有限公司 | Multichannel signal acquisition and conversion method and circuit |
| CN102969697A (en) * | 2011-09-02 | 2013-03-13 | 通嘉科技股份有限公司 | Control method for overvoltage protection and control circuit used for power supply controller |
| CN103026604A (en) * | 2010-03-12 | 2013-04-03 | 密克罗奇普技术公司 | Digital device with boot strap circuit stimulator |
| CN103107562A (en) * | 2011-11-09 | 2013-05-15 | 珠海全志科技股份有限公司 | Switch charging circuit and power management system |
| CN103430439A (en) * | 2010-08-30 | 2013-12-04 | 德州仪器公司 | Dc-dc converter |
| CN103929060A (en) * | 2014-04-17 | 2014-07-16 | 卓荣集成电路科技有限公司 | Step-down conversion circuit |
| US20160172974A1 (en) * | 2014-12-15 | 2016-06-16 | Kabushiki Kaisha Toshiba | Power supply circuit and control method thereof |
| US20160190923A1 (en) * | 2014-12-31 | 2016-06-30 | Texas Instruments Incorporated | Fast mode transitions in a power converter |
-
2016
- 2016-12-21 CN CN201611192092.3A patent/CN106549578B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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