CN102065254A - Multichannel signal acquisition and conversion method and circuit - Google Patents
Multichannel signal acquisition and conversion method and circuit Download PDFInfo
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- CN102065254A CN102065254A CN2009101988489A CN200910198848A CN102065254A CN 102065254 A CN102065254 A CN 102065254A CN 2009101988489 A CN2009101988489 A CN 2009101988489A CN 200910198848 A CN200910198848 A CN 200910198848A CN 102065254 A CN102065254 A CN 102065254A
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Abstract
The invention provides a multichannel signal acquisition and conversion method, which comprises the following steps of: a) selecting a path of analog signals from multiple channels by adopting a multichannel selection time division multiplexing time sequence signal; b) converting the analog signals into digital signals; and c) latching and outputting the digital signals. The invention also provides a multichannel signal acquisition and conversion circuit, which comprises a channel selection module, an analog to digital converter (ADC) module, an output latch module and a time sequence control module. Various signals in a television system are acquired and detected in a single-ADC multichannel circular acquisition mode, the application amount of the ADC module is saved, an input circuit structure is greatly simplified, and the number of input/output (IO) ports is reduced. The whole multichannel ADC circuit is simple in structure and high in efficiency, the multichannel signal conversion is implemented by one ADC module, and an economic and flexible choice is provided in the application of the television system.
Description
Technical field
The invention belongs to television set ADC signal acquisition circuit field, be specifically related to a kind of multi-channel signal acquiring conversion method and circuit.
Background technology
Need in the system for TV set to gather and detect multiple signal, as push button signalling, battery electric quantity signal, machine cavity temperature signal, ambient brightness signal etc.Aspect the push button signalling input, form the mode of keyboard matrix supplied with digital signal by a plurality of button IO of direct usefulness, also have by the electric resistance partial pressure mode, the road low speed ADC input port that utilizes CPU to provide is simulated the mode of a plurality of button IO inputs; Aspect the input of battery electric quantity signal, the overwhelming majority adopts the ADC transducer of different accuracy to realize signals collecting; Aspect machine cavity temperature signal, the input of ambient brightness signal, general method is earlier with corresponding sensor sensing machine cavity temperature signal or ambient brightness signal, to realize the collection of signal more respectively with different ADC modules.
When needing integrated above-mentioned multinomial function in the television system, have to adopt a plurality of ADC transformational structures and a plurality of IO mouth to finish the collection and the detection of signal.It is big so just to be faced with the resource requirement of an IO mouth, the baroque problem of input circuit.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of can simplify circuit structure, the used IO mouth quantity of reduction, realize the automatic collection of the multiple signal of a plurality of passages and the multi-channel signal acquiring change-over circuit of conversion; And provide the automatic collection of the multiple signal of a kind of corresponding a plurality of passages and the method for conversion.
For solving the problems of the technologies described above, the invention provides a kind of multi-channel signal acquiring conversion method, comprising: a) the time-multiplexed clock signal that adopts multichannel to select is selected one tunnel analog signal from described multichannel; B) described analog signal conversion is become digital signal; C) described digital signal is latched and exports.
Optionally, adopt the analog switch of a multiselect one, the time-multiplexed clock signal that described multichannel is selected is controlled the analog switch of described multiselect one and select one tunnel analog signal from described multichannel.
Optionally, when the time-multiplexed clock signal that described multichannel is selected was effective, corresponding passage was opened; When the time-multiplexed clock signal that described multichannel is selected is invalid, corresponding pathway closure.
Optionally, adopt data output synchronizing signal when signal is exported in the step c), allow data to be read by late-class circuit.
Optionally, adopt the passage enable signal from described a plurality of passages, need to select the passage of acquired signal before the step a).Wherein, when the time-multiplexed clock signal while that the passage enable signal and the multichannel of a certain passage correspondence in the described multichannel are selected was effective, this passage was opened; Otherwise this pathway closure.
Optionally, can adopt the ADC module that described analog signal conversion is become digital signal in the step b).Described ADC module can be the adc circuit that approaches one by one.
The present invention also provides a kind of multi-channel signal acquiring change-over circuit, comprising: channel selecting module, from a plurality of passages, select one tunnel analog signal; The ADC module becomes digital signal with described analog signal conversion; The output latch module latchs and exports described digital signal; Time-sequence control module produces required clock signal and the control signal of circuit working.
Optionally, the clock signal of described time-sequence control module generation comprises time division multiplexing clock signal that the open/close multichannel of the described passage of control is selected and the gap marker signal of distinguishing different passages with control signal.Wherein, the pass of the number N of the figure place n of described gap marker signal and described passage is: n=log
2N.
Optionally, described multi-channel signal acquiring change-over circuit also comprises the passage enable module, produces the passage enable signal need to select acquired signal from described a plurality of passages passage.The time division multiplexing clock signal that described multichannel is selected is controlled the ON/OFF of described selecteed passage.
Optionally, clock signal that described time-sequence control module produces and control signal also comprise data output synchronizing signal, allow data to be read by late-class circuit.
Optionally, the reset signal that clock signal that described time-sequence control module produces and control signal also comprise the ADC module quits work when making the ADC module not receive described analog signal.
Optionally, the analog switch of described channel selecting module employing multiselect one.The NAND gate of passing through of the analog switch of described multiselect one is controlled by described time-sequence control module.
Optionally, the adc circuit of described ADC module for approaching one by one.
Optionally, described ADC module produces passage EOC signal and gives time-sequence control module, makes time-sequence control module produce the timing control signal of next passage change-over period.
The invention provides a kind of multi-channel signal acquiring conversion method and circuit, mode by single ADC multichannel circle collection realizes multiple signal automatic acquisition in the system for TV set, saved the use amount of ADC module, simplify the input circuit structure greatly, reduced used IO mouth quantity simultaneously.Whole multichannel adc circuit is simple in structure, and the efficient height is realized the multi channel signals conversion with an ADC, is economy during system for TV set is used, and selects flexibly.
Description of drawings
Fig. 1 is the circuit structure block diagram of embodiments of the invention one;
Fig. 2 is the circuit structure block diagram of embodiments of the invention two;
Fig. 3 is the circuit structure block diagram of embodiments of the invention three;
Fig. 4 is the structural representation of a kind of channel selecting module of the present invention;
Fig. 5 is the workflow diagram of embodiments of the invention one correspondence;
Fig. 6 is the working timing figure of embodiments of the invention one correspondence;
Fig. 7 is the workflow diagram of embodiments of the invention two correspondences;
Fig. 8 is the working timing figure of embodiments of the invention two correspondences;
Fig. 9 is the workflow diagram of embodiments of the invention three correspondences;
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the specific embodiment of the present invention is described in further detail below in conjunction with accompanying drawing.
With reference to Fig. 1, Fig. 1 is the circuit structure block diagram of embodiments of the invention one.As shown in Figure 1, multi-channel signal acquiring change-over circuit of the present invention comprises following module: multichannel is selected module, ADC module, time-sequence control module and output latch module, and wherein port number is N, and N is the natural number greater than 1.
Multichannel is selected module can select input signal (being analog signal) in the paths to send to the ADC module from N paths A1-AN to handle.In the present embodiment, adopt N to select one analog switch to select module as multichannel.Each channel transfer one road signal, this signal be the analog signal in the system for TV set that obtains of sensor acquisition normally, for example push button signalling, battery electric quantity signal, machine cavity temperature signal, ambient brightness signal etc.Multichannel selects module one paths can only be opened at synchronization, and rest channels is closed, and the signal in the passage of opening sent in the ADC module handles.
The ADC module will become digital signal from the analog signal conversion that multichannel selects module to send over; Though the ADC module can only be changed a kind of analog signal of selecting module to send over from multichannel at synchronization, select module to select different signals by multichannel, the ADC module can realize changing multiple different signal by time-multiplexed mode.The shared ADC module of multiple like this conversion of signals has been simplified circuit structure, has saved cost.Consider conversion accuracy and frequency needs in the system for TV set, this module can be realized by an adc circuit that approaches one by one.
The output latch module latchs and exports the digital signal by the ADC resume module, reads for late-class circuit (as CPU) when synchronizing signal DR is effective up to data, if data are not read, then is updated behind next passage EOC.
Time-sequence control module produces required clock signal and the control signal of circuit working, comprising: the time division multiplexing clock signal SLOT[1:N of N channel selecting] and gap marker signal CH_SIGN[n:1] etc.The time division multiplexing clock signal SLOT[1:N of N channel selecting] and each passage A1-AN corresponding one by one, control the ON/OFF of each passage A1-AN, make and have only a passage to open and transmission signals at most at synchronization.Gap marker signal CH_SIGN[n:1], identify and distinguish different passages.As a certain passage A[i] when opening, corresponding gap marker signal is effective, expression AD this moment conversion be passage A[i] analog signal.The pass of the figure place n of gap marker signal and port number N is: n=log2N.
The required clock signal of ADC module work can be produced by system, also can be produced by time-sequence control module, and present embodiment is preferably produced the clock signal of ADC module by time-sequence control module.
Time-sequence control module produces the required clock signal of circuit working and control signal can also comprise data output synchronizing signal DR, and whether the sign output signal is effective, allows data to be read by late-class circuit.When data output synchronizing signal DR was effective, the data of output latch module output were effective, read for late-class circuit (as CPU).
Fig. 2 is the circuit structure block diagram of embodiments of the invention two.As shown in Figure 2, on the basis of circuit structure shown in Figure 1, increased a passage enable module, produced passage enable signal CH_EN[1:N], selection needs the passage of acquired signal from N passage A1-AN.Passage enable signal CH_EN[1:N] be and N passage A1-AN enable signal one to one.Gather the signal of certain passage when needs, then the enable signal of correspondence is provided with effectively.If the enable signal of certain passage is set to forbid, then do not gather the signal of this passage, do not produce the data output efficient synchronization signal DR of this passage simultaneously yet.By passage enable signal CH_EN[1:N] can in a plurality of passage A1-AN, choose the passage that one or several needs acquired signal, other are not by passage enable signal CH_EN[1:N] pathway closure chosen.As certain passage A[m] not by its corresponding passage enable signal CH_EN[m] enable this pathway closure so.Even this moment its corresponding channel selecting time division multiplexing clock signal SLOT[m] effectively, still do not have analog signal and be sent to the ADC module.In a certain moment, when the channel selecting time division multiplexing clock signal of the passage enable signal of a certain passage correspondence and correspondence was effective simultaneously, the signal of this passage could be gathered.So both can be selective the signal of some passage of needing of collection, then close for the passage that does not need acquired signal, saved energy consumption; Can realize multichannel automatic collection by time-multiplexed mode again, simplify circuit structure.
Fig. 3 is the circuit structure block diagram of embodiments of the invention three.As shown in Figure 3, on the basis of circuit structure shown in Figure 2, the reset signal that clock signal that time-sequence control module generation circuit working is required and control signal can also comprise the ADC module, make the ADC module not receive input signal (being analog signal) time and quit work, finish effective period up to passage.
Fig. 4 is the structure chart of a kind of channel selecting module of the present invention.Wherein, A1, A2...AN are N passage, the corresponding analog signal of each channel transfer; As can be seen from Figure 4, present embodiment adopts the analog switch of multiselect one as channel selecting module, and is controlled by time-sequence control module by NAND gate.Opening or closing of the switch of each passage correspondence by passage enable signal CH_EN[1:N] and clock signal SLOT[1:N] common control.If will gather any several channel signal, the CH_EN[i of these passages during circuit working then] can remain effectively always.Because SLOT[1:N] be a time-multiplexed clock signal, so any one has only the switch of a passage to open constantly, can not cause the interference of each interchannel data.
Do not adopt the corresponding workflow of multi-channel signal acquiring change-over circuit (embodiment one) of passage enable signal below in conjunction with Fig. 5 explanation:
1. after the multi-channel signal acquiring change-over circuit was started working, time-sequence control module produced the time-multiplexed clock signal SLOT[1:N of N passage];
2. at certain passage in effective time (SLOT[i] be high level), then the analog switch of respective channel is opened in the channel selecting module, and this channel signal is sent to the AD module processing;
3.AD modular converter becomes digital signal to analog signal conversion;
4. digital signal is delivered to the output latch module and is latched;
5. time-sequence control module produces the output synchronizing signal, allows data to be read by late-class circuit;
6. the effective clock signal of passage finishes SLOT[i] become low level, time-sequence control module produces the clock signal of next passage, and the change-over period of a passage finishes.
The sequential chart of flow process correspondence shown in Figure 5 as shown in Figure 6.Produce the time-multiplexed clock signal SLOT[1:N of N passage by time-sequence control module], when the clock signal of certain passage correspondence was high level, circuit was changed the signal of this passage; In any one moment, having only a SLOT signal is high level.In the channel signal transition period, time-sequence control module produces gap marker signal CH_SIGN[n:1], be used to distinguish the passage of conversion; After this channel signal was changed through AD, data were output latch module and latch, and time-sequence control module produces output synchronizing signal DR, and DR is the pulse signal of a high level.At the trailing edge of DR signal, late-class circuit reading of data and gap marker signal.
In order to optimize service behaviour of the present invention, in circuit, add produce passage enable signal CH_EN[1:N] the passage enable module, so just can choose as required and want to gather the also passage of translation data.The workflow of its corresponding multi-channel signal acquiring change-over circuit (embodiment two) as shown in Figure 7.Between above-mentioned step 1 and step 2, can increase channel selecting enable signal CH_EN[i] judgement (step 7).If the respective channel enable signal is (CH_EN[i] be high level) effectively, then the analog switch of respective channel is opened in the channel selecting module, and this channel signal is sent to the AD module processing; If respective channel is selected enable signal CH_EN[i] be invalid, then the analog switch of respective channel turn-offs, thereby reduces the power consumption of circuit.Simultaneously, if channel selecting enable signal CH_EN[i] be invalid, time-sequence control module does not produce effective output synchronizing signal DR at this passage in the change-over period, avoid the data of late-class circuit read error.
The sequential chart of flow process correspondence shown in Figure 7 as shown in Figure 8.Passage enable signal CH_EN[1:N] effective during high level, the expression respective channel has signal demand collection conversion.In Fig. 8, CH_EN[2] be low level, the invalidating signal of passage 2, other channel signals are gathered; Produce the effective clock signal SLOT[1:N of N passage by time-sequence control module], high level is effective; Time-sequence control module produces gap marker signal CH_SIGN[n:1 according to the passage useful signal]; After change-over period, time-sequence control module produces an effectively output synchronizing signal DR, at trailing edge CPU reading of data and the channel information of this efficient synchronization signal DR through 1 passage.In Fig. 8, because the signal of passage 2 is not gathered, so there is not corresponding effective DR signal to produce, dateout keeps the data of passage 1.
As a kind of further optimization execution mode, in circuit, add the reset signal of ADC module.The reset signal time-sequence control module of this ADC module produces in the present embodiment.The workflow of its corresponding multi-channel signal acquiring change-over circuit (embodiment three) as shown in Figure 9.Be exactly for above-mentioned steps 7, as respective channel enable signal CH_EN[i] be invalid, then the analog switch of respective channel turn-offs.Simultaneously time-sequence control module produces the reset signal of AD modular converter, when passage does not need to change, the AD modular converter is quit work, and finishes effective period up to passage, thereby further reduces the power consumption of circuit.
As preferred embodiment, ADC module among embodiment one, embodiment two and the embodiment three can also produce passage EOC signal and give time-sequence control module, make time-sequence control module produce the timing control signal of next passage change-over period, to improve the accuracy of conversion of signals.Corresponding workflow makes time-sequence control module produce the timing control signal of next passage change-over period for being exactly to deliver in above-mentioned steps 4 digital signals to produce this passage EOC signal when the output latch module latchs to time-sequence control module.
Multi-channel signal acquiring conversion method provided by the invention, its key step comprises:
A) from multichannel, select one tunnel analog signal;
B) selecteed analog signal conversion in the step a) is become digital signal;
C) digital signal that obtains in the step b) is latched and exports;
Wherein, the time-multiplexed clock signal SLOT[1:N that adopts multichannel to select in the step a)] selection one tunnel analog signal from described multichannel.
In the step a), N passage arranged, be respectively A1-AN.The time-multiplexed clock signal SLOT[1:N that the multichannel that is adopted is selected] corresponding one by one with each passage A1-AN.The time-multiplexed clock signal SLOT[1:N that selects by multichannel] control the ON/OFF of each passage A1-AN, make and have only a passage to open and transmission signals at most at synchronization.As a kind of optimal way, can adopt the multichannel among Fig. 1 to select module.Time-multiplexed clock signal SLOT[1:N with the multichannel selection] control the channel switch that this multichannel is selected module, thus realize from N passage, selecting one tunnel analog signal.Further, can adopt the analog switch of multiselect shown in Figure 4 as channel selecting module.
In the step b), can adopt ADC module shown in Figure 1 to become digital signal from the analog signal conversion that multichannel selects module to send over.Can realize by an adc circuit that approaches one by one as this ADC module of a kind of optimal way.
In the step c), latching and exporting of digital signal can adopt output latch module shown in Figure 1 to realize.During output, can adopt the passage of the digital signal correspondence that gap marker signaling zone branch will export.Simultaneously, can also adopt data output synchronizing signal DR.The output latch module latchs and exports the digital signal by the ADC resume module, allows data to be read by late-class circuit (as CPU) when synchronizing signal DR is effective up to data, if data are not read, then is updated behind next passage EOC.
At certain passage in effective time (SLOT[i] be high level), then respective channel is opened; Rest channels is closed, and the time-multiplexed clock signal that its corresponding multichannel is selected is a low level.Analog signal in this passage that is opened is latched and exports after being converted into numeral.The signal of gap marker signal indication output is from this passage that is opened during output, and the indication late-class circuit can read the signal of this output when output synchronizing signal DR was effective.When the effective clock signal of this passage that is opened finishes SLOT[i] become low level after, the clock signal of next passage produces, and finishes when the change-over period of prepass.
As a kind of preferred mode, the time-multiplexed clock signal SLOT[1:N that above-mentioned multichannel is selected], gap marker signal and output synchronizing signal DR can be with time-sequence control module generations.
As a kind of preferred mode, can be at the time-multiplexed clock signal SLOT[1:N that selects with multichannel] from N passage, select before one tunnel analog signal, choose wherein some or several passages that need acquired signal earlier from N passage A1-AN.The passage enable signal CH_EN[1:N that can adopt passage enable module shown in Figure 2 to produce] choose the passage that those need acquired signal.Have only passage enable signal CH_EN[i this moment when a certain passage Ai correspondence among N the passage A1-AN] and the time-multiplexed clock signal SLOT[i that selects of multichannel] while, this passage was just opened when effective; Otherwise this pathway closure.If channel selecting enable signal CH_EN[i] when invalid, do not produce effective output synchronizing signal DR.
As a kind of preferred mode, with passage enable signal CH_EN[1:N] choose need to gather and the passage of switching signal after, if the time-multiplexed clock signal SLOT[i that multichannel is selected] effectively, and passage enable signal CH_EN[i] invalid, can not carry out the AD conversion this moment.Not that is to say when the ADC module receives the analog signal that front stage circuits (multichannel selection module) sends over to quit work, finish effective period up to current passage.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (21)
1. multi-channel signal acquiring conversion method comprises:
A) the time-multiplexed clock signal that adopts multichannel to select is selected one tunnel analog signal from described multichannel;
B) described analog signal conversion is become digital signal;
C) described digital signal is latched and exports.
2. multi-channel signal acquiring conversion method according to claim 1, it is characterized in that, the analog switch of a multiselect one is provided, and the time-multiplexed clock signal that described multichannel is selected is controlled the analog switch of described multiselect one and select one tunnel analog signal from described multichannel.
3. multi-channel signal acquiring conversion method according to claim 1 and 2 is characterized in that, when the time-multiplexed clock signal that described multichannel is selected was effective, corresponding passage was opened; When the time-multiplexed clock signal that described multichannel is selected is invalid, corresponding pathway closure.
4. multi-channel signal acquiring conversion method according to claim 1 is characterized in that, adopts the gap marker signal when signal is exported in the step c), distinguishes different passages.
5. multi-channel signal acquiring conversion method according to claim 1 is characterized in that, adopts data output synchronizing signal when signal is exported in the step c), allows data to be read by late-class circuit.
6. according to claim 1,2,4,5 described multi-channel signal acquiring conversion method wherein, it is characterized in that, adopt the passage enable signal from described a plurality of passages, need to select the passage of acquired signal before the step a).
7. multi-channel signal acquiring conversion method according to claim 6 is characterized in that, when the time-multiplexed clock signal while that the passage enable signal and the multichannel of a certain passage correspondence in the described multichannel are selected was effective, this passage was opened; Otherwise this pathway closure.
8. multi-channel signal acquiring conversion method according to claim 7 is characterized in that, adopts the ADC module that described analog signal conversion is become digital signal in the step b); And described ADC module does not quit work when receiving described analog signal.
9. according to claim 1,2,4,5 described multi-channel signal acquiring conversion method wherein, it is characterized in that, adopt the ADC module that described analog signal conversion is become digital signal in the step b).
10. multi-channel signal acquiring conversion method according to claim 9, the adc circuit of described ADC module for approaching one by one.
11. a multi-channel signal acquiring change-over circuit comprises:
Channel selecting module is selected one tunnel analog signal from a plurality of passages; The ADC module becomes digital signal with described analog signal conversion; The output latch module latchs and exports described digital signal; Time-sequence control module produces required clock signal and the control signal of circuit working.
12. multi-channel signal acquiring change-over circuit according to claim 11, it is characterized in that the clock signal that described time-sequence control module produces comprises the open/close multichannel of the described passage of control time division multiplexing clock signal of selecting and the gap marker signal of distinguishing different passages with control signal.
13. multi-channel signal acquiring change-over circuit according to claim 12 is characterized in that, the pass of the figure place n of described gap marker signal and the number N of described passage is: n=log
2N.
14. multi-channel signal acquiring change-over circuit according to claim 12 is characterized in that, described multi-channel signal acquiring change-over circuit also comprises the passage enable module, produces the passage enable signal need to select acquired signal from described a plurality of passages passage.
15. multi-channel signal acquiring change-over circuit according to claim 14 is characterized in that, the time division multiplexing clock signal that described multichannel is selected is controlled the ON/OFF of described selecteed passage.
16., it is characterized in that clock signal that described time-sequence control module produces and control signal also comprise data output synchronizing signal, allow data to be read by late-class circuit according to claim 11 or 12 or 14 or 15 described multi-channel signal acquiring change-over circuits.
17. according to claim 11 or 12 or 14 or 15 described multi-channel signal acquiring change-over circuits, it is characterized in that, the reset signal that clock signal that described time-sequence control module produces and control signal also comprise the ADC module quits work when making the ADC module not receive described analog signal.
18., it is characterized in that described channel selecting module adopts the analog switch of multiselect one according to claim 11 or 12 or 14 or 15 described multi-channel signal acquiring change-over circuits.
19. multi-channel signal acquiring change-over circuit according to claim 18 is characterized in that the analog switch of described multiselect one is controlled by described time-sequence control module by NAND gate.
20., it is characterized in that the adc circuit of described ADC module according to claim 11 or 12 or 14 or 15 described multi-channel signal acquiring change-over circuits for approaching one by one.
21. according to claim 11 or 12 or 14 or 15 described multi-channel signal acquiring change-over circuits, it is characterized in that described ADC module produces passage EOC signal and gives time-sequence control module, make time-sequence control module produce the timing control signal of next passage change-over period.
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| CN103391147A (en) * | 2012-05-11 | 2013-11-13 | 中兴通讯股份有限公司 | Method and device for transmitting signals of communication power supply |
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| CN103391147A (en) * | 2012-05-11 | 2013-11-13 | 中兴通讯股份有限公司 | Method and device for transmitting signals of communication power supply |
| CN103391147B (en) * | 2012-05-11 | 2016-08-10 | 中兴通讯股份有限公司 | The transmission method of a kind of communication power supply semaphore and device |
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| CN104459638A (en) * | 2014-12-25 | 2015-03-25 | 中国矿业大学(北京) | Eight-channel share-based geological radar acquisition system |
| CN106549578A (en) * | 2016-12-21 | 2017-03-29 | 湖南国科微电子股份有限公司 | Multi-mode power source managing system |
| CN107014432A (en) * | 2017-04-12 | 2017-08-04 | 上海琪云压缩空气系统服务有限公司 | A kind of analog signal monitoring system and method |
| CN107491056A (en) * | 2017-06-07 | 2017-12-19 | 宝沃汽车（中国）有限公司 | Acquisition method, system, battery management system and the electric automobile of data |
| CN109067398A (en) * | 2018-07-16 | 2018-12-21 | 珠海市微半导体有限公司 | A kind of control method of multichannel adc circuit |
| CN109067398B (en) * | 2018-07-16 | 2022-04-01 | 珠海一微半导体股份有限公司 | Control method of ADC circuit with multi-channel signals |
| CN109547024A (en) * | 2019-01-09 | 2019-03-29 | 上海艾为电子技术股份有限公司 | The detection method and detection control apparatus of multi signal |
| CN109547024B (en) * | 2019-01-09 | 2024-04-16 | 上海艾为电子技术股份有限公司 | Multi-signal detection method and detection control device |
| CN113033133A (en) * | 2021-03-17 | 2021-06-25 | 烽火通信科技股份有限公司 | Logic multiplexing circuit design method and circuit structure |
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Application publication date: 20110518 |