CN206041557U - Cascode circuit - Google Patents
Cascode circuit Download PDFInfo
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- CN206041557U CN206041557U CN201620960249.1U CN201620960249U CN206041557U CN 206041557 U CN206041557 U CN 206041557U CN 201620960249 U CN201620960249 U CN 201620960249U CN 206041557 U CN206041557 U CN 206041557U
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Abstract
The utility model discloses a CASCODE CIRCUIT, including a plurality of functional modules, the fan -out of preceding stage functional module end is connected with the logic input end of back level functional module, and control signal is received to the logic input termination of first order functional module, be provided with first control circuit in the functional module and connect rather than the logic input end, be provided with the 2nd control circuit and connect rather than the fan -out end, the logic input of functional module end through logic control circuit with the 2nd control circuit's control end is connected. The utility model discloses need not to set up the synchro control that CASCODE CIRCUIT can be accomplished to complicated device, include that synchronous battery status detects and synchronous battery is balanced, reduced the complexity and the manufacturing cost of circuit.
Description
Technical field
The utility model is related to electric and electronic technical field, and in particular to a kind of cascade circuit.
Background technology
Multiple modules for realizing same or similar function are attached by certain regular connected mode, it is believed that
It is cascade circuit.The use occasion of cascade circuit has a lot, for example, multi-cascade amplifying circuit, the balance module of series-connected cell, etc.
Deng.By taking the balance module of series-connected cell as an example, battery, need to enter to battery electric quantity to extend battery life when being used in series
Row is balanced.As shown in figure 1, balance module U1, U2 and U3 carry out equilibrium to the battery 1- batteries 4 of four series connection.Balance module U1
Three input/output terminals be connected respectively to the negative terminal of battery 1, the anode (negative terminal of battery 2) of battery 1, the anode of battery 2.
Weighing apparatus module U1 makes both voltage differences within certain value by detecting the voltage of battery 1 and battery 2 and carry out equilibrium to which.When
The voltage versus cell 1 of battery 2 is higher than certain value, then input of the B points for balance module U1, output of the A points for balance module U1, electricity
Electricity in pond 2 is transferred in battery 1 by balance module U1；When the 2 high certain value of voltage versus cell of battery 1, A points are
The input of balance module U1, the output of B points position balance module U1, the electricity in battery 1 are transferred to electricity by balance module U1
In pond 2；In the same manner, U3 carries out equilibrium to battery 3 and battery 4；U2 carries out equilibrium to battery 1, battery 2 and battery 3, battery 4.
In order to improve voltage detecting precision in a balanced way, when balance module detects cell voltage, all balance modules all stop
It is only balanced.Therefore need to synchronize all balance modules so as to while balanced and stopping is balanced, to detect corresponding battery
Voltage.Then balance module stops equilibrium, and detects cell voltage, then carry out again to battery balanced certain hour
Weighing apparatus ... is so circulated, and is reached in the range of reasonable pressure.
In the prior art, all balance modules need CPU to desynchronize equilibrium, such as synchronous time and the stopping in a balanced way
The time of balanced detection cell voltage.As shown in figure 1, due to U1 and U2 altogether, CPU directly can transmit a signal to U1 and
U2.Not altogether, signal need to be transferred to U3 by optocoupler by CPU for U3 and CPU.For the battery equalization system of multiple batteries series connection
In, such as 16 batteries, as shown in Fig. 2 then most of balance module all gets along well CPU altogether, need multiple optocouplers, and system connection is multiple
It is miscellaneous, high cost.
As can be seen here, the cascade circuit of prior art is in the middle of practical application, and it is multistage same that part occasion needs to control which
Step, and prior art is due to Multi-stage module and controls its CPU not altogether, needs to arrange optocoupler to solve asking for Synchronization Control
Topic, increased the production cost of the complexity and product of circuit system connection.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of cascade of the complexity and cost for reducing Synchronization Control
Circuit, asks to the technology for arranging the complex devices such as optocoupler to realize cascade circuit synchronization that needs for solving prior art presence
Topic.
Technical solution of the present utility model is to provide a kind of cascade circuit of following structure, including multiple function moulds
Block, the logic output terminal of prime functional module are connected with the logic input terminal of rear class functional module, first order functional module it is defeated
Enter end and receive control signal；It is characterized in that：
It is provided with first control circuit to be connected with its logic input terminal in the functional module, is provided with second control circuit
It is connected with its logic output terminal, logic input terminal Jing logic control circuits and the second control circuit of the functional module
Control end connects.
Preferably, when the control signal that the logic input terminal of the first order functional module is received characterizes the second state,
The logic input terminal of first order functional module is placed in the second state by described control signal；When the first order functional module
The control signal that logic input terminal is received characterize first state or it is invalid when, the logic input terminal of described first order functional module
It is set to first state；Logic input terminal state and/or state duration of the logic control circuit according to functional module
And/or functional module internal signal, the working condition of second state control circuit is controlled, it is defeated to determine functional module logic
Go out the state at end, and transmit to the logic input terminal of rear class functional module.
Preferably, described functional module is battery balanced module, and described battery balanced module also includes battery status
Detection part and battery balanced part, described battery status detection part are used to detect respective battery state, described battery
Equalizing sections carry out the equilibrium between respective battery.
Preferably, described first state control circuit is pull-up circuit, and the second described state control circuit is drop-down
Circuit, the logic input terminal Jing logic control circuits of battery balanced module are connected with the control end of pull-down circuit.
Preferably, when described control signal is drop-down to the logic input terminal of battery balanced module, the first order is battery balanced
The logic input terminal of module is set to low level, and now the battery balanced module of the first order carries out battery status detection, during being somebody's turn to do
Battery balanced not enable, the low level of logic input terminal makes logic control circuit control pull-down circuit drop-down, by first order battery
The logic output terminal of balance module is drop-down, and is pulled low the logic input terminal of the battery balanced module of rear class successively, realizes synchronous
Battery status is detected.
Preferably, when described control signal is pulled up or is invalid to the logic input terminal of battery balanced module, first order electricity
The logic input terminal of pond balance module is pulled up circuit and is set to high level, and now to carry out battery equal for the battery balanced module of the first order
Weighing apparatus, does not carry out battery status detection during being somebody's turn to do, the high level of logic input terminal makes logic control circuit control pull-down circuit not
Drop-down, it is invalid that the logic output terminal of the first order battery balanced module is set to, and the battery balanced module logic input of subordinate is not
High level can be pulled low and be set to, the logic output terminal of present battery balance module is defeated in the logic of the battery balanced module of subordinate
Also high level is set in the presence of entering end, and is driven high the logic input terminal of the battery balanced module of subordinate successively, realize same
Step is battery balanced.
Preferably, when the logic input terminal of battery balanced module is pulled low, described logic control circuit control is described
Corresponding pull-down circuit will be the logic output terminal of battery balanced module drop-down, and now described battery balanced module carries out battery status
Detection, should during do not carry out it is battery balanced, while logic control circuit to battery status detection carry out timing；When default first
Between, when the logic input terminal of battery balanced module is set to high level, if the now battery status detection time not up to very first time,
Then voltage detecting is invalid, do not carry out yet it is battery balanced, into idle condition；When the logic input terminal of battery balanced module is set to height
Level, if now battery status detection time is more than the very first time, is carried out battery balanced.
Preferably, when battery balanced module carries out equilibrium, logic control circuit carries out timing to time for balance；Default the
Two times, if battery balanced module carries out the battery balanced time more than the second time, stopping carry out it is battery balanced, into sky
Not busy state；If carrying out the battery balanced time less than the second time, the logic input terminal of battery balanced module is pulled low, then into electricity
Pond state-detection state；In idle condition, when the logic input terminal of battery balanced module is set to low level, also into battery
State-detection state.
Preferably, when the logic input terminal of battery balanced module is pulled low, described logic control circuit control is described
Corresponding pull-down circuit will be the logic output terminal of battery balanced module drop-down, and now described battery balanced module carries out battery status
Detection, should during do not carry out it is battery balanced, while logic control circuit to battery status detection carry out timing；Logic control electricity
To after the battery status detection time for arranging, battery status detection terminates for road timing；Balance module carry out it is battery balanced, while patrolling
Volume control circuit carries out timing to time for balance, if logic control circuit timing not to the time for balance of setting when, it is battery balanced
The logic input terminal of module is set to high level, then balance module stopping is battery balanced, into idle condition, under the idle condition not
Carry out timing.
Preferably, when the battery balanced module carries out battery status detection, the logic input terminal of battery balanced module
High level is set to, meanwhile, second control circuit is not dragged down to the logic input terminal of battery balanced module, the battery balanced mould of rear class
The logic output terminal of present battery balance module is set to high level by the logic input terminal of block, now stops battery status detection,
Do not carry out battery balanced, into idle condition, under the idle condition, do not carry out timing yet；Under the idle condition, if the electricity
The logic input terminal of pond balance module is pulled low, then its logic output terminal is also pulled down, and now detects into battery status, goes forward side by side
Row timing.
Preferably, if battery balanced module is when timing is to the time for balance for arranging, the logic input of battery balanced module
When end is still low, then balance module stops equilibrium, does not also carry out battery status detection, into idle condition；Now, it is battery balanced
The logic input terminal of module is low, and logic control circuit carries out timing to the idle condition, when timing is to the free time for arranging
When, then balance module carries out battery status detection.
Using circuit structure of the present utility model, compared with prior art, with advantages below：The utility model is based on level
Connection circuit Synchronization Control, be particularly suited for multiple batteries series connection battery equalization system in, by the way of pull-down current come
Synchronous signal transmission, balance module have a synchronous signal input end Fi and a synchronous signal output end.When prime battery it is equal
The ground potential of weighing apparatus module is not higher than the ground potential of rear class balance module, then the synchronous signal output end of prime balance module can be right
The synchronous signal input end of rear class balance module carries out drop-down, then synchronizing signal passes to rear class equilibrium model by prime balance module
Block.The utility model completes the Synchronization Control of cascade circuit, including the detection of synchronous battery status by need not arranging complex devices
It is battery balanced with synchronous, reduce the complexity and production cost of circuit.
Description of the drawings
Fig. 1 is the circuit structure diagram of the battery balanced module of 4 batteries in prior art；
Circuit structure diagrams of the Fig. 2 for the battery balanced module of 16 batteries of prior art；
Electrical block diagrams of the Fig. 3 for the battery balanced module of 4 batteries of the utility model；
Fig. 4 is the internal circuit configuration figure of single battery balance module in Fig. 3；
Fig. 5 is a kind of FB(flow block) of mode of operation of the utility model；
Fig. 6 is working waveform figure of the utility model based on the FB(flow block) of Fig. 5；
Fig. 7 is the FB(flow block) of the utility model another kind mode of operation；
Fig. 8 is working waveform figure of the utility model based on the FB(flow block) of Fig. 7；
Fig. 9 is working waveform figure that the utility model is a kind of implementation for not meeting CPU；
Electrical block diagrams of the Figure 10 for the battery balanced module of 16 batteries of the utility model.
Specific embodiment
Preferred embodiment of the present utility model is described in detail below in conjunction with accompanying drawing, but the utility model is not merely
It is limited to these embodiments.The utility model covers any replacement made in spirit and scope of the present utility model, modification, equivalent
Method and scheme.
In order that the public has to the utility model thoroughly understand, in following the utility model preferred embodiment specifically
Clear concrete details, and description without these details can also understand that this practicality is new completely for a person skilled in the art
Type.
Referring to the drawings the utility model more particularly described below by way of example in the following passage.It should be noted that, accompanying drawing
Non- accurately ratio is used in the form of more simplifying and, only conveniently, lucidly to aid in illustrating the utility model
The purpose of embodiment.
With reference to shown in Fig. 3, the battery balanced module of 4 batteries of the utility model, multiple battery balanced module structures are illustrated
Into cascade circuit, including battery 1, battery 2, battery 3 and the battery 4 connected, the electricity of balance module U1, U2 and U3 to four series connection
Pond 1- battery 4 carries out equilibrium.Three input/output terminals of balance module U1 are connected respectively to the negative terminal of battery 1, the anode of battery 1
The anode of (negative terminal of battery 2) and battery 2.Balance module U1 obtains the two by detection battery 1 and the voltage of battery 2
Pressure reduction, and carry out equilibrium to which, makes both voltage differences within reasonable value.When the 1 high certain value of voltage versus cell of battery 2, then B
Input of the point for balance module U1, output of the A points for balance module U1, the electricity in battery 2 are transmitted by balance module U1
To in battery 1, U1 is operated in decompression mode；When the 2 high certain value of voltage versus cell of battery 1, A points are defeated for balance module U1's
Enter, output of the B points for balance module U1, U1 are operated in boost mode, and the electricity in battery 1 is transferred to by balance module U1
In battery 2；In the same manner, U3 carries out equilibrium to battery 3 and battery 4；U2 carries out equilibrium to battery 1, battery 2 and battery 3, battery 4.U1
With U3 as ground floor balance module, and U2 is used as the balance module of the second layer.
The present embodiment come synchronous signal transmission (as control signal), but adopts pull-up current by the way of pull-down current
Mode can also implement, now only illustrated in the way of pull-down current, the synchronous input end Fi of balance module U1 is (as patrolling
Volume input) control signal as synchronizing signal is received, the synchronizing signal can be produced by CPU, also can be and straight without CPU
Accessing one has drop-down and not drop-down signal, is arranged as required to drop-down and not drop-down corresponding pulsewidth, Huo Zhejie
Enter pulldown signal as control signal, stop when not needed drop-down.The synchronous output end Fo of balance module U1 will be synchronous
Signal is transmitted to the synchronous input end Fi of rear class balance module U2.Synchronizing signal in the present embodiment is current signal, to battery
The synchronous input end Fi of balance module carries out pullup or pulldown, and synchronizing signal refers to no signal input when being invalid, do not having
The situation of signal input, the synchronous input end of battery balanced module are set to high level by the pull-up circuit of first control circuit.Though
So in the present embodiment, the control signal that pull-down current is exported with CPU the synchronous input end Fi of balance module U1 is carried out it is drop-down, but
It is the different designs according to first control circuit and second control circuit, it would however also be possible to employ the control letter of CPU output pull-up currents
Number the synchronous input end Fi of balance module U1 is pulled up, thus in the present embodiment preferably embodiment can not constitute it is right
The restriction of the utility model scope, therefore here is explained, and this explanation is equally applicable to the feelings of other accompanying drawings and embodiment
Condition, i.e., in the case where CPU is not met, it would however also be possible to employ the mode of pull-up current.
The ground potential of battery balanced module 1 is not higher than the ground potential of balance module 2, the synchronizing signal of battery balanced module 1
Output end Fo can carry out drop-down to the synchronous signal input end Fi of battery balanced module 2, then synchronizing signal is passed by balance module 1
Battery balanced module 2 is passed, i.e., by prime module by synchronous transmission of signal to post-module；Battery balanced module 2 be further continued for by
Synchronous transmission of signal is not higher than battery balanced module U3 of battery balanced module 2 to next ground potential.
With reference to shown in Fig. 4, the internal circuit configuration of the battery balanced module of the utility model, including synchronous input end are illustrated
Fi and synchronous output end Fo (as logic output terminal), because functional module of the present utility model is by taking battery balanced module as an example, the
The synchronous input Fi connections of one control circuit, the synchronous output end Fo connection of second control circuit are described battery balanced
The synchronous input end Jing logic control circuits of module are connected with the control end of the second control circuit.The first described control electricity
Road is pull-up circuit, and described second control circuit is pull-down circuit, the synchronous input end Fi Jing logic controls of battery balanced module
Circuit processed is connected with the control end of pull-down circuit.
Described pull-up circuit includes resistance R1, a termination power end Vd of the resistance R1, and the resistance R1's is another
Termination synchronous input end Fi.Described pull-down circuit includes switching tube M1, the first termination synchronous output end of the switching tube M1
The second end ground connection of Fo, the switching tube M1, control end G of described switching tube M1 are connected with logic control circuit.Described
Switching tube M1 can adopt N-type power switch pipe.When switching tube M1 can adopt p-type power switch pipe, then need to the second control electricity
The circuits such as road are improved, and those of ordinary skill in the art can know such conversion.
In battery balanced module, synchronous input end Fi connects puller circuit, and pull-up circuit is connected to the power end of balance module
Vd；Synchronous output end Fo connects pull-down circuit, and pull-down circuit is connected to the reference ground of battery balanced module, and wherein pull-down circuit is drop-down
Pull-up current of the electric current more than pull-up circuit.It is drop-down whether logic control circuit output signal G control pull-down circuit is carried out to Fo.
When logic control circuit output G is high level, M1 conductings, Fo are low；When logic control circuit exports low level, M1 is turned off,
Pull-down current is 0, Fo not drop-down.
In the present embodiment, " first state " therein is high level in Fig. 4 embodiments, and " the second state " refers to low electricity
Flat, engineering noise refers to no signal." control signal sign first state " is referred to and can be pulled up synchronous input end by control signal,
And " it is invalid to characterize " refers to do not have the situation of pullup or pulldown, now in the presence of the pull-up circuit of first control circuit, then
Synchronous input end Fi can be placed in high level.For example, during M1 shut-offs, the synchronous output end Fo of present battery balance module does not have
There is electric current pulldown signal, but as the synchronous input end Fi of the battery balanced module of rear class has pull-up circuit to be pulled up, then now
The synchronous output end Fo of present battery balance module can be drawn high by rear class.It should be noted that the portion of buck is eliminated in Fig. 4
Point, i.e. balance module works in decompression mode, and electricity is transmitted in the low side of the high lateral voltage of voltage；Balance module works in boosting
Pattern, the high side of the low lateral voltage of voltage transmit electricity, and the Basic Topological which is realized can adopt conventional Buck open up
Flutter or Boost is topological, control the break-make of master power switch pipe and continued flow tube as needed, from the perspective of on essential meaning, when opening up
After the input/output terminal flutterred is exchanged, it is exactly to change from buck topology to Boost topology, or turns from Boost topology to buck topology
Change.
With reference to shown in Fig. 5, the FB(flow block) of the utility model one of which mode of operation is illustrated.The first described control
Circuit (pull-up circuit) is output as high level (i.e. first state), if the synchronous input end Fi of battery balanced module does not receive synchronization
Signal or synchronizing signal are invalid, then synchronous input end Fi is in high level；When the synchronization input of the first order functional module
When the synchronizing signal that end receives is by synchronous input end drop-down (characterizing the second state), described synchronizing signal is by battery balanced mould
The synchronous input end of block is placed in low level；The logic control circuit according to the synchronous input end state of battery balanced module and/
Or state duration and/or functional module internal signal, the working condition of the second control circuit is controlled, to determine battery
The state of balance module synchronous output end Fo, and transmit to the synchronous input end Fi of the battery balanced module of rear class.Described is " synchronous
Input state " refers to high level or low level in the present embodiment, naturally it is also possible to arrange or define other state conducts
Trigger condition.Time and/or the electricity of time and/or voltage detecting of described " state duration " including holding low and high level
Pond time in a balanced way.By taking the present embodiment as an example, then employ the duration phase of the state and battery status detection of low and high level
With reference to mode, adjust and control the flow process under this mode of operation." the functional module internal signal " is referred to except synchronous defeated
Enter outside end other can by the signal produced inside functional module or via the incoming signal to functional module in outside, due to
Finally enter inside functional module via the incoming signal to functional module in outside, therefore also included the inside of functional module
Signal, for example, the timing signal that logic circuit is produced；By detecting detection signal, etc. obtained from battery status.
Flow process in Fig. 5 is applied to into the cascade circuit that the balance module in Fig. 4 is constituted, it is specific as follows：Battery balanced mould
Block U1 meets CPU and synchronizes, and produces synchronizing signal by CPU, and synchronizing signal is connected to the synchronous input end of balance module U1
Fi, the synchronous output end Fo of battery balanced module U1 are connected to the synchronous signal input end Fi of balance module U2, battery balanced mould
The synchronous transmission of signal is given balance module U2 by block U1, and U2 is again by the synchronous transmission of signal to U3.Successively synchronizing signal is transmitted
Give rear class balance module.Wherein, the ground potential of rear class balance module is not less than the ground potential of prime balance module.
When CPU carries out drop-down to the Fi ends of U1, then the Fi ends of U1 are for low, and control the switching tube M1 in pull-down circuit and lead
Logical, Fo carries out drop-down to the synchronous input end Fi of battery balanced module U2 of rear class, makes the switch of post-module detect Fi to be
It is low, M1 conductings.So one by one the Fi ends of balance module are dragged down, M1 conductings, all balance modules are made while stopping equal
Weighing apparatus, carries out battery status detection, if battery status detection time is more than after very first time t1, CPU stop carrying out Fi ends it is drop-down,
Then Fi ends are pulled up circuit and are pulled upward to high level, stop battery status detection, carry out equilibrium, while Fi is controlled by control logic
Circuit so as to which it is low, M1 shut-offs to export G, makes pull-down current stop carrying out down the synchronous input end Fi of the balance module of rear class
Draw.So one by one the Fi ends of battery balanced module are drawn high, and turn off M1, all balance modules are made while stopping battery
State-detection, carries out equilibrium.
CPU stops carrying out Fi ends drop-down, then Fi is pulled up circuit and is pulled upward to high level, now battery status detection time
If being less than very first time t1, stop battery status detection, also do not carry out equilibrium, while Fi ends are by control logic control circuit,
Make its output G be low, M1 shut-offs, make pull-down current stop carrying out down the synchronous signal input end Fi of the battery balanced module of rear class
Draw.So one by one the Fi ends of battery balanced module are drawn high, turns off M1, all battery balanced modules are made while stopping
Battery status detection, does not carry out equilibrium.Above-described " while " and nisi synchronization, as the signal of one-level one-level is passed
Pass, can there is certain delay, therefore here is explained.The threshold value that very first time t1 is used as battery status detection is set in addition
Time, the factors such as interference are mainly in view of, that is, have ensured that time enough carries out battery status detection, otherwise may be because of dry
The factor of disturbing causes the fluctuation of pressure reduction, and erroneous trigger is battery balanced.
It is high level in Fi, and when carrying out battery balanced, if time for balance is to the second time t2, CPU does not also enter to Fi
Row is drop-down, then battery balanced module enters idle condition, i.e., do not carry out battery balanced, does not also carry out battery status detection.Through
After the high level time that CPU is arranged, CPU carries out drop-down to Fi, then Fi pulled down to low level, switching tube M1 conductings, and such one
Battery balanced module synchronization signals input Fi is dragged down by level one-level ground, is so circulated.The purpose for arranging the second time t2 is,
Avoid generation from excessively continuing situation in a balanced way, if not dragging down synchronous input end always, equilibrium may be carried out always, therefore needed
Diacritical point during setting.
The working waveform figure of the FB(flow block) based on Fig. 5 with reference to shown in Fig. 6, is illustrated, is mainly shown each battery balanced
The waveform of the synchronous input end Fi of module.After synchronous input end Fi is pulled low, then detects into battery status, do not carry out battery
It is balanced；When CPU stops carrying out Fi ends drop-down, then Fi is pulled up circuit and is pulled upward to high level, now battery status detection time
If during more than very first time t1, now meeting pressure differential, i.e. pressure reduction more than default threshold pressure differential, then into battery balanced,
Synchronous input end Fi is driven high；After the completion of battery balanced, its time for balance is less than the second time t2, then synchronous input end Fi is again
Degree is pulled low, and detects into battery status；When time for balance reaches the second time t2, CPU does not also carry out drop-down to Fi, then enter
Idle condition, does not carry out battery status detection in idle condition, do not carry out yet it is battery balanced, in idle condition, synchronizing signal
After input Fi is pulled low, then battery status detection is again introduced into, if battery status detection time is less than very first time t1, then
Secondary entrance idle condition.
With reference to shown in Fig. 7, the FB(flow block) of wherein another kind of mode of operation of the utility model is illustrated, in this mode,
The battery balanced module of the first order works by need not meeting CPU.Synchronous input end Fi of the logic control circuit in battery balanced module
For it is low when timing is carried out to time for balance and battery status detection time, Fi for it is high when do not carry out timing.System
After upper electricity, when synchronous signal input end Fi is low, logic control circuit output G is height, the output of logic control circuit
End is connected with the control end of pull-down circuit, and synchronous output end Fo is low, and battery balanced module carries out battery status detection, does not carry out
It is battery balanced, while logic control circuit carries out timing.During the battery status detection that logic control circuit timing is arranged to inside
Between after, battery status detection terminate, battery balanced module carry out it is battery balanced, while logic control circuit is carried out to time for balance
Timing.
In equilibrium state, if Fi was high before the time for balance that logic control circuit timing is arranged to inside which,
Weighing apparatus module enters idle condition, and (as timing is not carried out under the state, for ease of distinguishing, the idle condition is used as in the present embodiment
The first idle condition), balance module stops balanced, does not also carry out battery status detection, and logic control circuit in Fi is
It is low that G is exported when high, and control M1 shut-offs, logic control circuit are not-time；If in logic control circuit timing to inside which
During the time for balance of setting, Fi is low always, then balance module stops equilibrium, does not also carry out battery status detection, and logic
Control circuit output G is low, control M1 shut-offs.Now, as Fi is low, logic control circuit is to the idle condition (due to this
Need to carry out timing under state, for ease of distinguish, the idle condition as the present embodiment in the second idle condition) carry out timing,
When timing is to internal setting free time, then balance module carries out battery status detection, and M1 conductings are so circulated.
The working waveform figure of the FB(flow block) based on Fig. 7 with reference to shown in Fig. 8, is illustrated, is mainly shown each battery balanced
The waveform of the synchronous input end Fi of module.After synchronous input end Fi is pulled low, then detects into battery status, do not carry out battery
Equilibrium, while logic control circuit carries out timing.Logic control circuit timing to after TA (battery status detection time), battery shape
State detection terminates, and battery balanced module carries out battery balanced, and now synchronous input end Fi remains as low level, logic control circuit
Timing is carried out to time for balance, after elapsed time TB, the also non-timing of timing of the logic control circuit to time for balance is to inside which
The time for balance of setting, now synchronous input end Fi be set to high level, battery balanced module enters idle condition, balance module
Stop equilibrium, also do not carry out battery status detection.Through CPU arrange high level time TC after, CPU Fi is carried out it is drop-down, then
Fi pulled down to low level, and the Fi ends of balance module are so dragged down, so circulated by M1 conductings one by one.
With reference to shown in Fig. 9, the working waveform figure that the utility model does not connect a kind of implementation of CPU is illustrated, but,
In the case of not meeting CPU, a kind of mode that Fig. 9 simply illustrates is not constituted to restriction of the present utility model.In the feelings for not meeting CPU
Under condition, the synchronous input end Fi of battery balanced module U1 is configured, such as the synchronous input end Fi of U1 is grounded, is now led to
Cross U1 and produce synchronizing signal, and synchronizing signal is passed to into the battery balanced module of rear class successively.Wherein, the ground potential of post-module
It is not less than the ground potential of prime module.
Specifically make the mode of U1 generation synchronizing signals as follows：The synchronous input end Fi of U1 is connect into low level, then it is synchronous to be input into
End Fi is pulled low, and logic control circuit controlled output G is height, and the switching tube M1 conductings of pull-down circuit make Fo be low, by rear class
The Fi of module is dragged down, and one-level Primary Transmit, and the Fi for making all battery balanced modules is low, makes all battery balanced modules same
When first stop equilibrium, carry out battery status detection, after certain time interval T D, then carry out equilibrium.When logic control circuit is to equal
During the time for balance TE that the timing of weighing apparatus time is arranged to inside, balance module stops equilibrium, and logic control circuit output G is low, control
M1 processed shut-off, stops carrying out the Fi of the battery balanced module of rear class drop-down, makes post-module also stop equilibrium, and rear class is battery balanced
The input Fi of module is set to high level.
As the timing of each module can be different, may not all modules simultaneously stop equilibrium, that is, will not
Simultaneously stop drop-down Fi, but have sequencing, it is possible to occur the module having enter detection pattern and some modules also
In balanced mode, so can there is the delay of signal transmission, and nisi synchronization in synchronization described in the utility model, but
Technical problem of the present utility model is can solve the problem that, while here is illustrated, the solution of technical problem is not perfect.Due to the Fi of U1
Ground connection (also referring to low level), U1 carry out timing to stopping the time in a balanced way, after time TF of the timing to its internal setting, U1's
Logic control circuit output G is height, and control M1 conductings carry out drop-down, and one-level Primary Transmit, make the Fi of all modules to rear class
All it is low.So, in addition to Fi meets low level U1, on the Fi of all modules, can all there is the signal of low and high level.Therefore can
By the signal on Fi being detected always as low, to make U1 produce synchronizing signal, carry out synchronous all battery balanced modules.As U1 is
Bottom module, and when not accessing CPU, arrange the time for balance that arranges inside U1 than all inside modules arrange it is balanced when
Between it is all short, to realize synchronization.
With reference to shown in Figure 10, the battery balanced module of 16 batteries of the utility model, multiple battery balanced modules are illustrated
Constitute cascade circuit.For the battery balanced module of a 16 batteries series connection, using pull-down current mode synchronous signal transmission,
The synchronous principle of its signal can be found in the embodiment of 4 batteries, and therefore not to repeat here.
In the battery balanced module using current signal transfer synchronizing signal, voltage signal is transmitted without the need for optocoupler, or even
CPU can not needed, and system connection is simple, and each balance module only needs to a synchronous input end and a synchronism output
End.
In the embodiment of Fig. 3 and Figure 10, the two has all referred to the situation of point multiple levels of battery balanced module.In figure
In 3, the battery balanced module for being labeled as T1 is the first level, and the battery balanced module for being labeled as T2 is the second level.In Figure 10
In, the battery balanced module for being labeled as T1 is the first level, and the battery balanced module for being labeled as T2 is the second level, is labeled as T3
Battery balanced module be third layer level.As the description for Fig. 3, only for man-to-man battery balanced, U2 is then for U1 and U3
Realize the equilibrium of two pairs two.In the same manner, Figure 10 and other possible deformations, arrange level all in accordance with actual conditions.
In addition, although above embodiment is separately illustrated and is illustrated, but it is related to the common technology in part, in this area
Those of ordinary skill apparently, can be replaced between the embodiments and integrate, and be related to one of embodiment and be not expressly recited
Content, then refer to another embodiment on the books.
Embodiments described above, does not constitute the restriction to the technical scheme protection domain.It is any in above-mentioned enforcement
Modification, equivalent and improvement made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (11)
1. a kind of cascade circuit, including multiple functional modules, logic output terminal and the rear class functional module of prime functional module
Logic input terminal connects, and the logic input terminal of first order functional module receives control signal；It is characterized in that：
Be provided with first control circuit to be connected with its logic input terminal in the functional module, be provided with second control circuit and its
Logic output terminal connection, the logic input terminal Jing logic control circuits of the functional module and the control of the second control circuit
End connection.
2. cascade circuit according to claim 1, it is characterised in that：When the logic input terminal of the first order functional module
When the control signal of reception characterizes the second state, the logic input terminal of first order functional module is placed in the by described control signal
Two-state；When the first order functional module logic input terminal receive control signal characterize first state or it is invalid when, institute
The logic input terminal of the first order functional module stated is set to first state；Logic control circuit the patrolling according to functional module
Input state and/or state duration and/or functional module internal signal are collected, the work of the second control circuit is controlled
State, to determine the state of functional module logic output terminal, and transmits to the logic input terminal of rear class functional module.
3. cascade circuit according to claim 1, it is characterised in that：Described functional module be battery balanced module, institute
The battery balanced module stated also includes battery status detection part and battery balanced part, and described battery status detection part is used
In detection respective battery state, described battery balanced part carries out the equilibrium between respective battery.
4. cascade circuit according to claim 3, it is characterised in that：Described first control circuit be pull-up circuit, institute
The second control circuit stated is pull-down circuit, the logic input terminal Jing logic control circuits and pull-down circuit of battery balanced module
Control end connects.
5. cascade circuit according to claim 4, it is characterised in that：Described control signal is patrolled to battery balanced module
When volume input is drop-down, the logic input terminal of the battery balanced module of the first order is set to low level, and now the first order is battery balanced
Module carries out battery status detection, and battery balanced during being somebody's turn to do not enable, the low level of logic input terminal makes logic control circuit
Control pull-down circuit is drop-down, will be the logic output terminal of the first order battery balanced module drop-down, and makes the battery balanced mould of rear class successively
The logic input terminal of block is pulled low, and realizes synchronous battery status detection.
6. cascade circuit according to claim 4, it is characterised in that：Described control signal is patrolled to battery balanced module
When collecting input pull-up or the logic input terminal of battery balanced module not controlled, the logic input of the battery balanced module of the first order
End is pulled up circuit and is set to high level, now the battery balanced module of the first order carry out it is battery balanced, should during do not carry out battery
State-detection, the high level of logic input terminal make logic control circuit control pull-down circuit not drop-down, the battery balanced module of subordinate
Logic input terminal will not be pulled low and be set to high level, and the logic output terminal of present battery balance module is equal in subordinate's battery
Also high level is set in the presence of the logic input terminal of weighing apparatus module, and make the logic input terminal of the battery balanced module of subordinate successively
It is driven high, realizes synchronous battery balanced.
7. the cascade circuit according to claim 5 or 6, it is characterised in that：When the logic input terminal quilt of battery balanced module
When dragging down, described logic control circuit controls corresponding pull-down circuit will be the logic output terminal of battery balanced module drop-down
Now described battery balanced module carries out battery status detection, should during do not carry out it is battery balanced, while logic control circuit
Timing is carried out to battery status detection；The default very first time, when the logic input terminal of battery balanced module is set to high level, electricity
If not up to very first time pond state-detection time, battery status detection it is invalid, do not carry out yet it is battery balanced, into idle shape
State；When the logic input terminal of battery balanced module is set to high level, if battery status detection time is more than the very first time, enter
Row is battery balanced.
8. the cascade circuit according to claim 5 or 6, it is characterised in that：When battery balanced module carries out equilibrium, logic
Control circuit carries out timing to time for balance；Default second time, if battery balanced module carries out the battery balanced time being more than
Second time, then stop carry out it is battery balanced, into idle condition；If carry out the battery balanced time less than the second time, electricity
The logic input terminal of pond balance module is pulled low, then detect state into battery status；In idle condition, when battery balanced mould
The logic input terminal of block is set to low level, detects state also into battery status.
9. cascade circuit according to claim 4, it is characterised in that：Described control signal is patrolled to battery balanced module
When volume input is drop-down, the logic input terminal of the battery balanced module of the first order is set to low level, and described control signal is to electricity
When the logic input terminal of pond balance module pulls up or be hanging, the logic input terminal of the battery balanced module of the first order is pulled up circuit and puts
For high level；When the logic input terminal of battery balanced module is low level, described logic control circuit control is described corresponding
Pull-down circuit will be the logic output terminal of battery balanced module drop-down, now described battery balanced module carries out battery status inspection
Survey, should during do not carry out it is battery balanced, while logic control circuit to battery status detection carry out timing；Logic control circuit
To after the battery status detection time for arranging, battery status detection terminates for timing；Balance module carry out it is battery balanced, while logic
Control circuit carries out timing to time for balance, if logic control circuit timing not to arrange time for balance when, battery balanced mould
The logic input terminal of block is set to high level, then balance module stopping is battery balanced, into idle condition, does not enter under the idle condition
Row timing.
10. the cascade circuit according to claim 4 or 9, it is characterised in that：Battery shape is carried out in the battery balanced module
When state is detected, the logic input terminal of battery balanced module is set to high level, meanwhile, second control circuit is not to battery balanced mould
The logic input terminal of block is dragged down, and the logic input terminal of the battery balanced module of rear class is by the logic output terminal of present battery balance module
Be set to high level, now stop battery status detection, do not carry out yet it is battery balanced, into idle condition, under the idle condition not
Carry out timing；Under the idle condition, if the logic input terminal of the battery balanced module is pulled low, its logic output terminal
It is pulled down, now detects into battery status, and carry out timing.
11. cascade circuits according to claim 4 or 9, it is characterised in that：If battery balanced module is in timing to setting
During time for balance, when the logic input terminal of battery balanced module is still low, then balance module stops equilibrium, does not also carry out battery shape
State is detected, into idle condition；Now, the logic input terminal of battery balanced module is low, and logic control circuit is to the idle shape
State carries out timing, and when timing is to the free time for arranging, then balance module carries out battery status detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620960249.1U CN206041557U (en) | 2016-08-29 | 2016-08-29 | Cascode circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620960249.1U CN206041557U (en) | 2016-08-29 | 2016-08-29 | Cascode circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206041557U true CN206041557U (en) | 2017-03-22 |
Family
ID=58305777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620960249.1U Expired - Fee Related CN206041557U (en) | 2016-08-29 | 2016-08-29 | Cascode circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206041557U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106208244A (en) * | 2016-08-29 | 2016-12-07 | 杰华特微电子（张家港）有限公司 | Cascade circuit and synchronisation control means thereof |
| EP3700050A1 (en) * | 2019-02-20 | 2020-08-26 | Samsung SDI Co., Ltd. | Method and battery management system for controlling cell balancing |
-
2016
- 2016-08-29 CN CN201620960249.1U patent/CN206041557U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106208244A (en) * | 2016-08-29 | 2016-12-07 | 杰华特微电子（张家港）有限公司 | Cascade circuit and synchronisation control means thereof |
| EP3700050A1 (en) * | 2019-02-20 | 2020-08-26 | Samsung SDI Co., Ltd. | Method and battery management system for controlling cell balancing |
| US11631980B2 (en) | 2019-02-20 | 2023-04-18 | Samsung Sdi Co., Ltd. | Method and battery management system for controlling cell balancing |
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