CN1753174A - 无外引脚封装结构 - Google Patents

无外引脚封装结构 Download PDF

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CN1753174A
CN1753174A CNA2004100118620A CN200410011862A CN1753174A CN 1753174 A CN1753174 A CN 1753174A CN A2004100118620 A CNA2004100118620 A CN A2004100118620A CN 200410011862 A CN200410011862 A CN 200410011862A CN 1753174 A CN1753174 A CN 1753174A
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chip carrier
lead frame
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CN100349288C (zh
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盖永锋
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及一种无外引脚封装结构，主要包含一导线架、一芯片、一黏胶及多条导电线，其中，导线架由芯片座及其周缘多个引脚所组成，且该等引脚环设于该芯片座周边；另外，芯片座具有一黏晶区、一凹槽及一芯片接地区，且该凹槽设置于黏晶区及接地区间，再者，芯片背面通过黏胶设置于芯片座上，且主动表面借助多条导电线分别与引脚电性接合，值得注意的是，凹槽为上窄下宽，故黏胶涂布于芯片座时，过量的银胶能分布于凹槽中以适当地控制而不溢入芯片座的接地区，因此芯片通过导电线与芯片座接地导通时，不会因溢出银胶的作用，而影响导电线与芯片座接地区的接合强度。

Description

无外引脚封装结构
技术领域
本发明涉及一种无外引脚封装结构，特别是一种可提升芯片与导线架间电性接合可靠度及提升封胶材与导线架间的接合可靠度的无外引脚封装结构。
背景技术
近年来，由于移动电话、个人数字助理(personal digital assistance，PDA)、及数字相机等消费性电子产品的需求与日俱增，因此封装构造的型态朝向于重量轻、尺寸小，及信号传输路径短等方向来发展。
其中，由Matsushita公司所开发的无外引脚封装结构(即四方扁平无引脚封装结构(Quad Flat Nolead Package，QFN))，为以导线架为构装基材的芯片尺寸构装(lead frame based CSP)。由于无引脚型(leadless)的芯片尺寸构装具有信号传递路径(trace)短，降低信号衰减的优点，一直是低脚位(low pin count)半导体元件常用的构装结构。
请参照图1，其显示现有无外引脚封装结构的剖面示意图。该无外引脚封装结构的导线架110(如铜导线架)由芯片座112(die pad)及其周缘多个引脚114(lead)所组成。其中，芯片座112包含芯片接合区112a及接地区112b，且芯片120以其背面122通过银胶130(silver paste)与芯片座112的芯片接合区112a贴合。芯片120的主动表面124(activesurface)上的焊垫126(bonding pad)则通过导电线(金线)140(goldwire)，分别与引脚114的顶面114a连接及芯片座112的接地区112b，形成电性导通。而封胶材150(molding compound)包覆芯片120、导电线140、芯片座112的芯片接合区112a及接地区112b及引脚114的顶面114a，而暴露出芯片座112的底面112c及引脚114的底面114b。通过引脚114的底面114b与外部的印刷电路板(未显示)连接。
承上所述，为使芯片120能与芯片座112紧密接合，常需涂布适量的银胶130以作为连接之用；惟当芯片120的尺寸与芯片座112的尺寸相近，且芯片120周边128距离导电线140与芯片座112的接地区112b小于6μ(mils)时(即D＜6mils)，过量的银胶将溢入接地区112b，使得导电线无法与芯片座112的接地区112b紧密地接合。也因此使得无外引脚封装结构的产品可靠度降低。
有鉴于此，为避免前述无外引脚封装结构的缺点，以提升多无外引脚封装结构的封胶材与导线架间接合可靠度及提升芯片与导线架间电性接合可靠度，实为一重要的课题。
发明内容
有鉴于上述课题，本发明的目的在于克服现有技术的不足与缺陷，提供一种无外引脚封装结构，用以提升无外引脚封装结构中芯片与导线架间电性接合的可靠度及提升封胶材与导线架间的接合可靠度。
为达上述目的，本发明提供一种无外引脚封装结构，主要包含一导线架、一芯片、一黏着层(液态黏着胶或银胶)及多条导电线。其中，导线架由芯片座及其周缘多个引脚所组成，且芯片座具有一黏晶区、一凹槽及一芯片接地区，且凹槽设置于芯片接地区与黏晶区间。而芯片具有一背面及一主动表面，且芯片以背面面向芯片座设置于黏晶区上并通过黏着层与芯片座接合，而主动表面通过多条导电线分别与引脚电性接合。
综上所述，由于芯片座的接地区与黏晶区间设置一凹槽，故银胶涂布于黏晶区时，凹槽中能容置过量的银胶，使银胶能适当地受到控制而不易溢入芯片座的接地区域，故芯片通过导电线与芯片座接地导通时，不会因溢出银胶的作用，而影响导电线与芯片座接地区域的接合强度。再者，由于凹槽为上窄下宽的形式，故可增加芯片座与封胶体的结合强度。
附图说明
图1为一示意图，显示现有无外引脚封装结构的剖面示意图；
图2为一示意图，显示本发明较佳实施例的无外引脚封装结构的剖面示意图；
图3为一示意图，显示本发明第一较佳实施例中导线架的俯视示意图；
图4为一示意图，显示图3中A-A处的芯片座的剖面示意图。
图中符号说明
110   导线架
112   芯片座
112a  芯片接合区
112b  接地区
112c  芯片座底面
114   引脚
114a  引脚顶面
114b  引脚底面
120   芯片
122   芯片背面
124   芯片主动表面
126   芯片焊垫
128   芯片周边
130   黏着胶(银胶)
140   导电线
150   封胶材
210   导线架
212   芯片座
212a  黏晶区
212b  凹槽
212c  接地区
212d  芯片座底面
212e  凹槽开口
212f  凹槽底面
212g  凹槽侧壁
212h  凹槽底面与凹槽侧壁的夹角
214a  引脚顶面
214b  引脚底面
220   芯片
222   芯片背面
224   芯片主动表面
230   黏着层(银胶)
240   导电线
250   封胶材
具体实施方式
以下将参照相关附图，说明依本发明较佳实施例的无外引脚封装结构。
图2显示本发明的第一较佳实施例的无外引脚封装结构。本发明的无外引脚封装结构至少包含导线架210、芯片220、黏着层230(液态黏着胶、银胶或B-stage胶)及多条导电线240。其中，图3显示本发明实施例中所述的导线架210(如铜导线架)俯视图，导线架210(如铜导线架)由芯片座212及其周缘多个引脚214所组成，且芯片座212具有一黏晶区212a、一凹槽212b及一接地区212c，其中该凹槽212b设置于黏晶区212a及接地区212c之间且环绕黏晶区212a的周边配置。而芯片220具有一背面222及一主动表面224，且芯片220以背面222面向芯片座212设置于黏晶区212a上并通过黏着层230(如液态黏着胶、银胶或B阶胶层)与芯片座210接合，而主动表面224通过多条导电线240分别与引脚214电性接合及接地区212c接地导通。
再者，本发明的无外引脚封装结构更可包含封胶材250(moldingcompound)包覆芯片220、导电线240、芯片座212的黏晶区212a、凹槽212b及接地区212c与引脚214的顶面214a，而暴露出芯片座212的底面212d及引脚214的底面214b。通过引脚214的底面214b及芯片座212的底面212d与外部的印刷电路板(未显示)连接。
再者，请参考图4，其显示本实施例图3中A-A处的芯片座的剖面示意图。于蚀刻形成凹槽时，可通过蚀刻阻罩的设计及控制蚀刻时间，使凹槽的开口212e小于凹槽底面212f。如此更可通过凹槽侧壁212g的倾斜设计，即该凹槽侧壁212g与底面连接形成一角度，且该角度小于90度，以使封胶材250与导线架间的接合强度提升。
承上所述，一般凹槽212b的深度约大于芯片座212厚度的二分之一。如此，芯片220容置于凹槽212b中时，由于芯片座212的接地区212c域突出设置于凹槽212b周边，故涂布于芯片凹槽212b中的液态黏着层230能适当地被控制而不易溢入芯片座212的接地区212c，如此芯片220通过导电线240与芯片座212接地导通时，不会因溢出液态黏着层230(如银胶)的作用，而影响导电线240与芯片座212接地区212c的接合强度。
于本实施例的详细说明中所提出的具体的实施例仅为了易于说明本发明的技术内容，而并非将本发明狭义地限制于该实施例，因此，在不超出本发明的精神及以下权利要求书的情况，可作种种变化实施。

Claims (11)

1.一种无外引脚封装结构，其特征在于，包含：
一导线架，具有一芯片座及多个引脚，该芯片座具有一黏晶区、一凹槽及一芯片接地区，该等引脚环设于该芯片座周边，且该凹槽设置于该黏晶区及该接地区之间；
一芯片，具有一主动表面及一背面，该背面设置于该黏晶区上；
至少一第一导电线，该第一导电线连接该芯片与该芯片座的该接地区；以及
至少一第二导电线，该第二导电线连接该芯片与该引脚之一。
2.如权利要求1所述的无外引脚封装结构，其中，更包含一黏着层，该黏着层设置于黏晶区与该芯片的背面间。
3.如权利要求2所述的无外引脚封装结构，其中，该黏着层包含银胶、或是包含B阶胶层。
4.如权利要求1所述的无外引脚封装结构，其中，该第一导电线包含金线。
5.如权利要求1所述的无外引脚封装结构，其中，该第二导电线包含金线。
6.如权利要求1所述的无外引脚封装结构，其中，该芯片接地区环绕该凹槽。
7.如权利要求1所述的无外引脚封装结构，其中，该凹槽为一上窄下宽的凹槽。
8.一种无外引脚封装导线架，其特征在于，包含：
一芯片座，该芯片座具有一黏晶区、一凹槽及一芯片接地区，该凹槽设置于该黏晶区及该接地区之间；及
多个引脚，该等引脚环设于该芯片座周边。
9.如权利要求8所述的无外引脚封装导线架，其中，该芯片接地区环绕该凹槽。
10.如权利要求8所述的无外引脚封装导线架，其中，该凹槽具有一凹槽底面与一凹槽侧壁，该凹槽侧壁与该凹槽底面相连接，且该凹槽侧壁为一斜面。
11.如权利要求10所述的无外引脚封装导线架，其中，该凹槽侧壁与该凹槽底面定义一角度，且该角度小于90度。
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Cited By (5)

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Publication number Priority date Publication date Assignee Title
US7812432B2 (en) 2008-03-07 2010-10-12 Chipmos Technologies Inc. Chip package with a dam structure on a die pad
US7816750B2 (en) 2007-07-24 2010-10-19 Aptina Imaging Corporation Thin semiconductor die packages and associated systems and methods
CN101241890B (zh) * 2007-02-06 2012-05-23 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
TWI511207B (zh) * 2009-06-22 2015-12-01 Stats Chippac Ltd 具有底膠之積體電路封裝系統及其製造方法
US10074599B2 (en) 2007-07-24 2018-09-11 Micron Technology, Inc. Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6585905B1 (en) * 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
JP4068336B2 (ja) * 2001-11-30 2008-03-26 株式会社東芝 半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241890B (zh) * 2007-02-06 2012-05-23 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
US7816750B2 (en) 2007-07-24 2010-10-19 Aptina Imaging Corporation Thin semiconductor die packages and associated systems and methods
US10074599B2 (en) 2007-07-24 2018-09-11 Micron Technology, Inc. Semiconductor dies with recesses, associated leadframes, and associated systems and methods
US10431531B2 (en) 2007-07-24 2019-10-01 Micron Technology, Inc. Semiconductor dies with recesses, associated leadframes, and associated systems and methods
US7812432B2 (en) 2008-03-07 2010-10-12 Chipmos Technologies Inc. Chip package with a dam structure on a die pad
TWI511207B (zh) * 2009-06-22 2015-12-01 Stats Chippac Ltd 具有底膠之積體電路封裝系統及其製造方法

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