CN1741715A - 部件的表面组装安装 - Google Patents
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Abstract
本说明书描述了用于制造高器件密度的电路板的表面安装方法。在板上的部件的基准距间隔能通过选择性的省略或者选择性的去除在部件封装下的焊料掩模层而显著增大。这在清洗操作期间改善了清洗液到达部件下面的通道。
Description
技术领域
本发明涉及表面组装技术(SMT)和用于安装提高改善后焊料清洁的SMT部件的方法。
背景技术
用于电子设备的印刷电路板(PCBs)的制造方法随着部件尺寸的缩小和在支撑板上部件密度的增加经历了许多变化。熟知的具有穿孔引线的双列直插式封装(DIP)已经被从板的一侧安装和粘贴的表面组装技术(SMT)器件取代。SMT组装具有多种形式。许多用于杂化电路的地址安装分离部件。典型部件是电容、电阻、电感、LED、离散晶体管(discrete transistor)等等。结合了这些部件的子电路或子装配封装也通常被封装为SMT部件。例如,滤波器和其它RC电路经常被作为单个单元封装。具有大量数目的器件的集成电路器件,无源器件和有源晶体管,都使用SMT安装。
在连接部件到板表面中,焊料几乎是通用的连接媒介。这使得连接也用作电互连。在部件上的电触点焊接到板上的导电垫上。在部件上的电触点可以是无引线的,即,平坦预镀锡表面,或者可以是从部件封装延伸的引线。在有引线的芯片载体封装上的引线典型地具有明显的形状,如欧翼型、J形、I形。
焊接操作典型地产生了残留物和碎片。残留物通过焊接助熔剂产生,该助熔剂是酸性的、腐蚀性的,并包含产生电信号的离子成分。如果没有完全去除,这些残留物能导致产品可靠性问题。碎片可以包括焊料的小颗粒和/或在焊料回流步骤中形成的其它材料,其对已完成的器件同样是有害的。因此,SMT焊接操作通常以清洗步骤而结束,其中液体围绕已组装的器件循环。清洗液的流动也渗透到在部件和板之间的间隔中,该间隔经常包含有害的残留物和碎片。在部件底部和板或衬底之间的间隔以下称作基准距(stand-off)间隔,以及分开衬底表面和部件底部的距离称作基准距(stand-off)高度。在板或衬底上使用焊接掩模的SMT方法中,基准距高度由焊接掩模层的上表面和部件封装的下表面之间的垂直距离确定。在有引线的封装中,基准距间隔名义上被引线的尺寸和形状控制。在无引线的芯片载体和类似的封装中,基准距主要通过表面张力和在回流中的焊料倒塌(collapse)高度而确定。
随着板上的器件密度增加以满足用于小尺寸和小型封装的高度封装需求,基准距间隔(stand-off space)变得更加受限制。受限制的间隔更倾向于俘获残留物和碎片,并对于清洗液的流动来说是不可到达的。因此,其中基准距间隔是非常受限制的,清洗操作是无效的。
发明内容
基准距空间可以通过选择性地省略(omitting),或者选择性地去除在部件封装下的焊接掩模而被显著地放大。在部件封装下面的衬底上的其中部件被焊接的区域,这里指部件印记(footprint)。它典型地是正方形或长方形。通过选择性地在部件下省略焊接掩模,通过消耗已省略的焊接掩模的厚度增加了基准距高度。在人工SMT的状态下,基准距高度典型地是小的,并且焊接掩模的厚度是基准距高度中的很大一部分。
附图说明
当结合附图考虑时,可以更好地理解本发明,
其中图1是安装在电路板上的鸥翼型引线部件焊料的一部分的示意图,并说明了现有技术的俘获碎片的问题。
图2是更加具体地说明下述相关尺寸的示意图。
图3是与图1的视图类似的焊接安装无引线的表面安装部件的示意图,但说明了在SMT的另一形式中的俘获碎片的问题。
图4是与图1中的类似,但是用于球栅阵列(BGA)或倒装芯片SMT部件的示意图。
图5是安装了从部件下的区域省略了图1示出的焊料掩模的SMT焊接的示意图。
图6是说明当缺少部件下的焊料掩模时,图2的相关尺寸的效果的示意图。
图7是示出了用于图5和图8的断线的图5的部件的平面图。
图8是在图7中示出的图5中的SMT部件的截面图,示出了在基准距间隔中流动的清洗液。
图9是与图3中的具有从部件下的区省略的焊料掩模的类似的示意图。
图10是与图4中的具有从部件下的区省略的焊料掩模的类似的示意图。
图11是示出了仿真(phantom)的引线部件的现有技术焊料掩模的平面图。
图12是根据本发明的具有在缺失部件下的部分制造的焊料掩模的平面图。
图13是在应用焊锡膏后图12的截面图。
图14是在应用和回流焊锡膏后与图12类似的平面图。
图15是在焊料垫回流和放置SMT之后的SMT器件的高度(elevation)。
图16和17示出了提供到基准距间隔的增强通道的焊料掩模的变形。
图18和19示出了为基准距间隔提供增强通道的衬底形状的变形。
具体实施方式
参考图1,示出了具有鸥翼型引线12的引线部件11通过焊料缝脚14安装到衬底13上。与本发明描述相关的该结构以截面的形式示出(部件的内部特征没有示出)。衬底13,其可以是电路板如环氧树脂(例如FR4),以切除的方式示出了在图中示出的板仅仅是更大的电路板的一部分,或者典型的一小部分。在焊料缝脚(solder fillet)下面是导体垫15。导体垫与在板上互连多层部件的电路片槽(runner)集成。导体垫典型地是铜的,但也可以是铝或具有顶部板金属形式的其它金属以通过应用的焊料保证导体垫的湿润。
图1是通用SMT方法的代表,其中使用焊料掩模,这里以16表示,以选择性也限定在衬底上的焊料的位置。从焊接操作得到的碎片以18表示,被俘获在焊料掩模层16和部件11的底部之间的基准距间隔中。
可以理解图中的元件并没有必要是按比例的。例如,与其它尺寸相关的焊料掩模的厚度可以稍微地放大以说明本发明。
图2示出了图1的虚线部分,并更加详细地示出了基准距间隔。焊料掩模层的厚度在这个图中以t表示。基准距高度S主要由引线12的尺寸和形状决定。引线要么接触衬底13的表面,或者,如果部件非常小可以稍微浮置在衬底表面的上方。然而,与焊接位相关的实际上的基准距高度被衬底表面决定,并具有最大高度S。在实际操作中,然而,在部件11下方的基准距高度不是由衬底13的表面决定,而是由焊料掩模层16的表面决定。因此,在图2中的实际上的基准距高度是g。如更早所提及的方法,这个基准距高度随着器件尺寸的缩小而变得更小。图2示出了碎片18被牢固地俘获在缝隙g中。
图1和2示出了通常在基准距间隔中俘获或形成碎片或残留物的问题。当这里所示的部件是具有欧翼型引线的引线封装时,在多个分离部件和集成电路封装中更广泛地遇到了该问题。为了说明,图3示出了在无引线表面安装部件中的问题。所有的元件与图1中的相同,除了没有引线12。在表面安装部件下的基准距主要由在焊料回流期间焊料表面张力/表面塌陷特性决定。典型地镀锡部件(未示出)的末端以提高在部件和导体垫之间的湿润。图4是另一个SMT封装类型,其中使用焊料凸块或BGA球24用于粘贴器件11。典型地在BGA技术中的器件11是集成电路,以及球或互连的数量会非常大。
已知示出了碎片和残留物问题存在于多种SMT封装类型中,下面将详细描述与图1中的欧翼型封装有关的细节。
图5示出了具有从大约与部件印记相对应的区域省略的焊接掩模的图1的封装。焊料掩模16仍然保留在所示出的焊接位的周围。从部件印记中省略焊料掩模的效果在图6中是明显的,其中在部件11的底部和衬底之间的缝隙g与图2中示出的最大基准距相当,由此通过在后焊接清洗操作期间的清洗液流动显著地增强了基准距间隔的通道。
图5示出了通过部件11的引线12的截面,即沿着在图7中的“图5”表示的线的截面。在图8中示出了在引线之间的视图,由图7中的断线“图8”表示。清洗液的流动由箭头表示,并以31表示去除碎片。可以看出清洗液的流动并没有受到焊料掩模的阻碍。
图9示出了图3的实施例,SMT无引线芯片载体(LCC),具有从部件印记省略的焊料掩模,以及图10示出了图4的具有从印记省略的焊料掩模的实施例。在每个情形中,用于图5的描述的相同的效果是显然的。
在SMT技术中,焊料掩模层典型地是聚合物,例如聚酰亚胺、聚丙烯酸脂,或合适的替换物。更优选地,可以是可光成像的(photoimageable)聚合物。焊料掩模材料优选是沉积在衬底上的覆盖层,并使用光刻构图。在现有技术中已知多种光致抗蚀剂材料,并且这些材料的类型很容易通过公知或已发展很好的技术涂覆和构图。该层被掩模,曝光以显影。可选择地使用其它的方法,例如类似于丝网印刷的其它方法。图11示出了焊料掩模层41的平面图,根据现有技术构图,以覆盖除了焊接位42之外的衬底。在仿真(phantom)中用45表示部件轮廓(outline),在46处示出了部件引线。同样的,在仿真中示出了导体垫47。为了清楚,仅示出了一个导体垫,可以理解导体垫位于每个焊接位42之下。在引线之间的间隔可以比示出的更大,以允许在引线和导体垫之间的某些未对准。典型地制造导体垫比引线更大以使得欧翼型的基线完全留在垫上。在现有技术的SMT中,用于产生焊料掩模的光掩模类似于图11,具有与每个焊接位对应的开口的构图。
相反地,在图12中示出了用于实现本发明的具有开口51的大约相应于部件印记的焊料掩模。如所示提供了焊接位窗口52。
放置图12的焊料掩模,除了选择性地涂覆膏剂到焊接位窗口52以外以通用方法进行焊料粘贴操作,并在部件印记区域中省略。这在图13中进行了说明,其中焊料膏61被选择性地涂覆到焊接位窗口中。焊料膏的选择性的涂覆可以使用公知的模板(stencil)方法易于进行。提供具有用于焊接位的开口但在部件印记区域没有开口的模板。焊料膏然后回流以产生以在图14中以71示出的焊料凸块。适当的焊料凸块也可以通过其它的方法产生。例如,焊料可以通过阴影掩模(shadow mask)蒸发。
当焊料凸块形成时,设置具有与焊料凸块71对应的引线的部件11,如图15中所示,并且焊料回流以产生图5的装配(assembly)。然后进行如上所述的清洗操作。清洗液可以是任何公知的有机溶剂或清洁剂。
可以使用几个可选择的方法以进一步提高清洗液到达部件下的区域的通道。例如,认识到在图7中的部件11在四边的仅仅两个上具有引线,在焊料掩模的端部的开口间隔可以延伸以扩展到空的间隔中。在图16中示出了其中延伸的空区域51a产生了一个增大的部件印记以增加到达部件下的区域的通道。图17示出了实施例,其中在仿轮廓81中示出的部件在四边上都具有引线。使得在部件下的焊料掩模中的开口比部件印记的稍微大一些,另外,提供一个或者多个通道82以提高清洗液到部件下的区域的可到达性。
如所述能使用本发明制造多种SMT器件。也存在多种安装衬底。典型的PCB是环氧树脂板,例如FR4。它们可以是单层或多层。安装衬底也可以是陶瓷或硅。
在焊料掩模形成时,在省略在部件印记的区域中的焊料掩模的手段是本发明的一个简单的实施,其它步骤可以得到相同的结果。重要的是在清洗操作期间在部件下的焊料掩模可以没有。因此,在部件印记中的焊料掩模可以在单个的步骤中被蚀刻掉。如果利用涂刷器施加焊料膏,这个顺序是有用的,使得限定焊料膏以适合焊接位更加困难。在那样的情况下,可以形成传统的焊料掩模,焊料膏沉积并回流,然后去除焊料掩模的部件印记区域。存在一些公知的能选择性地蚀刻焊料掩模的有机溶剂。
在已经描述的本发明的几个实施例中,基准距间隔通过去除焊料掩模的部分而增加。一个替代方法是去除衬底的一部分,或成形衬底,由此提高基准距高度。在图18和19中示出了用于达到这个目的的两个实施例,在图18中,在部件印记下的衬底的顶表面的区域被选择形地蚀刻以在衬底上形成凹陷91。焊料掩模可以选择存在或者省略。基准距高度由于蚀刻凹陷的深度而被增大。可选择地,可以使用预先制造的凹陷而制造衬底。形成具有适当地位于板上的凹陷的电路板是直接的,特别是电路板是通过成型工艺典型地形成的时候。图19表示其中具有上升部分95成型的衬底的实施例。这些处于焊接位的位置并用于从板表面提高部件,由此达到提高基准距高度的目的。
对于本领域的技术人员可以产生本发明的多种其它的变形。来自本说明书的具体说明的所有变动基本上依赖于原则和它们的等价物,通过它们本技术可以在权利要求中描述的范围内被引申或正确地考虑。
Claims (19)
1、用于制造电器件的方法,包括:
a.提供互连衬底,该衬底具有顶表面和底表面,顶表面包括部件印记(footprint)区域,和多个焊接位。
b.在顶表面上形成焊接掩模层,该焊接掩模层具有:
i.围绕焊接位的多个开口,和
ii.围绕部件印记区域的至少一部分的至少一个开口,由此使得部件印记区域的至少一部分没有焊接掩模;
c.通过将电部件的一部分焊接到焊接位,而将电部件粘贴到衬底上,电部件具有邻近衬底和与衬底分开的底侧,由此在衬底的顶表面和部件的底侧之间留下了基准距(stand off)间隔。
d.通过将衬底暴露在清洗液中清洗衬底,该清洗步骤包括通过暴露基准距间隔到清洗液来清洗基准距间隔。
2、如权利要求1所述的方法,其中选择性地涂覆焊料膏到焊接位。
3、如权利要求1所述的方法,其中该部件是无引线器件。
4、如权利要求1所述的方法,其中该部件是引线器件。
5、如权利要求1所述的方法,其中在b.ii中的开口的尺寸超过了部件印记区域的尺寸。
6、如权利要求1所述的方法,其中焊料掩模通过在衬底上沉积可光成像的聚合物的覆盖层而形成,将覆盖层的各区域暴露到光下,然后去除暴露的区域,其中各暴露区域与b.i和b.ii相对应。
7、如权利要求2所述的方法,其中使用模板方法选择性地涂覆焊料膏。
8、如权利要求1所述的方法,其中该部件安装在衬底底侧上。
9、一种SMT器件,包括:
a.互连衬底,该衬底包括顶表面和底表面,顶表面包括部件印记区域,和多个焊接位;
b.在顶表面上的焊料掩模层,其具有:
i.围绕焊接位的多个开口,和
ii.围绕至少部件印记区域的一部分的至少一个开口,由此使得部件印记区域的至少一部分没有焊料掩模;
c.焊接到焊接位的电部件,该电部件具有邻接并从衬底分开的底侧,由此在衬底的顶表面和部件的底侧之间留下了基准距间隔。
10、如权利要求9的SMT器件,其中在b.ii的开口区域超过了部件印记区域的区域的尺寸。
11、如权利要求9的SMT器件,其中该器件是无引线芯片载体。
12、如权利要求9的SMT器件,其中该器件是引线器件。
13、如权利要求9的SMT器件,其中焊料掩模层包括可光成像聚合物。
14、如权利要求9的SMT器件,进一步包括在部件印记区域中衬底中的凹陷。
15、如权利要求9的SMT器件,其中该衬底是印刷电路板。
16、如权利要求15的SMT器件,其中该衬底是聚合物。
17、如权利要求9的SMT器件,其中该衬底是陶瓷。
18、如权利要求9的SMT器件,进一步包括在焊接位处的衬底的上升部分。
19、如权利要求9的SMT器件,其中进一步包括安装在衬底的底侧上的部件。
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US10/838,897 US20050247761A1 (en) | 2004-05-04 | 2004-05-04 | Surface mount attachment of components |
US10/838,897 | 2004-05-04 |
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CN1741715A true CN1741715A (zh) | 2006-03-01 |
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CNA2005100817920A Pending CN1741715A (zh) | 2004-05-04 | 2005-04-29 | 部件的表面组装安装 |
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EP (1) | EP1593450A1 (zh) |
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CN102834950A (zh) * | 2009-12-18 | 2012-12-19 | 克拉-坦科股份有限公司 | 用于维持组件的安全操作温度的组件封装 |
CN103913837A (zh) * | 2013-01-07 | 2014-07-09 | 精工爱普生株式会社 | 封装件、光学模块以及电子设备 |
US9165846B2 (en) | 2002-01-24 | 2015-10-20 | Kla-Tencor Corporation | Process condition sensing wafer and data analysis system |
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- 2005-05-02 JP JP2005134097A patent/JP2005322915A/ja not_active Withdrawn
- 2005-05-03 TW TW094114324A patent/TW200607422A/zh unknown
- 2005-05-03 EP EP05252728A patent/EP1593450A1/en not_active Withdrawn
- 2005-05-04 KR KR1020050037577A patent/KR20060047725A/ko not_active Application Discontinuation
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2007
- 2007-08-09 US US11/891,279 patent/US20080041620A1/en not_active Abandoned
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US9165846B2 (en) | 2002-01-24 | 2015-10-20 | Kla-Tencor Corporation | Process condition sensing wafer and data analysis system |
CN101990364B (zh) * | 2009-08-04 | 2012-05-09 | 纬创资通股份有限公司 | 组装组件至电路板的方法与相关电路板组装系统 |
CN102834950A (zh) * | 2009-12-18 | 2012-12-19 | 克拉-坦科股份有限公司 | 用于维持组件的安全操作温度的组件封装 |
CN102834950B (zh) * | 2009-12-18 | 2015-10-14 | 克拉-坦科股份有限公司 | 用于维持组件的安全操作温度的组件封装 |
CN103913837A (zh) * | 2013-01-07 | 2014-07-09 | 精工爱普生株式会社 | 封装件、光学模块以及电子设备 |
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US20050247761A1 (en) | 2005-11-10 |
US20080041620A1 (en) | 2008-02-21 |
KR20060047725A (ko) | 2006-05-18 |
EP1593450A1 (en) | 2005-11-09 |
TW200607422A (en) | 2006-02-16 |
JP2005322915A (ja) | 2005-11-17 |
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