CN1701425A - 具有低导通电阻的高电压功率mosfet - Google Patents

具有低导通电阻的高电压功率mosfet Download PDF

Info

Publication number
CN1701425A
CN1701425A CNA038043890A CN03804389A CN1701425A CN 1701425 A CN1701425 A CN 1701425A CN A038043890 A CNA038043890 A CN A038043890A CN 03804389 A CN03804389 A CN 03804389A CN 1701425 A CN1701425 A CN 1701425A
Authority
CN
China
Prior art keywords
epitaxial loayer
groove
tagma
polysilicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA038043890A
Other languages
English (en)
Other versions
CN100463122C (zh
Inventor
理查德·A·布朗夏尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Semiconductor Inc
Original Assignee
General Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Semiconductor Inc filed Critical General Semiconductor Inc
Publication of CN1701425A publication Critical patent/CN1701425A/zh
Application granted granted Critical
Publication of CN100463122C publication Critical patent/CN100463122C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供一种功率MOSFET，该MOSFET包括第一导电类型的衬底(2)。在衬底(2)上淀积也是第一导电类型的外延层(1)。在外延层(1)中设置第一和第二体区(5，6)并限定其间的漂移区。体区具有第二导电类型。在第一和第二体区(5，6)分别设置第一导电类型的第一和第二源区(7，8)。在外延层的漂移区中的体区下面设置多个沟槽。从第一和第二体区朝衬底延伸的沟槽填有薄氧化层和多晶半导体材料，例如，多晶硅，该材料包括第二导电类型的掺杂剂。薄氧化层溶入外延层，掺杂剂从沟槽扩散到邻近沟槽的部分外延层中，多晶半导体材料转变为单晶材料，由此形成使得反向电压在水平方向和垂直方向都增加的p－型掺杂区。

Description

具有低导通电阻的高电压功率MOSFET
相关申请的声明
本申请是2000年6月2日申请的、名称为“High Voltage PowerMOSFET Having Low On-Resistance(具有低导通电阻的高电压功率MOSFET)”的美国申请09/586,407的继续部分申请。
本申请与2001年5月4日申请的、名称为“High Voltage PowerMOSFET Having Low On-Resistance(具有低导通电阻的高电压功率MOSFET)”美国申请09/849,036相关。
技术领域
本发明一般涉及半导体器件，更具体涉及功率MOSFET器件。
背景技术
功率MOSFET器件用于如汽车电子系统、电源供给以及电源管理应用中。这种器件应该在断态保持高电压以及应该在通态提供低压降的强电流。
图1图示了N沟道功率MOSFET的典型结构。在N+硅衬底2上形成的N-外延硅层1包含用于器件中的两个MOSFET单元的p-体区5a和6a以及N+源区7和8。P-体区5和6还可以包括深p-体区5b和6b。源区-体区电极12延伸横穿外延层1的某些表面部分，以接触源区和体区。在图1中，通过延伸至上半导体表面的部分N-外延层1形成用于两个单元的N-型漏区。在N+衬底2的底部提供漏电极(未单独示出)。在部分源区和体区以及体区之间的漏区表面上设置包括如二氧化硅和多晶硅的介质的绝缘栅电极18。
图1所示的常规MOSFET的导通电阻很大程度上由外延层1中的漂移区阻抗决定。漂移区阻抗由外延层1的掺杂和层厚度决定。但是，为了增加器件的击穿电压，外延层1的掺杂浓度必须被减小，而层厚度必须被增加。图2中的曲线20示出了作为常规MOSFET的击穿电压函数的每单位面积的导通电阻。不幸地，如曲线20所示，随着其击穿电压增加，器件的导通电阻迅速地增加。当MOSFET在较高电压下工作时，尤其在大于几百伏的电压下工作时，阻抗的这种快速增加存在问题。
图3示出了设计为在较高电压下工作时具有减小的导通电阻的MOSFET。在1998年的IEDM的会议论文集第683页、文件号26.2中公开了这种MOSFET。除了该MOSFET包括从体区5和6底下延伸到器件的漂移区中的p-型掺杂区40和42之外，该MOSFET类似于图2所示的常规MOSFET。限定漂移区中的列的p-型掺杂区40和42被n-型掺杂列分开，该n-型掺杂列被邻近p-掺杂区40和42的部分外延层1限定。相反掺杂类型的交替列使得反向电压不仅在垂直方向上增加，如在常规MOSFET中，而且水平方向方向也增加。结果，该器件可以获得与常规器件相同的反向电压，减小了外延层1的层厚度并增加了漂移区中的掺杂浓度。图2中的曲线25示出了作为图3所示的MOSFET的击穿电压函数的每单位面积的导通电阻。显然，在较高工作电压下，该器件的导通电阻相对于图1中所示的器件实质上减小，随击穿电压基本上线性地增加。
图3所示器件的增强工作特性是基于晶体管的漂移区中的电荷补偿。亦即，通过增加相反掺杂类型的列，漂移区中的掺杂实质上增加例如一个数量级或更多，以及附加的电荷被平衡。因此晶体管的截止电压保持不变。当器件处于其导通状态时，相反掺杂类型电荷补偿列不会有助于电流导电。晶体管的这些希望的性能关键取决于在相反掺杂类型的相邻列之间实现的电荷补偿程度。不幸地，由于在它们的制造过程中限制工艺参数的控制，因此难以避免列的掺杂剂梯度的不均匀性。例如，穿过列和衬底之间的界面以及列和p-体区之间的界面的扩散将导致接近那些界面的部分列的掺杂剂浓度变化。
可以用包括多个外延淀积步骤工艺顺序制造图3中所示的结构，每个之后引入适当的掺杂剂。不幸地，执行外延淀积步骤是昂贵的，且因此制造这些结构是昂贵的。
由此，希望提供一种制造图3中所示的MOSFET结构的方法，该方法需要最小数量的外延淀积步骤，以便它可以廉价制造，而且还允许充分的控制工艺参数，以便在器件的漂移区中的相反掺杂类型的相邻列中可以实现高度的电荷补偿。
发明内容
根据本发明，提供一种功率MOSFET，包括第一导电类型的衬底。在衬底上淀积同样是第一导电类型的外延层。在外延层中设置第一和第二体区并限定它们之间的漂移区。该体区具有第二导电类型。分别在第一和第二体区中设置第一导电类型的第一和第二源区。在外延层的漂移区中的体区下面设置多个沟槽。从第一和第二体区朝衬底延伸的沟槽填有薄氧化层和多晶半导体材料(例如，多晶硅)，该材料包括第二导电类型的掺杂剂。薄氧化层溶入外延层中，掺杂剂从沟槽扩散到邻近沟槽的部分外延层中，多晶半导体材料变为单晶材料，因此形成使得反向电压在水平方向以及垂直方向都增加的p-型掺杂区。
根据本发明的另一方面，提供一种用于形成功率MOSFET的方法。该方法首先提供第一导电类型的衬底，以及在衬底上淀积外延层。外延层具有第一导电类型。在外延层中形成第一和第二体区，以限定其间的漂移区。该体区具有第二导电类型。在第一和第二体区中分别形成第一导电类型的第一和第二源区。在外延层的漂移区中形成多个沟槽。在沟槽中外延地淀积具有第二导电类型的掺杂剂的材料。沟槽从第一和第二体区朝着衬底延伸。在沟槽的壁和底部上形成二氧化硅层。在沟槽中淀积具有第二导电类型的掺杂剂的多晶半导体材料。通过加热使二氧化硅层溶入外延层。使至少部分掺杂剂从沟槽扩散到邻近沟槽的部分外延层中，多晶半导体材料变为单晶材料。
附图说明
图1示出了常规功率MOSFET结构的剖面图。
图2示出了作为常规功率MOSFET和根据本发明构成的MOSFET的击穿电压函数的每单位面积的导通电阻。
图3示出了设计为在与图1所描绘的结构相同的电压下工作时每单位面积具有更低的导通电阻的MOSFET结构。
图4-6示出了根据本发明构成的功率MOSFET的各个实施例的相关部分。
图7示出了根据本发明构成的完整功率MOSFET。
具体实施方式
根据本发明，通过首先刻蚀置于将设置p-型区40和42位置周围中心的一对沟槽，形成图3所示的p-型区40和42。接着用富掺杂剂材料填充沟槽。材料中的掺杂剂从沟槽向外扩散，并进入形成器件漂移区的相邻外延层。外延层的所得的掺杂部分形成p-型区。填充沟槽的材料连同没有从沟槽往外扩散的掺杂剂一起留在最终的器件中。由此，应该选择材料，以便它不会不利地影响器件的性能。可以用于填充沟槽的材料的示例性材料包括多晶硅或介质，如二氧化硅。
图4-6示出了可以用来填充在外延硅层1中形成的沟槽44和46的几种不同材料的组合。尽管图4-6示出了沟槽44和46、外延层1以及衬底2，为了清楚，图4-6没有示出包括P-体区和源区的功率MOSFET结构的上部。
在图4所示的本发明的实施例中，沟槽44和46填有掺杂介质，如硼掺杂的二氧化硅。在填充沟槽之后，硼扩散到相邻的外延层1中，以形成p-型区40和42。填充沟槽的硼掺杂二氧化硅留在最终的MOSFET器件中。
在图5所示的本发明的实施例中，用多晶硅，即掺有硼的多晶硅至少部分地填充沟槽。在填充沟槽之后，硼扩散到相邻的外延层1中，以形成p-型区40和42。填充沟槽的剩下的硼掺杂多晶硅留在最终的MOSFET器件中。可选地，在执行扩散步骤之后可以全部或部分地氧化多晶硅，以形成二氧化硅。由此，在最终MOSFET器件中剩下的沟槽填有介质，例如二氧化硅和任何剩余的多晶硅。在另一可选方案中，沟槽中的任意硼掺杂多晶硅在升温时再次结晶，以形成单晶硅。在此情况下，最终MOSFET器件中剩下的沟槽填有与二氧化硅或其它介质结合的单晶硅或单晶硅。
在其中采用多晶硅填充沟槽然后再结晶的本发明的那些实施例中，通过在淀积多晶硅之前在沟槽的壁和底部上形成二氧化硅薄层可以易于再结晶。以此方式，可以很好地控制随后在二氧化硅上淀积的多晶硅的晶粒尺寸。由此，当多晶硅再结晶时，给定时间和温度获得的结晶度大于不存在二氧化硅时可达到的结晶度。换句话说，二氧化硅通过很好地控制两种状态之间的过渡有助于影响多晶硅上的单晶结构。在适当的退火温度下再结晶多晶硅之前，通过提高温度可以有效地除去二氧化硅层，以便二氧化硅溶入外延层1的硅中(当然假定外延层具有低于其固溶度的氧浓度)。结果，多晶硅将与形成外延层1的单晶硅直接接触。由于多晶硅的退火温度超过约1050℃，以及二氧化硅溶于硅的温度超过约950℃，因此可以方便地同时执行退火和溶解步骤。
在图5所示的本发明的实施例中，首先用掺杂多晶硅部分地填充沟槽44和46，接着淀积介质以完全填充沟槽。在填充沟槽之后，硼扩散到相邻的外延层1中，以形成p-型区40和42。剩下的硼掺杂多晶硅和填充沟槽的介质留在最终的MOSFET器件中。有时在高温下再结晶硼掺杂的多晶硅，以形成单晶硅。由此，用单晶硅和介质填充最终的MOSFET器件中剩下的沟槽。
图7示出了根据本发明构成的最终功率MOSFET。该MOSFET包括衬底2、外延层1、p-体区5a和6a、深p-体区5b和6b、源区7和8、以及其中分别设置沟槽44和46的p-型区40和42。P-型区40和42限定由n-型掺杂列分开的列。还示出了包括氧化层48和多晶硅层49的栅电极以及包括金属层50的源区-体区电极。
在本发明的又一个实施例中，可以用外延地淀积的材料(如掺杂硅)填充沟槽44和46。在某些情况下可以有利地采用外延淀积，因为它减小缺陷形成和增强沟槽中的掺杂剂梯度的控制，以便可以实现更好的均匀性。如前面所述，掺杂剂梯度的控制是重要的，因为在较高工作电压下减小器件的导通电阻关键取决于在相反掺杂类型的相邻列之间实现的电荷补偿度。由此，尽管本发明的该实施例需要利用附加的外延淀积步骤，它可以有利地允许实现更好的电荷补偿。
可以根据任意常规处理技术制造图7中所示的本发明的功率MOSFET。例如，可以执行下面的一系列示例性步骤，以形成图7中描绘的功率MOSFET。
首先，通过用氧化层覆盖外延层1的表面形成氧化物掩模层，然后通常露出并构图氧化物掩模层，以留下限定沟槽44和46的位置的掩模部分。用反应离子刻蚀通过掩模开口干刻蚀沟槽至一般为10-40微米范围的深度。可以“平滑”每个沟槽的侧壁，以消除由反应离子刻蚀工艺引起的损坏。在沟槽44和46以及掩模部分上生长牺牲二氧化硅层。通过缓冲氧化刻蚀或HF刻蚀除去牺牲层和掩模部分，以致所得的沟槽侧壁尽可能平整。
用先前提及的任意材料(如多晶硅、二氧化硅、硅或其组合物)填充沟槽44和46。在淀积过程中，多晶硅或氧化物一般掺有掺杂剂，如硼。执行后续扩散步骤，以将掺杂剂扩散到沟槽外面并进入周围的外延层中。如果留在沟槽中的材料是多晶硅，那么它可以被氧化或再结晶。如前面所述，如果多晶硅再次结晶，那么在淀积多晶硅之前在沟槽中首先淀积二氧化硅薄层是有利的。
为了制造DMOS晶体管本身，首先形成厚场氧化物。接下来，掩模和刻蚀将接收掺杂剂或被栅极(有源区)覆盖的区域。生长栅氧化物，淀积、掩模并刻蚀多晶硅。
接下来，在注入硼之后，使用光刻胶掩模工艺形成限定体区5a和6a的构图掩模层。该顺序被重复，以形成深体区5b和6b。然后通过掩模、注入和扩散工艺形成源区7和8。例如，可以在80KeV下用砷注入源区至一般在2×1015至1.2×1016/cm2的浓度范围内。注入之后，砷扩散到约0.5至2.0微米的深度。深p-体区的深度一般约为2.5至5微米的范围，而体区的深度约为1-3微米的范围。然后用淀积的氧化物涂敷该结构。通过形成和构图氧化层形成接触开口以常规方式完成DMOS晶体管。此外淀积和掩模金属层50，以限定源区-体区和栅电极。此外，使用焊盘掩模限定焊盘接触。最后，在衬底的底表面上形成漏极接触层(未示出)。
应当注意，尽管在先前描述的工艺中，在形成p体区和深p-体区之前形成沟槽，但是本发明更通常包含其中在形成沟槽之前或形成任意或全部剩下的掺杂区之后的工序。此外，尽管公开了用于制造功率MOSFET的具体工艺顺序，但是也可以使用在本发明的范围内的其他工艺顺序。
根据本发明构成的功率MOSFET器件提供超过由常规技术构成的现有技术器件的许多优点。例如，p-型区的垂直掺杂剂梯度非常接近零。通过改变引入的掺杂剂量以及扩散步骤中使用的热周期数目和持续时间可以精确地控制水平掺杂剂梯度。而且，可以改变引入的掺杂剂量和横向掺杂剂梯度，以优化器件的击穿电压和导通电阻。
在图7所示的本发明的实施例中，在体区下面形成p-型沟槽。但是，不是每个p-型沟槽需要具有与之相关的体区，特别在管芯的周边或包含焊盘或互连的区域中。
尽管在此具体地图示和描述了各种实施例，应当理解，在不脱离本发明的精神和想要的范围条件下对本发明的改进和改变都被上述教导所覆盖且落在所附权利要求的范围内。例如，根据本发明的功率MOSFET中各个半导体区的导电性可以与在此描述的相反。此外，尽管在此描述的本发明存在至少两个体区，两个源区以及两个沟槽，但是根据MOS栅器件的具体几何形状也可以制造具有一个或多个这些区域的器件。

Claims (13)

1、一种形成高电压MOSFET的方法，包括下列步骤：
提供第一导电类型的衬底；
在衬底上淀积外延层，所述的外延层具有第一导电类型；
在外延层中形成一个或多个体区，以限定其间的漂移区，所述的体区具有第二导电类型；
在体区中形成第一导电类型的一个或多个源区；以及
在外延层的所述漂移区形成一个或多个沟槽，所述的沟槽从体区朝着衬底延伸；
在所述沟槽的表面上形成二氧化硅层；
在所述沟槽中的二氧化硅上淀积掺有第二导电类型的掺杂剂的多晶硅，以填充所述的沟槽；
使至少部分所述的掺杂剂从所述的沟槽扩散到邻近沟槽的部分外延层中；以及
再结晶至少部分所述的多晶硅，以形成单晶硅。
2、根据权利要求1所述的方法，其中，再结晶所述多晶硅的步骤包括退火所述多晶硅的步骤。
3、根据权利要求1所述的方法，其中，所述外延层具有在溶解温度时低于其固溶度的氧浓度以及还包括将二氧化硅溶入所述外延层中的步骤。
4、根据权利要求2所述的方法，其中，所述外延层具有在溶解温度时低于其固溶度的氧浓度以及还包括将二氧化硅溶入所述外延层中的步骤。
5、根据权利要求4所述的方法，其中，在高温下执行溶解步骤。
6、根据权利要求5所述的方法，其中，基本同时执行溶解步骤和退火步骤。
7、根据权利要求5所述的方法，其中，溶解步骤在退火步骤之前。
8、根据权利要求2所述的方法，其中，退火步骤基本上再结晶所有的多晶硅。
9、根据权利要求1所述的方法，其中，所述的体区包括深体区。
10、根据权利要求1所述的方法，其中，通过提供限定至少一个沟槽的掩模层以及刻蚀由掩模层限定的沟槽而形成所述的沟槽。
11、根据权利要求1所述的方法，其中，通过注入和扩散掺杂剂到衬底中而形成所述的体区。
12、一种根据权利要求1所述的方法制造的高电压MOSFET。
13、一种根据权利要求4所述的方法制造的高电压MOSFET。
CNB038043890A 2002-02-20 2003-02-20 具有低导通电阻的高电压功率mosfet Expired - Fee Related CN100463122C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/079,945 US6660571B2 (en) 2000-06-02 2002-02-20 High voltage power MOSFET having low on-resistance
US10/079,945 2002-02-20

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN2009100018860A Division CN101567384B (zh) 2002-02-20 2003-02-20 具有低导通电阻的高电压功率mosfet

Publications (2)

Publication Number Publication Date
CN1701425A true CN1701425A (zh) 2005-11-23
CN100463122C CN100463122C (zh) 2009-02-18

Family

ID=27752793

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2009100018860A Expired - Fee Related CN101567384B (zh) 2002-02-20 2003-02-20 具有低导通电阻的高电压功率mosfet
CNB038043890A Expired - Fee Related CN100463122C (zh) 2002-02-20 2003-02-20 具有低导通电阻的高电压功率mosfet

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2009100018860A Expired - Fee Related CN101567384B (zh) 2002-02-20 2003-02-20 具有低导通电阻的高电压功率mosfet

Country Status (8)

Country Link
US (1) US6660571B2 (zh)
EP (1) EP1476895B1 (zh)
JP (1) JP4511190B2 (zh)
KR (1) KR100965962B1 (zh)
CN (2) CN101567384B (zh)
AU (1) AU2003219831A1 (zh)
TW (1) TWI265633B (zh)
WO (1) WO2003071585A2 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958283A (zh) * 2009-07-09 2011-01-26 上海华虹Nec电子有限公司 获得交替排列的p型和n型半导体薄层结构的方法及结构
CN101459093B (zh) * 2007-12-10 2011-09-28 上海华虹Nec电子有限公司 验证非对称高压场效应管漂移区电阻的方法
CN103247533A (zh) * 2012-02-02 2013-08-14 茂达电子股份有限公司 功率晶体管组件的制作方法
CN101645448B (zh) * 2008-08-06 2013-11-13 飞兆半导体公司 用于在沟槽下形成pn嵌位区的结构和方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7694188B2 (en) * 2007-02-05 2010-04-06 Microsoft Corporation Disk failure prevention and error correction
CN101834208A (zh) * 2010-04-30 2010-09-15 苏州硅能半导体科技股份有限公司 一种低导通电阻的功率mos场效应管及制造方法
JP5621441B2 (ja) * 2010-09-14 2014-11-12 株式会社デンソー 半導体装置の製造方法
CN102760662B (zh) * 2011-04-29 2014-12-31 茂达电子股份有限公司 半导体功率装置的制作方法
TWI441261B (zh) * 2011-05-13 2014-06-11 Anpec Electronics Corp 半導體功率元件的製作方法
CN102214582B (zh) * 2011-05-26 2013-07-10 上海先进半导体制造股份有限公司 用于深槽超结mos器件的终端结构的制作方法
US8698229B2 (en) * 2011-05-31 2014-04-15 Infineon Technologies Austria Ag Transistor with controllable compensation regions
US8803205B2 (en) * 2011-05-31 2014-08-12 Infineon Technologies Austria Ag Transistor with controllable compensation regions
JP2017055102A (ja) * 2015-09-10 2017-03-16 株式会社豊田自動織機 トレンチゲート型半導体装置及びその製造方法
CN106298946A (zh) * 2016-10-09 2017-01-04 无锡新洁能股份有限公司 一种降低低压Trench DMOS导通电阻的制造方法
EP3590138B1 (en) 2017-03-03 2020-09-16 ABB Power Grids Switzerland AG Silicon carbide superjunction power semiconductor device and method for manufacturing the same
DE102018113145B4 (de) * 2018-06-01 2020-06-04 Infineon Technologies Ag Gleichrichtereinrichtung
TWI671912B (zh) * 2018-08-23 2019-09-11 立錡科技股份有限公司 能降低導通電阻之mos元件及其製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191396B1 (en) 1978-10-13 1995-12-26 Int Rectifier Corp High power mosfet with low on-resistance and high breakdown voltage
GB2089119A (en) 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
JPS6262516A (ja) * 1985-09-13 1987-03-19 Hitachi Ltd 不純物拡散方法
JPS63186423A (ja) * 1987-01-29 1988-08-02 Toshiba Corp 半導体装置の製造方法
US5404040A (en) 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
JPH04276628A (ja) * 1991-03-05 1992-10-01 Olympus Optical Co Ltd 半導体装置の製造方法
CN1019720B (zh) 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
JPH07220987A (ja) * 1994-01-28 1995-08-18 Nippon Telegr & Teleph Corp <Ntt> 単結晶Ｓｉ基板とその製造方法
JPH08264772A (ja) 1995-03-23 1996-10-11 Toyota Motor Corp 電界効果型半導体素子
DE59707158D1 (de) * 1996-02-05 2002-06-06 Infineon Technologies Ag Durch feldeffekt steuerbares halbleiterbauelement
DE19611045C1 (de) 1996-03-20 1997-05-22 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
DE19748523C2 (de) 1997-11-03 1999-10-07 Siemens Ag Halbleiterbauelement, Verfahren zum Herstellen eines derartigen Halbleiterbauelementes und Verwendung des Verfahrens
EP1029358A1 (de) 1997-11-03 2000-08-23 Infineon Technologies AG Hochspannungsfeste randstruktur für halbleiterbauelemente
EP0973203A3 (de) 1998-07-17 2001-02-14 Infineon Technologies AG Halbleiterschicht mit lateral veränderlicher Dotierung und Verfahren zu dessen Herstellung
US6452230B1 (en) * 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
KR100773380B1 (ko) * 1999-06-03 2007-11-06 제네럴 세미컨덕터, 인코포레이티드 전력 ｍｏｓｆｅｔ, 이를 형성하는 방법, 및 이 방법에 의해 형성되는 다른 전력 ｍｏｓｆｅｔ
JP2001345444A (ja) * 1999-10-25 2001-12-14 Seiko Instruments Inc 半導体装置とその製造方法
US6479352B2 (en) * 2000-06-02 2002-11-12 General Semiconductor, Inc. Method of fabricating high voltage power MOSFET having low on-resistance
US20050216275A1 (en) * 2004-03-24 2005-09-29 Heng-Chien Chen Telephone apparatus for making telephone calls in conjunction with a computing device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459093B (zh) * 2007-12-10 2011-09-28 上海华虹Nec电子有限公司 验证非对称高压场效应管漂移区电阻的方法
CN101645448B (zh) * 2008-08-06 2013-11-13 飞兆半导体公司 用于在沟槽下形成pn嵌位区的结构和方法
CN101958283A (zh) * 2009-07-09 2011-01-26 上海华虹Nec电子有限公司 获得交替排列的p型和n型半导体薄层结构的方法及结构
CN103247533A (zh) * 2012-02-02 2013-08-14 茂达电子股份有限公司 功率晶体管组件的制作方法

Also Published As

Publication number Publication date
EP1476895A4 (en) 2009-07-15
KR100965962B1 (ko) 2010-06-24
AU2003219831A8 (en) 2003-09-09
WO2003071585A3 (en) 2003-11-06
JP2005518663A (ja) 2005-06-23
CN100463122C (zh) 2009-02-18
WO2003071585A2 (en) 2003-08-28
CN101567384A (zh) 2009-10-28
US20020140025A1 (en) 2002-10-03
US6660571B2 (en) 2003-12-09
JP4511190B2 (ja) 2010-07-28
EP1476895A2 (en) 2004-11-17
TWI265633B (en) 2006-11-01
TW200305285A (en) 2003-10-16
AU2003219831A1 (en) 2003-09-09
KR20040079445A (ko) 2004-09-14
CN101567384B (zh) 2012-07-04
EP1476895B1 (en) 2017-07-12

Similar Documents

Publication Publication Date Title
CN1171318C (zh) 具有低导通电阻的高压功率金属氧化物半导体场效应晶体管
KR100830932B1 (ko) 전력 ｍｏｓｆｅｔ 및 전력 ｍｏｓｆｅｔ 제작 방법
CN1305122C (zh) 具有浮岛电压维持层的功率半导体器件的制造方法
CN100463122C (zh) 具有低导通电阻的高电压功率mosfet
CN100342544C (zh) 含有掺杂柱的高压功率mosfet
TW200305970A (en) Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
EP3651202B1 (en) Semiconductor device with superjunction and oxygen inserted si-layers
CN1812129A (zh) 半导体器件及其制造方法
KR20040037243A (ko) 부유 아일랜드의 형성을 용이하게 하는 층단으로 된트렌치를 갖는 전압 지속 층을 구비하는 전력 반도체디바이스의 제조 방법
CN109686781B (zh) 一种多次外延的超结器件制作方法
CN109713029B (zh) 一种改善反向恢复特性的多次外延超结器件制作方法
KR100292718B1 (ko) 반도체 장치 및 그 제조방법
CN1941414B (zh) 功率mos场效应管及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090218

Termination date: 20160220

CF01 Termination of patent right due to non-payment of annual fee