CN103247533A - 功率晶体管组件的制作方法 - Google Patents
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Abstract
本发明公开了一种功率晶体管组件的制作方法,其包含有下列步骤。首先,提供一半导体基底,半导体基底具有一扩散掺杂区设于其中,且扩散掺杂区与半导体基底的表面相接触,其中扩散掺杂区邻近表面的掺杂浓度大于扩散掺杂区远离表面的掺杂浓度。然后,进行一热氧化制程,于半导体基底的表面形成一氧化层,其中与表面相接触的扩散掺杂区的一部分与氧反应为氧化层的一部分。接着,移除氧化层。借此,可解决功率晶体管中超级结结构的电洞浓度与电子浓度分布不均匀的问题。
Description
技术领域
本发明涉及一种功率晶体管组件的制作方法。
背景技术
在功率晶体管组件中,漏极与源极间导通电阻RDS(on)的大小与组件的功率消耗成正比,因此降低导通电阻RDS(on)的大小可减少功率晶体管组件所消耗的功率。于导通电阻RDS(on)中,用于耐压的外延层所造成的电阻值所占的比例为最高。虽然增加外延层中导电物质的掺杂浓度可降低外延层的电阻值,但外延层的作用是用于承受高电压。若增加掺杂浓度会降低外延层的崩溃电压,因而降低功率晶体管组件的耐压能力。
为了维持或提升功率晶体管组件的耐压能力,并降低外延层的电阻值,目前已发展出一种具有超级结(super junction)结构的功率晶体管组件,以兼具高耐压能力以及低导通电阻。习知制作功率晶体管组件的方法是在N型基底上形成一N型外延层,然后利用蚀刻制程于N型外延层中形成多个深沟槽。接着,在深沟槽中填入掺杂物来源层,并利用高温扩散的方法将掺杂物来源层中的P型掺杂物扩散至N型外延层中,以形成P型掺杂区,且N型外延层与P型掺杂区构成垂直基底的PN接面,即超级结结构。然而,P型掺杂区是利用扩散方式所形成,因此其掺杂浓度是随着越接近深沟槽的侧壁而越高。借此,P型掺杂区的表面掺杂浓度容易过高,使超级结结构中的电洞浓度与电子浓度分布不均匀,导致超级结结构的耐压能力不佳。
有鉴于此,降低P型掺杂区的表面掺杂浓度,以解决超级结结构中的电洞浓度与电子浓度分布不均匀的问题实为业界努力的目标。
发明内容
本发明的主要目的在提供一种降低扩散掺杂区的表面掺杂浓度的方法、超级结结构的制作方法以及功率晶体管组件的制作方法,以解决超级结结构中的电洞浓度与电子浓度分布不均匀的问题。
为达上述的目的,本发明提供一种超级结结构的制作方法。首先,提供一半导体基底,具有一第一导电类型。接着,在半导体基底中形成至少一沟槽。然后,在沟槽的两侧的半导体基底中分别形成两扩散掺杂区,其中各扩散掺杂区邻近沟槽的侧壁的掺杂浓度大于各扩散掺杂区远离沟槽的侧壁的掺杂浓度,且各扩散掺杂区具有不同于第一导电类型的一第二导电类型。随后,进行一热氧化制程,在沟槽的侧壁以及底部形成一氧化层,其中与沟槽的侧壁相接触的各扩散掺杂区的一部分与氧反应为氧化层的一部分。然后,移除氧化层。
为达上述的目的,本发明提供一种功率晶体管组件的制作方法。首先,提供一半导体基底,具有一第一导电类型。接着,在半导体基底中形成至少一沟槽。然后,在沟槽的两侧的半导体基底中分别形成两扩散掺杂区,其中各扩散掺杂区邻近沟槽侧壁的掺杂浓度大于各扩散掺杂区远离沟槽侧壁的掺杂浓度,且各扩散掺杂区具有不同于第一导电类型的一第二导电类型。随后,进行一热氧化制程,在沟槽的侧壁以及底部形成一氧化层,其中与沟槽的侧壁相接触的各扩散掺杂区的一部分与氧反应为氧化层的一部分。然后,移除氧化层。接着,在沟槽中形成一绝缘层。之后,在沟槽的至少一侧的半导体基底上形成一栅极结构。随后,在栅极结构的两侧的半导体基底中分别形成两基体掺杂区,且各基体掺杂区分别与各扩散掺杂区相接触,其中基体掺杂区具有第二导电类型。接着,于各基体掺杂区中分别形成一源极掺杂区。
为达上述的目的,本发明提供一种降低扩散掺杂区的表面掺杂浓度的方法。首先,提供一半导体基底,半导体基底具有一扩散掺杂区设于其中,且扩散掺杂区与半导体基底的一表面相接触,其中扩散掺杂区邻近表面的掺杂浓度大于扩散掺杂区远离表面的掺杂浓度。然后,进行一热氧化制程,在半导体基底的表面形成一氧化层,其中与表面相接触的扩散掺杂区的一部分与氧反应为氧化层的一部分。接着,移除氧化层。
本发明利用热氧化制程,使具有较高浓度的各扩散掺杂区与氧反应而成为氧化层,借此后续进行将氧化层移除的步骤会将具有较高浓度的扩散掺杂区的一部分移除,因此所留下的各扩散掺杂区的表面掺杂浓度可有效地被降低,以均匀化超级结结构中的电洞浓度与电子浓度,进而提升超级结结构的耐压能力。
附图说明
图1到图3为本发明一优选实施例的降低扩散掺杂区的表面掺杂浓度的方法示意图。
图4到图13为本发明一优选实施例的功率晶体管组件的制作方法示意图。
图14与图15为本发明另一优选实施例的超级结结构的制作方法。
其中,附图标记说明如下:
10半导体基底 10a 上表面
12扩散掺杂区 14氧化层
100功率晶体管组件 102半导体基底
102a基材 102b外延层
104垫层 106硬掩模层
108开口 110沟槽
112掺杂物来源层 114扩散掺杂区
116氧化层 118绝缘层
120栅极绝缘层 122栅极导电层
124栅极结构 126基体掺杂区
128源极掺杂区 130介电层
130a接触洞 132接触掺杂区
134阻障层 136源极金属层
138漏极金属层 W1第一宽度
W2第二宽度
具体实施方式
请参考图1到图3,图1到图3为本发明一优选实施例的降低扩散掺杂区的表面掺杂浓度的方法示意图。如图1所示,首先,提供一半导体基底10,例如硅晶圆。半导体基底10具有一扩散掺杂区12设于其中,且扩散掺杂区12与半导体基底10的一上表面10a相接触。并且,扩散掺杂区12邻近上表面10a的掺杂浓度大于扩散掺杂区12远离上表面10a的掺杂浓度。如图2所示,随后,进行一热氧化制程,于半导体基底10的上表面10a形成一氧化层14。并且,与上表面10a相接触的扩散掺杂区12的一部分会与氧反应为氧化层14的一部分,也就是邻近上表面10a且具有较高浓度的扩散掺杂区12的一部分会因与氧反应而成为氧化层14。如图3所示,接着,移除氧化层14,也就是移除具有较高浓度且与氧反应而成为氧化层14的扩散掺杂区12的一部分,借此扩散掺杂区12的表面掺杂浓度可有效地被降低。于本实施例中,扩散掺杂区12的导电类型与半导体基底10的导电类型可为N型或P型,且可彼此相同或彼此不同。
本发明进一步将上述降低扩散掺杂区的表面掺杂浓度的方法应用于功率晶体管组件的超级结结构的制作方法中,以降低超级结结构中的电洞浓度或电子浓度,进而均匀化超级结结构中的电洞浓度与电子浓度,但本发明的降低扩散掺杂区的表面掺杂浓度的方法并不限应用于此。请参考图4到图13,图4到图13为本发明一优选实施例的功率晶体管组件的制作方法示意图,其中图4到图7为本发明优选实施例的超级结结构的制作方法示意图。如图4所示,首先,提供一半导体基底102,且半导体基底102具有一第一导电类型。接着,在半导体基底102上形成一垫层104,例如二氧化硅(SiO2),但不限于此。然后,进行一沉积制程,在垫层104上形成一硬掩模层106,例如氮化硅(Si3N4),但不限于此。接着,进行一微影暨蚀刻制程,图案化垫层104与硬掩模层106,在垫层104与硬掩模层106中形成多个开口108,分别贯穿垫层104与硬掩模层106并暴露出半导体基底102。然后,以硬掩模层106为掩模,进行一蚀刻制程,通过各开口108在半导体基底102中形成多个沟槽110,此时各沟槽110具有一第一宽度W1与各开口的宽度约略相同。在本实施例中,半导体基底102可包括一基材102a,例如硅晶圆,以及一外延层102b,且外延层102b设于基材102a上。并且,各沟槽110贯穿外延层102b,并暴露出基材102a,但本发明不限于此,各沟槽110也可未贯穿外延层102b。此外,本发明的开口108与沟槽110的数量不限为多个,也可分别仅为单一个。
如图5所示,接着,在各沟槽110中填入一掺杂物来源层112,且掺杂物来源层112覆盖于硬掩模层106上。其中,掺杂物来源层112包含有多个具有不同于第一导电类型的一第二导电类型的掺杂物。然后,进行一热趋入制程,将第二导电类型的掺杂物扩散至半导体基底102中,以在各沟槽110的两侧的半导体基底102中分别形成两扩散掺杂区114。由于各扩散掺杂区114是通过热来扩散掺杂物而形成的,因此各扩散掺杂区114也具有第二导电类型,且各扩散掺杂区114的掺杂浓度分布会随着越接近掺杂物来源层112而具有较高的掺杂浓度。也就是,各扩散掺杂区114邻近各沟槽侧壁的掺杂浓度大于各扩散掺杂区114远离各沟槽侧壁的掺杂浓度。在本实施例中,第一导电类型为N型,且第二导电类型为P型,但不限于此,本发明的第一导电类型与第二导电类型也可互换。并且,形成掺杂物来源层112的材料包含有硼硅玻璃(Boron silicate glass,BSG),但不限于此,本发明的掺杂物来源层112的材料可根据所欲形成的扩散掺杂区114的导电类型来决定。在本发明的共它实施例中,形成P型扩散掺杂区的方法也可利用P型离子布植制程,在N型半导体基底中植入P型离子,然后进行热趋入制程来形成P型扩散掺杂区,但不以此为限。
如图6所示,然后,进行另一蚀刻制程,移除掺杂物来源层112。随后,进行一热氧化制程,在各沟槽110的侧壁以及底部形成一氧化层116。由于各P型扩散掺杂区114是通过于含硅的N型半导体基底102中掺杂P型掺杂物而形成,因此各P型扩散掺杂区114包含硅。并且,各P型扩散掺杂区114的一部分与各沟槽110的各侧壁相接触而被暴露出,因此暴露出的各P型扩散掺杂区114的一部分会与氧反应,而成为氧化层116的一部分。换句话说,邻近各沟槽的侧壁且具有较高浓度的各P型扩散掺杂区114的一部分会因与氧反应而成为氧化层116。在本实施例中,氧化层116的厚度可约略介于10埃(angstrom)与10000埃之间,但本发明不以此为限。并且,热氧化制程所通入的一气体可包括水气(H2O)、氧气(O2)、氯化氢(HCl)与水气的混合气体、氯化氢与氧气的混合气体、氮气(N2)与水气的混合气体或氮气与氧气的混合气体。热氧化制程的一温度范围可介于800℃与1200℃之间,且其压力范围可约略介于600托耳(Torr)至760托耳之间。但本发明的热氧化制程的条件并不以上述为限。
如图7所示,接着,移除氧化层116,也就是移除具有较高浓度且与氧反应而成为氧化层116的各P型扩散掺杂区114的一部分,并暴露出具有较低掺杂浓度的各P型扩散掺杂区114。至此,所形成的各P型扩散掺杂区114与N型半导体基底102分别形成一PN接面,约略垂直N型半导体基底102,也就是本实施例的超级结结构。在本实施例中,移除氧化层116的步骤包括一湿式蚀刻制程,以移除位于硬掩模层106下方的氧化层116,但不限于此。并且,由于各P型扩散掺杂区114的一部分会被移除,因此各沟槽110在移除氧化层116的步骤之后会具有一第二宽度W2,且第二宽度W2大于各开口108的宽度。值得注意的是,由于具有较高浓度的各P型扩散掺杂区114会与氧反应而成为氧化层116,且在移除氧化层116的步骤会被移除,因此所留下的各P型扩散掺杂区114的表面掺杂浓度可有效地被降低,以均匀化超级结结构中的电洞浓度与电子浓度,进而提升超级结结构的耐压能力。
如图8所示,然后,进行另一沉积制程,在硬掩模层106上形成一绝缘材料层,例如:氧化硅,且绝缘材料层填满于各沟槽110中。然后,进行一化学机械研磨(Chemical Mechanical Polishing,CMP)制程,移除位于硬掩模层106上的绝缘材料层。接着,进行另一蚀刻制程,移除位于开口108中的绝缘材料层,以在各沟槽110中形成一绝缘层118。在本实施例中,绝缘层118的上表面约略与垫层104的上表面位于同一平面,但本发明并不限于此,绝缘层118的上表面也可介于垫层104的上表面与N型半导体基底102的上表面之间,或与N型半导体基底102的上表面位于同一平面。
如图9所示,随后,移除硬掩模层106与垫层104,并暴露出N型半导体基底102。接着,进行另一热氧化制程,在N型半导体基底102上形成一栅极绝缘层120。然后,于栅极绝缘层120与绝缘层118上覆盖一导电材料层,例如多晶硅。随后,进行另一微影暨蚀刻制程,图案化导电材料层,以在两相邻沟槽110之间的N型半导体基底102上分别形成一栅极导电层122,作为功率晶体管组件的栅极,且各栅极导电层122与位于各栅极导电层122以及N型半导体基底102之间的栅极绝缘层120构成一栅极结构124。在本实施例中,栅极绝缘层120的上表面约略与绝缘层118的上表面位于同一平面,但不限于此。在本发明的其它实施例中,栅极结构也可仅为单一个,而可于其中一沟槽110的一侧的N型半导体基底102上形成栅极结构124。
如图10所示,接着,以栅极导电层122为掩模,进行一P型离子布值制程以及另一热趋入制程,在各栅极结构124的两侧的N型半导体基底102中分别形成两P型基体掺杂区126,且各P型基体掺杂区126与各P型扩散掺杂区114相接触,并与各栅极结构124部分重叠,以作为功率晶体管组件的基极。
如图11所示,然后,利用一掩模(图未示),进行一N型离子布值制程以及另一热趋入制程,在各P型基体掺杂区126中形成一N型源极掺杂区128,分别与各栅极结构124部分重叠,以作为功率晶体管组件的源极。本发明的栅极结构124、P型基体掺杂区126以及N型源极掺杂区128并不限分别具有多个,且也可仅具有单一个,并可依据实际需求来作相对应调整。
如图12所示,接着,在栅极结构124以及绝缘层118上覆盖一介电层130,例如氧化硅。然后,进行另一微影暨蚀刻制程,在介电层130中形成多个接触洞130a,并移除部分栅极绝缘层120以及绝缘层118。各接触洞130a暴露出N型源极掺杂区128与P型基体掺杂区126。接着,进行另一P型离子布植制程与另一热趋入制程,以在各P型基体掺杂区126中形成一P型接触掺杂区132。
如图13所示,然后,进行另一沉积制程,在介电层130上与接触洞130a的侧壁与底部覆盖一阻障层134,例如钛或氮化钛。接着,在阻障层上形成一源极金属层136,且源极金属层136填满接触洞130a,并覆盖于介电层130上。并且,在N型半导体基底102下形成一漏极金属层138。至此已完成本实施例的功率晶体管组件100。在本实施例中,形成源极金属层136与漏极金属层138的步骤可分别包含进行等离子溅镀或电子束沉积等制程,且源极金属层136与漏极金属层138可分别包括钛、氮化钛、铝、钨等金属或金属化合物,但不限于此。
本发明的功率晶体管组件的超级结结构的制作方法并不以上述实施例为限。下文将继续揭示本发明的其它实施例或变化形,然为了简化说明并突显各实施例或变化形之间的差异,下文中使用相同标号标注相同组件,并不再对重复部分作赘述。
请参考图14与图15,且一并参考图4到图7。图14与图15为本发明另一优选实施例的超级结结构的制作方法。相较于上述实施例,本实施例的制作方法还在移除掺杂物来源层的步骤与形成氧化层的热氧化制程之间依序进行填入另一掺杂物来源层的步骤、另一热趋入制程以及移除另一掺杂物来源层的步骤至少一次,以用于调整P型扩散掺杂区的掺杂浓度,进而达到所欲的掺杂浓度。本实施例的制作方法在形成P型扩散掺杂区的步骤之前与上述实施例相同,如图4到图5所示。接着,如图14所示,移除掺杂物来源层112,然后填入另一掺杂物来源层202。在本实施例中,掺杂物来源层202是与上述实施例的掺杂物来源层112相同,例如硼硅玻璃(Boron silicate glass,BSG),且也具有多个P型掺杂物,但本发明不限于此。随后,进行另一热趋入制程,将P型掺杂物扩散至P型扩散掺杂区114中,以增加P型扩散掺杂区114的掺杂浓度。然后,如图15所示,移除掺杂物来源层202。本实施例的后续步骤与上述实施例相同,如图6与图7所示,因此不再在此赘述。在本发明的其它实施例中,为了调整P型扩散掺杂区114的掺杂浓度,以达到所欲的掺杂浓度,也可重复进行填入另一掺杂物来源层202的步骤、另一热趋入制程以及移除另一掺杂物来源层202的步骤多次。
在本发明的其它实施例中,也可通过重复依序进行填入另一掺杂物来源层的步骤、另一热趋入制程、移除另一掺杂物来源层的步骤、热氧化制程以及移除氧化层的步骤多次,来达到所欲的P型扩散掺杂区的掺杂浓度,进而制作出所欲的超级结结构。
综上所述,本发明利用热氧化制程,使邻近各沟槽的侧壁且具有较高浓度的各扩散掺杂区与氧反应而成为氧化层,借此后续进行将氧化层移除的步骤会将具有较高浓度的扩散掺杂区的一部分移除,因此所留下的各扩散掺杂区的表面掺杂浓度可有效地被降低,以均匀化超级结结构中的电洞浓度与电子浓度,进而提升超级结结构的耐压能力。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。凡在本发明的精神和原则的内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围的内。
Claims (20)
1.一种超级结结构的制作方法,其特征在于,包括:
提供一半导体基底,具有一第一导电类型;
于所述半导体基底中形成至少一沟槽;
在所述沟槽两侧的所述半导体基底中分别形成两扩散掺杂区,其中各所述扩散掺杂区邻近所述沟槽侧壁的掺杂浓度大于各所述扩散掺杂区远离所述沟槽侧壁的掺杂浓度,且各所述扩散掺杂区具有不同于所述第一导电类型的一第二导电类型;
进行一热氧化制程,在所述沟槽的侧壁形成一氧化层,其中与所述沟槽的侧壁相接触的各所述扩散掺杂区的一部分与氧反应为所述氧化层的一部分;以及
移除所述氧化层。
2.如权利要求1的超级结结构的制作方法,其特征在于,形成所述扩散掺杂区的步骤包括:
在所述沟槽中填入一掺杂物来源层,其中所述掺杂物来源层包括多个掺杂物,且所述掺杂物具有所述第二导电类型;以及
进行一热趋入制程,将所述掺杂物扩散至所述半导体基底中,以形成所述扩散掺杂区。
3.如权利要求2的超级结结构的制作方法,其特征在于,在形成所述扩散掺杂区的步骤与进行所述热氧化制程之间,所述制作方法还包括移除所述掺杂物来源层。
4.如权利要求3的超级结结构的制作方法,其特征在于,在进行热氧化制程与移除所述掺杂物来源层的步骤之间,所述制作方法还包括依序进行填入另一掺杂物来源层的步骤、另一热趋入制程以及移除所述另一掺杂物来源层的步骤至少一次。
5.如权利要求1的超级结结构的制作方法,其特征在于,在提供所述半导体基底的步骤与形成所述沟槽的步骤之间,所述制作方法还包括在所述半导体基底上形成一硬掩模层,且所述硬掩模层具有至少一开口。
6.如权利要求5的超级结结构的制作方法,其特征在于,在移除所述氧化层的步骤之后,所述沟槽具有一宽度,大于所述开口的一宽度。
7.如权利要求1的超级结结构的制作方法,其特征在于,移除所述氧化层的步骤包括一湿式蚀刻制程。
8.如权利要求1的超级结结构的制作方法,其特征在于,所述热氧化制程所通入的一气体包括水气、氧气、氯化氢与水气的混合气体、氯化氧与氧气的混合气体、氮气与水气的混合气体或氮气与氧气的混合气体。
9.如权利要求1的超级结结构的制作方法,其特征在于,所述热氧化制程的一温度范围介于800℃与1200℃之间。
10.一种功率晶体管组件的制作方法,其特征在于,包括:提供一半导体基底,具有一第一导电类型;
在所述半导体基底中形成至少一沟槽;
在所述沟槽两侧的所述半导体基底中分别形成两扩散掺杂区,其中各所述扩散掺杂区邻近所述沟槽侧壁的掺杂浓度大于各所述扩散掺杂区远离所述沟槽侧壁的掺杂浓度,且各所述扩散掺杂区具有不同于所述第一导电类型的一第二导电类型;
进行一热氧化制程,在所述沟槽的侧壁以及底部形成一氧化层,其中与所述沟槽侧壁相接触的各所述扩散掺杂区的一部分与氧反应为所述氧化层的一部分;
移除所述氧化层;
在所述沟槽中形成一绝缘层;
在所述沟槽至少一侧的所述半导体基底上形成一栅极结构;
在所述栅极结构的两侧的所述半导体基底中分别形成两基体掺杂区,且各所述基体掺杂区分别与各所述扩散掺杂区相接触,其中所述基体掺杂区具有所述第二导电类型;以及
在各所述基体掺杂区中分别形成一源极掺杂区。
11.如权利要求10所述的功率晶体管组件的制作方法,其特征在于,形成所述扩散掺杂区的步骤包括:
在所述沟槽中填入一掺杂物来源层,其中所述掺杂物来源层包括多个掺杂物,且所述掺杂物具有所述第二导电类型;以及
进行一热趋入制程,将所述掺杂物扩散至所述半导体基底中,以形成所述扩散掺杂区。
12.如权利要求11的功率晶体管组件的制作方法,其特征在于,在形成所述扩散掺杂区的步骤与进行所述热氧化制程之间,所述制作方法还包括移除所述掺杂物来源层。
13.如权利要求12的功率晶体管组件的制作方法,其特征在于,在进行热氧化制程与移除所述掺杂物来源层的步骤之间,所述制作方法还包括依序进行填入另一掺杂物来源层的步骤、另一热趋入制程以及移除所述另一掺杂物来源层的步骤至少一次。
14.如权利要求10的功率晶体管组件的制作方法,其特征在于,在提供所述半导体基底的步骤与形成所述沟槽的步骤之间,所述制作方法还包括于所述半导体基底上形成一硬掩模层,且所述硬掩模层具有至少一开口。
15.如权利要求14的功率晶体管组件的制作方法,其特征在于,在移除所述氧化层的步骤之后,所述沟槽具有一宽度,大于所述开口的一宽度。
16.如权利要求14的功率晶体管组件的制作方法,其特征在于,在形成所述绝缘层的步骤与形成所述栅极结构的步骤之间,所述制作方法还包括移除所述硬掩模层。
17.如权利要求10的功率晶体管组件的制作方法,其特征在于,移除所述氧化层的步骤包括一湿式蚀刻制程。
18.如权利要求10的功率晶体管组件的制作方法,其特征在于,所述热氧化制程所通入的一气体包括水气、氧气、氯化氢与水气的混合气体、氯化氢与氧气的混合气体、氮气与水气的混合气体或氮气与氧气的混合气体。
19.如权利要求10的功率晶体管组件的制作方法,其特征在于,所述热氧化制程的一温度范围介于800℃与1200℃之间。
20.一种降低扩散掺杂区的表面掺杂浓度的方法,其特征在于,包括:提供一半导体基底,所述半导体基底具有一扩散掺杂区设于其中,且所述扩散掺杂区与所述半导体基底的一表面相接触,其中所述扩散掺杂区邻近所述表面的掺杂浓度大于所述扩散掺杂区远离所述表面的掺杂浓度;
进行一热氧化制程,在所述半导体基底的所述表面形成一氧化层,其中与所述表面相接触的所述扩散掺杂区的一部分与氧反应为所述氧化层的一部分;以及
移除所述氧化层。
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CN104465389A (zh) * | 2013-09-25 | 2015-03-25 | 中国科学院微电子研究所 | FinFet器件源漏区的形成方法 |
CN110429140A (zh) * | 2019-08-06 | 2019-11-08 | 上海朕芯微电子科技有限公司 | 一种超结mosfet结构及其制备方法 |
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TWI446521B (zh) * | 2011-04-21 | 2014-07-21 | Anpec Electronics Corp | 功率元件之耐壓終止結構 |
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