CN1617302A - 制造半导体器件的方法 - Google Patents
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Abstract
公开了一种制造半导体器件的方法。该方法包括下述步骤:依序在硅衬底上形成第一抗反射层和第一光致抗蚀剂膜;形成第一图像层;形成第二抗反射层和第二光致抗蚀剂膜;形成开口宽于第一图像层的第二图像层;为了将第二图像层的图形转移到第二抗反射层上并将第一图像层的图形转移到第一抗反射层上,向生成的结构提供氧等离子体,由此形成开口;形成金属层;形成金属图形以填充开口;并除去第二图像层、第二抗反射层、第一图像层和第一抗反射层。
Description
技术领域
本发明涉及用于制造半导体器件的方法,更为具体地,涉及利用三维结构制造包括集成电路器件、光电器件、磁器件、光学器件、微型电子机械器件(MEMS)等的半导体器件的方法。
背景技术
如现有技术通常公知的,以具有微图形的多层结构制造集成电路器件、光电器件、磁器件、光学器件等。在制造具有其中微图形形成在每一层上的多层结构的这些器件中,一般采用利用光的光刻技术形成微图形。为了通过光刻技术制造多层结构的器件,需要多个掩模(标线片(reticle))和掩模对准工序。
即,根据光刻技术,首先,在衬底上涂覆具有高粘性和对光反应性的聚合物材料(例如,光致抗蚀剂),其中要构图的材料已经堆叠(或沉积)在衬底上。然后,在预定的对准标记对准在期望图形中设计的标线片(掩模)。随后,通过将光射向聚合物材料进行曝光工艺,并通过显影工艺选择性地除去被曝光的聚合物材料,以便在要被构图的材料上形成具有期望图形的图形掩模。此后,利用图形掩模进行蚀刻工艺、生长抑制工艺、杂质注入工艺等。通过这些工艺,按照期望的图形构图叠置在衬底上的材料,或在衬底的预定区域中形成其中注入杂质的掺杂区,由此制造半导体器件。
期间,在上述光刻技术中,根据在曝光工艺中使用的光的波长来确定用于微型电子机械器件等的电路中的设计规则(或图形设计规则)。因此,从目前的技术水平判断,很难利用光刻工艺在衬底上形成超微小图形,例如,0.1微米或更小的设计规则。即,由于曝光的折射,实际上不可能形成具有0.1微米或更小宽度的图形。
同时,用户需要电子设备更轻、更纤细且更小,以至于需要制造具有0.1微米或更小图形宽度的超微小器件或高集成度电路(例如,DRAM、ASIC等)。然而,由于工艺技术的限制,不可能关注厚光致抗蚀剂的预定深度,且在固化工艺期间光致抗蚀剂会被损坏,以致没有办法采用现有技术来满足上述用户需求。
发明内容
因此,已经作出本发明来解决发生在现有技术中的上述问题,且本发明的一个目的是提供一种利用叠层结构来制造三维结构的半导体器件的方法,该叠层结构具有不包括光敏材料的材料以及含有硅和光敏材料的光致抗蚀剂。
为了实现该目的,提供了一种用于制造半导体器件的方法,该方法包括下述步骤:依序在硅衬底上形成不包含光敏材料的第一抗反射层和包含硅/光敏材料的第一光致抗蚀剂膜;曝光并湿显影第一光致抗蚀剂膜,由此形成具有预定形状的第一图像层;依序在包括第一图像层的衬底的整个表面上形成不包含光敏材料的第二抗反射层和包含硅/光敏材料的第二光致抗蚀剂膜;曝光并湿显影第二光致抗蚀剂膜,由此形成开口宽于第一图像层的第二图像层;为了将第二图像层的图形转移到第二抗反射层上以及将通过第二抗反射层暴露的第一图像层的图形转移到第一抗反射层上,向生成的结构提供氧等离子体,由此形成开口;在包括开口的衬底的整个表面上形成金属层;对金属层进行化学机械抛光工艺,由此形成金属图形以填充开口;并除去第二图像层、第二抗反射层、第一图像层和第一抗反射层。
优选地,形成大约2000厚度的第一光致抗蚀剂膜,以及大约3000厚度的第二光致抗蚀剂膜。
优选地,形成1-100μm厚度的第一抗反射层。
优选地,利用极性有机溶剂进行除去第二图像层、第二抗反射层、第一图像层和第一抗反射层的步骤。
优选地,在形成第一和第二抗反射层的每一个之后,另外进行烘焙工艺。
附图说明
通过下述结合附图的详细说明,本发明的上述及其它目的、特征和优点将更加显而易见,其中:
图1至8是阐释根据本发明一个实施方案的制造半导体器件的方法的剖面图。
具体实施方式
下文,将参考附图详细描述本发明的优选实施方案。在下述说明和附图中,使用相同的参考数字表示相同或相似的部件,且因此将省略相同或相似部件的重复说明。
图1至8是阐释根据本发明一个实施方案的制造半导体器件的方法的剖面图。
即,图1至8示出了通过利用具有不包含光敏材料的第一材料(抗反射层)和包含硅/光敏材料的第二材料(光致抗蚀剂膜)的叠层结构来形成金属图形的工序。
根据本发明的用于制造半导体器件的方法,如图1中所示,依序在硅衬底1上形成第一抗反射层2和含有硅和光敏材料的第一光致抗蚀剂膜3。其中,用不包含光敏材料但可以包含诸如酚醛清漆的添加剂以便于提高粘度的材料来形成第一抗反射层2。另外,形成1-100μm厚度的第一抗反射层2,以及形成大约2000厚度的第一光致抗蚀剂膜3。
随后,如图2中所示,曝光并湿刻蚀第一光致抗蚀剂膜,由此形成具有预定形状的第一开口a1的第一图像层3a。
接着,如图3中所示,依序在包括第一图像层3a的衬底的整个表面上形成第二抗反射层4和第二光致抗蚀剂膜5。这里,相似于第一抗反射层2,用不包含光敏材料但可以包含诸如酚醛清漆的添加剂以便于提高粘度的材料来形成第二抗反射层4。另外,形成大约3000厚度的第二光致抗蚀剂膜5。
通过多个步骤形成不包含光敏材料的抗反射层,例如在本发明中为两个步骤。另外,在形成抗反射层之后,另外进行烘焙工艺。
此后,如图4中所示,曝光并湿蚀刻第二光致抗蚀剂膜,由此形成第二图像层5a。这里,第二图像层5a包括尺寸大于第一图像层3a的第一开口a1的第二开口a2。
随后,如图5中所示,对包含第二开口a2的生成的结构进行氧等离子体工艺。作为氧等离子体工艺的结果,将第二图像层5a的图形转移到第二抗反射层4上,将通过第二抗反射层4暴露的第一图像层3a的图形转移到第一抗反射层2上,由此形成具有三维形状的第三开口a3。其中,在氧等离子体工艺期间,将第二图像层5a转移到氧化硅层中,以便于用作硬掩模。
其间,在图5中,通过虚线表示的第一和第二图像层的部分表示被氧等离子体处理的区域。
接着,如图6中所示,依序在包括第三开口a3的衬底的整个表面上形成扩散阻挡层和铜层。其中,通过电镀方法形成铜层。
此后,如图7中所示,铜层和扩散层依序受到处理直到暴露第二图像层,由此形成金属图形。
随后,如图8中所示,依序利用极性有机溶剂除去第二图像层、第二抗反射层、第一图像层和第一抗反射层,以便于在衬底1上留下铜图形和扩散阻挡层。
其中,根据本发明的制造半导体器件的方法中,能够利用提升(lift-off)方法来代替电镀方法。根据提升方法,首先,利用物理气相沉积方法在衬底上沉积用于物理气相沉积的金属层。接着,在利用极性有机溶剂依序除去第二图像层、第二抗反射层、第一图像层和第一抗反射层的同时,除去位于这些层上的用于物理气相沉积的金属层。
如上所述,根据本发明的制造半导体器件的方法,利用具有不包含光敏材料的第一材料(抗反射层)和包含硅/光敏材料的第二材料(光致抗蚀剂膜)的叠层结构形成金属图形,以便于与仅使用包含高粘度且高价格的硅/光敏材料的材料的现有技术相比,能够减小制造成本。另外,根据本发明的制造方法,可容易地控制开口的深度等,由此提高了微型电子机械器件(MEMS)的生产速度。
虽然为了解释说明的目的已经描述了本发明的优选实施方案,本领域一般技术人员应当意识到在不脱离如附属权利要求公开的本发明的范围和精神下,各种修改、添加和替换是可能的。
Claims (5)
1、一种用于制造半导体器件的方法,该方法包括下述步骤:
依序在硅衬底上形成不包含光敏材料的第一抗反射层和包含硅/光敏材料的第一光致抗蚀剂膜;
曝光并湿显影第一光致抗蚀剂膜,由此形成具有预定形状的第一图像层;
依序在包括第一图像层的衬底的整个表面上形成不包含光敏材料的第二抗反射层和包含硅/光敏材料的第二光致抗蚀剂膜;
曝光并湿显影第二光致抗蚀剂膜,由此形成开口宽于第一图像层的第二图像层;
为了将第二图像层的图形转移到第二抗反射层上,并将通过第二抗反射层暴露的第一图像层的图形转移到第一抗反射层上,向生成的结构提供氧等离子体,由此形成开口;
在包括开口的衬底的整个表面上形成金属层;
对金属层进行化学机械抛光工艺,由此形成金属图形以填充开口;和
除去第二图像层、第二抗反射层、第一图像层和第一抗反射层。
2、如权利要求1所述的方法,其中形成大约2000厚度的第一光致抗蚀剂膜,以及形成大约3000厚度的第二光致抗蚀剂膜。
3、如权利要求1所述的方法,其中形成1-100μm厚度的第一抗反射层。
4、如权利要求1所述的方法,其中利用极性有机溶剂进行除去第二图像层、第二抗反射层、第一图像层和第一抗反射层的步骤。
5、如权利要求1所述的方法,还包括在形成第一和第二抗反射层的每一个之后进行烘焙工艺的步骤。
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KR10-2003-0079152A KR100511890B1 (ko) | 2003-11-10 | 2003-11-10 | 반도체소자 제조방법 |
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CN1925136B (zh) * | 2005-08-31 | 2011-07-06 | 富士通半导体股份有限公司 | 半导体器件的制造方法及半导体器件 |
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US6432814B1 (en) * | 2000-11-30 | 2002-08-13 | Agere Systems Guardian Corp. | Method of manufacturing an interconnect structure having a passivation layer for preventing subsequent processing reactions |
US6383919B1 (en) * | 2001-02-07 | 2002-05-07 | Advanced Micro Devices, Inc. | Method of making a dual damascene structure without middle stop layer |
US6429121B1 (en) * | 2001-02-07 | 2002-08-06 | Advanced Micro Devices, Inc. | Method of fabricating dual damascene with silicon carbide via mask/ARC |
US6372631B1 (en) * | 2001-02-07 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of making a via filled dual damascene structure without middle stop layer |
US6562725B2 (en) * | 2001-07-05 | 2003-05-13 | Taiwan Semiconductor Manufacturing Co., Ltd | Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers |
US6656837B2 (en) * | 2001-10-11 | 2003-12-02 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
US6699784B2 (en) * | 2001-12-14 | 2004-03-02 | Applied Materials Inc. | Method for depositing a low k dielectric film (K>3.5) for hard mask application |
CN1215551C (zh) * | 2002-04-12 | 2005-08-17 | 台湾积体电路制造股份有限公司 | 阻绝气体释放及凸出结构产生的双镶嵌方法 |
-
2003
- 2003-11-10 KR KR10-2003-0079152A patent/KR100511890B1/ko active IP Right Grant
-
2004
- 2004-06-23 US US10/875,138 patent/US6962874B2/en not_active Expired - Lifetime
- 2004-06-30 CN CNB2004100794178A patent/CN1324652C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1925136B (zh) * | 2005-08-31 | 2011-07-06 | 富士通半导体股份有限公司 | 半导体器件的制造方法及半导体器件 |
Also Published As
Publication number | Publication date |
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KR20050045186A (ko) | 2005-05-17 |
CN1324652C (zh) | 2007-07-04 |
KR100511890B1 (ko) | 2005-09-05 |
US6962874B2 (en) | 2005-11-08 |
US20050101122A1 (en) | 2005-05-12 |
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