CN1606172A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1606172A
CN1606172A CN200410092152.5A CN200410092152A CN1606172A CN 1606172 A CN1606172 A CN 1606172A CN 200410092152 A CN200410092152 A CN 200410092152A CN 1606172 A CN1606172 A CN 1606172A
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electrode layer
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西部荣次
八柳俊佑
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Sanyo Electric Co Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

一种半导体装置及其制造方法。其提高高击穿电压MOS晶体管的工作击穿电压。将N－型漏极层(4b)与栅电极(5)的下面重叠而形成在P型半导体衬底(1)的表面，向N－型漏极层(4b)施加比向栅电极(5)施加的栅极·源极间电压Vgs高的漏极·源极间电压Vds时，使栅电极(5)的下面N－型漏极层(4b)部分的表面耗尽化。由此，流到MOS晶体管的沟道电流Ie避免遇到N－型漏极层(4b)的端部表面的电场集中部分，而流经其耗尽层(7)的下方的N－型漏极层(4b)，因此，衬底电流Isub降低，工作击穿电压提高。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，特别是涉及高击穿电压MOS晶体管的结构及其制造方法。
背景技术
图4是表示现有例的N沟道型高击穿电压MOS晶体管的结构剖面图。在P型硅衬底50上介由栅极绝缘膜51形成栅电极52。在栅电极52的侧壁上形成由绝缘膜构成的侧壁隔层53。另外，形成由N-型源极层54a和N+型源极层54b构成的源极层54，由N-型漏极层55a和N+型漏极层55b构成的漏极层55。
该高击穿电压MOS晶体管通过与栅电极52邻接而设置N-型漏极层55a，在离开栅电极52的位置设置N+型漏极层55b，衰减漏极电场，得到高的漏极击穿电压。
另外，这种高击穿电压MOS晶体管例如在以下的专利文献1公开。
专利文献1特开平5-218070号公报
发明内容
但是，在上述的现有高击穿电压MOS晶体管中，存在工作击穿电压(MOS晶体管导通时的漏极击穿电压)低的问题。特别是当栅极·源极间电压Vgs低，漏极·源极间电压Vds高时，电场集中在漏极端的表面，若晶体管的沟道电流路径与该电场集中部分相遇，则发生所谓碰撞电离现象(碰撞离子化现象)。由此，产生大的衬底电流Isub，工作击穿电压恶化。
因此，本发明提供一种极力降低高击穿电压MOS晶体管工作时的衬底电流Isub，使其工作击穿电压提高的装置。
本发明的半导体装置，具有：半导体衬底；在上述半导体衬底上介由栅极绝缘膜形成的栅电极；与上述栅电极的下面重叠而在所述半导体衬底的表面形成的低浓度漏极层；在上述半导体衬底的表面形成的高浓度漏极层；在上述半导体衬底的表面形成的源极层，当向所述高浓度漏极层施加比向所述栅电极施加的栅极·源极间电压Vgs高的漏极·源极间电压Vds时，使所述栅电极的下面的所述低浓度漏极层部分的表面耗尽化。
另外，在上述结构的基础上，上述高浓度漏极层配置在离开上述栅电极端部的位置。
另外，本发明的半导体装置的制造方法具有：在半导体衬底上形成栅极绝缘膜的第一工序；在上述半导体衬底的表面形成低浓度漏极层的第二工序；在上述栅极绝缘膜上形成与上述低浓度漏极层局部地重叠的栅电极的第三工序；以及在上述半导体衬底的表面上边形成高浓度漏极层的第四工序。
另外，上述第四工序在离开上述栅电极端部的位置形成上述高浓度漏极层。
根据本发明，将低浓度漏极层与上述栅电极下面重叠而形成在上述半导体衬底的表面，向上述高浓度漏极层施加比向上述栅电极施加的栅极·源极间电压Vgs高的漏极·源极间电压Vds时，使所述栅电极的下面的上述低浓度漏极层部分的表面耗尽化。因此，流到MOS晶体管的沟道电流避免遇到漏极端部表面的电场集中部分，而流经其耗尽层的下方的低浓度漏极层，因此，减少了衬底电流Isub，提高了工作击穿电压。另外，沟道电流流经离开半导体衬底表面的耗尽层的下边，因此减少了沟道担负沟道电流的载流子的表面散射，提高了晶体管的驱动能力。
另外，因为将高浓度漏极层配置在离开栅电极的端部的位置，所以能防止发生由栅电极端的强电场影响造成的漏极漏电流GIDL(Gate InducedDrain Leakage current)，进一步提高工作击穿电压。
附图说明
图1(a)、图1(b)、图1(c)是说明本发明第1实施例的半导体装置制造方法的剖面图；
图2是表示本发明第1实施例的半导体装置工作时漏极附近状态的剖面图；
图3是说明本发明第二实施例的半导体装置的剖面图；
图4是说明现有例的半导体装置的剖面图。
具体实施方式
接着，说明用于实施本发明的最佳方式(以下，称为实施例)。参照附图说明本发明实施例的半导体装置及其制造方法。首先，参照图1和图2说明第一实施例。图1是表示该半导体装置的制造方法的剖面图。
如图1(a)所示，在P型半导体衬底1(例如，P型硅衬底)的表面上用热氧化法等形成栅极绝缘膜2。然后，在P型半导体衬底1的表面互相隔开地形成N-型源极层3a和N-型漏极层4a。本工序中，用掩模在P型半导体衬底1的表面低浓度地离子注入磷等N型杂质，然后通过进行热扩散，形成N-型源极层3a和N-型漏极层4a。
其次，如图1(b)所示，在栅极绝缘膜2上形成与N-型源极层3a和N-型漏极层4a局部重叠的栅电极5。然后，在栅电极5的侧面形成侧壁隔层5。本工序，首先，整个面利用LPCVD法淀积多晶硅层，向其掺杂磷等的杂质而使其低电阻化后，局部蚀刻该多晶硅层而形成栅电极5。之后，全面利用LPCV D法淀积氧化硅膜，通过将该氧化硅膜进行各向异性蚀刻，在栅电极5的侧面形成侧壁隔层6。
其次，如图1(c)所示，向P型半导体衬底1的表面高浓度地离子注入磷等N型杂质，与栅电极5的端部邻接而形成N+型源极层3b和N+型漏极层3b。该高击穿电压MOS晶体管的源极层3由N-型源极层3a和N+型源极层3b构成，漏极层4由N-型漏极层4a和N+型漏极层4b构成。
参照图2说明该高击穿电压MOS晶体管的工作。图2是表示高击穿电压MOS晶体管工作时漏极附近状态的剖面图。向N+漏极层4b施加漏极电压Vds，向栅电极5施加栅电极Vgs。
这时，当施加比栅极·源极间电压Vgs高的漏极·源极间电压Vds时(Vds＞Vgs)，与栅电极5下面重叠的N-型漏极层4a部分的表面产生表面耗尽层7。于是，流到高击穿电压MOS晶体管的沟道电流Ie(电子电流)，避免遇到N-型漏极层4a端表面的电场集中部分，流经其表面耗尽层7下方的N-型漏极层4a的深区域，因此衬底电流Isub降低，工作击穿电压提高。
其次，参照图3说明第二实施例。图3是本发明第二实施例的半导体装置剖面图。在第一实施例中，N+型源极层3b和N+型漏极层4b与栅电极5的端部邻接而形成。因此，存在发生由栅电极5端部的强电场的影响导致的漏极漏电流GIDL(Gate Induced Drain Leakage current)的问题。因此，在本实施例中，将N+型漏极层4b形成在离开栅电极5端部的位置。
另外，在第一和第二的实施例中源极层3具有低浓度层，即N-型源极层3a，但也可是仅具有N+型源极层3b的单一源极层结构。

Claims (4)

1.一种半导体装置，其特征在于，具有：半导体衬底；在所述半导体衬底上介由栅极绝缘膜形成的栅电极；与所述栅电极的下面重叠而在所述半导体衬底的表面形成的低浓度漏极层；在所述半导体衬底的表面形成的高浓度漏极层；在所述半导体衬底的表面形成的源极层，
当向所述高浓度漏极层施加比向所述栅电极施加的栅极·源极间电压Vgs高的漏极·源极间电压Vds时，使所述栅电极的下面的所述低浓度漏极层部分的表面耗尽化。
2.按照权利要求1所述的半导体装置，其特征在于，所述高浓度漏极层配置在离开所述栅电极端部的位置。
3.一种半导体装置的制造方法，其特征在于，具有：在半导体衬底上形成栅极绝缘膜的第一工序；在所述半导体衬底的表面形成低浓度漏极层的第二工序；在所述栅极绝缘膜上形成与所述低浓度漏极层局部地重叠的栅电极的第三的工序；在所述半导体衬底的表面上边形成高浓度漏极层的第四工序。
4.按照权利要求3所述的半导体装置的制造方法，其特征在于，所述第四工序在离开所述栅电极端部的位置形成所述高浓度漏极层。
CN200410092152.5A 2003-10-09 2004-10-09 半导体装置及其制造方法 Pending CN1606172A (zh)

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CN101840932A (zh) * 2009-03-12 2010-09-22 夏普株式会社 半导体装置及其制造方法

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JP5418041B2 (ja) * 2009-07-24 2014-02-19 株式会社リコー 半導体装置
JP5434501B2 (ja) * 2009-11-13 2014-03-05 富士通セミコンダクター株式会社 Ｍｏｓトランジスタおよび半導体集積回路装置、半導体装置

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CN101840932A (zh) * 2009-03-12 2010-09-22 夏普株式会社 半导体装置及其制造方法
US8241985B2 (en) 2009-03-12 2012-08-14 Sharp Kabushiki Kaisha Semiconductor device having gate electrode with lower impurity concentration at edge portions than above channel and method of manufacturing the same

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