CN1543672A - 将氨用于刻蚀有机低k电介质 - Google Patents
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Abstract
用于将氨NH3用作活性刻蚀剂来刻蚀有机低k电介质的方法。以类似的过程条件,使用氨的过程导致至少两倍于使用N2/H2化学的过程的对有机低k电介质的刻蚀速率。其差别是由于在过程化学中NH3比N2低的多的离子化势能,这导致在类似过程条件下的明显较高的等离子体密度和刻蚀剂浓度。
Description
发明领域
本发明涉及半导体制造。更具体而言,本发明涉及对半导体晶片中有机低k电介质的刻蚀。
发明背景
集成电路使用电介质层来隔离半导体结构的各个层上的传导线,所述电介质层典型地由二氧化硅SiO2形成。随着半导体电路变得更牢固(fast)和紧凑,工作频率增加而半导体器件内的传导线之间的距离减小。由此引入了与电路的耦合电容的水平增加,这具有减慢半导体器件工作的缺点。因此,使用能有效减小电路中的耦合电容的电介质层已变得重要。
一般而言,集成电路中的电容与用来形成电介质层的材料的介电常数k成正比。如以上所指出的,常规集成电路中的电介质层在传统上由SiO2形成,其具有大约4.0的介电常数。由SiO2形成的电介质层并不将耦合电容充分减小到增加器件密度和工作频率所需的水平。在减小集成电路中的耦合电容水平的努力中,半导体行业致力于开发材料的研究,该材料具有低于SiO2的介电常数,适合于在形成集成电路中的电介质层的过程中使用。迄今为止,多种有希望的材料已被开发,其有时被称为“低k材料”。许多这些新电介质是有机化合物。在本说明书和权利要求中,低k材料的定义是具有小于3的介电常数的材料。
低k材料包括但具体并不局限于:苯并环丁烯(benzocyclobutene)或BCB;Honeywell,Inc.,Minneapolis,MN的分支Allied Signalof Morristown,NJ制造的FlareTM;可从Union CarbideCorporation,Danbury CT获得的一个或多个聚对二甲苯二聚物(Parylene dimer);聚四氟乙烯和PTFE;以及SiLK。适合于IC电介质应用的一个PTFE是可从W.L.Gore & Associate,Inc,Newark,DE获得的SPEEDFILMTM。可从DowChemical Company,Midland,Michigan获得的SiLK是无硅的BCB。
在半导体晶片的处理期间,使用众所周知的特图形化和刻蚀过程在晶片中限定半导体器件的特征。在这些过程中,光致抗蚀剂(PR)材料被淀积于晶片上,然后被曝光于由分划板(reticle)过滤的光。分划板通常是玻璃板,其用防止光传播经过该分划板的示例特征几何形状来图形化。
在经过分划板之后,所述光接触光致抗蚀剂材料的表面。该光改变光致抗蚀剂材料的化学成分,从而使显影剂(developer)可去除光致抗蚀剂材料的一部分。在正光致抗蚀剂材料的情况下,曝光区被去除,而在负光致抗蚀剂材料的情况下,未曝光区被去除。之后晶片被刻蚀以从不再受光致抗蚀剂材料保护的区域去除下面的材料,并由此限定晶片中的所需特征。低k有机聚合体通常可通过氧化(例如基于氧的)或还原(例如基于氢的)化学过程来刻蚀。
有机低k电介质的刻蚀可有利地在双频电容耦合(DFC)电介质刻蚀系统中完成。一个这样的系统是可从LamResearch Corporation,Fremont CA获得的LamResearch model 4520XLETM。4520XLETM系统在一个系统中处理极其全面的电介质刻蚀业务量(portfolio)。过程包括接触、通孔、双水平接触、无边界接触、氮化物和氧化物间隔、以及钝化。
类似4520XLETM的高级刻蚀系统在相同的系统中执行几个过程。通过在单个系统中执行许多不同的半导体制造步骤,晶片生产量可被增加。更高级的系统预期在相同的设备中执行附加的步骤。同样为了举例而不是局限,LamResearch Corporation的ExelanTM和Exelan-HPTM系统是能在单个设备中执行许多过程步骤的干刻蚀系统。ExelanTM使硬掩模开口(hardmas kopen)、无机和有机ARC刻蚀、以及光致抗蚀剂剥离(strip)能借助单个室在原地执行。该系统的大范围过程业务量包括亚-0.18微米环境中所需要的掺杂和未掺杂的氧化物和低k电介质中的所有双波纹结构(dual damascene structure)、接触、通孔、间隔和钝化刻蚀。当然,在此所列举的原理可被实施于各种各样的半导体制造系统中,并且这些原理具体预期所有这一类的替换。
如在此所使用的,术语“在原地”指的是在半导体制造设备的相同件上的给定基片如硅晶片上执行的一个或多个过程,而无需从设备去除基片。
如所讨论的,有机低k电介质的刻蚀可使用基于氧或基于氢的刻蚀过程来完成。然而,其每个都是不够理想的。
基于氢的刻蚀过程,例如:N2/H2过程,对于刻蚀有机低k电介质是不够理想的,特别是对于刻蚀在目前的亚-0.18微米器件中所需要的高密度特征。这由于多种原因是真实的。首先,目前的N2/H2过程提供通常低的刻蚀速率和对所刻蚀特征的差的轮廓控制:弯曲和凹入(re-entrant)的刻蚀轮廓尤其是问题。另一个问题涉及具有不同尺寸的高纵横比特征,该特征被同时刻蚀。
到低k材料中的有时被称为HART的高纵横比沟槽的刻蚀对于微米和纳米工程设计正变得日益重要。一个实例是在用于垂直晶体管的沟槽隔离、沟槽电容器和梳状驱动结构的情况下。纵横比AR被定义为沟槽的深度除以其宽度。目前,用于刻蚀HART的最一般实施的技术之一是干反应性离子刻蚀或RIE。
当借助RIE刻蚀HART时,观察到刻蚀速率取决于时间和掩模开口。一般而言,相对于较宽的沟槽开口,较小的沟槽开口刻蚀得较慢。因此,大特征以比小特征快的速率刻蚀。这个效应被已知为纵横比相关的刻蚀(ARDE)或“RIE滞后”。已知的N2/H2刻蚀过程不仅导致明显的RIE滞后,并且更重要的是,亦显示出对特征尺寸的刻蚀轮廓角度相关性。
有关已知的N2/H2化学的另一个问题是相对于在刻蚀期间一般被用作硬掩模的氧化物和氮化物,它们具有通常差的选择性。这意味着应提供精确特征限定的硬掩模本身通过N2/H2刻蚀化学在电介质刻蚀期间被相当快地刻蚀掉。
有关N2/H2等离子体的另一个问题是通常作为N2的高离子化势能的结果,它们仅在相当窄的压力和功率范围上是稳定的。
最后,借助N2/H2过程的有机低k电介质的刻蚀是缓慢的。这导致晶片生产量减小和对于集成电路制造商而言,处理设备的所有权的成本增加。
可通过N2/H2过程获得的慢刻蚀速率常常使用氧化过程来克服,最特别的是利用氧气O2和稀释剂如氮气N2。O2/N2刻蚀系统趋向于拥有比N2/H2系统快的多的刻蚀速率,但特别易于弯曲并且可使低k电介质的介电常数降级。更麻烦的是,它们引入了明显的新问题,特别是当与结合铜的集成电路器件的制造一起被使用时。
铜是目前被实施为有利于现有铝互连技术的互连材料。铜提供了优于铝的几个重要优点。铜较高的传导率简化了互连路线(interconnect routing)。由此将互连水平从12减小到6,这减小了200个以上的过程步骤并具有对器件产量的直接影响。具有铜互连的芯片在给定频率下以比具有铝互连的芯片小的功率工作。因此,铜互连技术使能对于移动应用具有明显较高性能的器件。最后,对于很小的特征,用于铜和低k材料的互连延迟是铝和SiO2的近似一半。铜互连因此对于很小的特征是优选的,这是因为它提供了对速度的提高,而并没有牺牲器件的可靠性。
当这种器件中的铜被曝光于刻蚀环境时,由于产生了含铜的残余物,氧等离子体的使用常常导致对铜线的损坏,所述残余物可淀积于沟槽上并通过侧壁,从而导致对电介质材料的铜污染。铜到器件的晶体管水平的最终迁移导致由于铜中毒而造成的器件故障。
许多目前的集成电路制造技术利用了在被用于形成晶片中的特征的一个或多个图形化步骤之后的光致抗蚀剂剥离步骤。如果可以找到不仅完成电介质刻蚀步骤而且同时从晶片的表面去除光致抗蚀剂的方法学,则可去掉单独的光致抗蚀剂剥离的过程步骤。这当然可导致较低的处理时间和较高的生产量。
根据以上所述,实施比先前N2/H2过程高的刻蚀速率同时避免与现有N2/H2过程关联的问题的低k刻蚀过程将是很理想的。
亦将很理想的是避免有关RIE滞后、刻蚀速率并且特别是轮廓控制的先前讨论的问题。
此外,很理想的是提供一种刻蚀过程,其显示出在有机低k电介质和通过电介质形成特征所需的硬掩模之间的选择性的高的多的程度。如果所述刻蚀过程可使所刻蚀的特征的底部处的“微屏蔽”效应最小,这将也是有利的。当所述刻蚀过程刻蚀掉硬掩模的一部分随后在所刻蚀的特征的底部处重新淀积所刻蚀的硬掩模的元素时发生微屏蔽。
将很有利的是如果可实施一种电介质刻蚀过程,其实现以上优点同时与目前的N2/H2过程相比,使能在较大幅度的压力和功率工作上的较稳定的刻蚀等离子体。
为了维持较高的晶片生产量,亦理想的是,方法学能在被用于形成晶片的制造设备中在原地被执行。
最后,如果这些优点可使用现有集成电路制造设备来实施,这将是很理想的。
本发明的这些和其它特征将结合随后的图并且在题为优选实施例详述的部分中更详细地描述。
发明概述
本发明讲授了一种过程化学,其利用氨NH3作为活性刻蚀剂,用于刻蚀结合有机低k电介质的晶片中的特征。该过程导致比先前N2/H2过程明显高的刻蚀速率并且避免了有关RIE滞后并且特别是轮廓控制的先前讨论的问题。该过程显示出在有机低k电介质和一般使用的硬掩模材料之间的选择性的高的多的程度。与目前的N2/H2过程相比,本发明所公开的过程使能在较大幅度的压力和功率工作上的较稳定的刻蚀等离子体。在此公开的过程能在被用于形成晶片的制造设备中在原地被执行,并且能在各种各样的现有集成电路制造设备上实施。氨刻蚀剂不仅刻蚀有机低k电介质,而且从晶片的表面去除光致抗蚀剂。
使用氨作为有机低k电介质刻蚀剂可与其它刻蚀例行工作结合以通过各种各样的膜形成特征,从而实施任何数量的集成电路设计。
附图简述
为了对本发明的较完整的理解,参考了以下优选实施例详述中的附图。在附图中:
图1a是一个过程的总流程图,该过程用于刻蚀作为集成电路器件的一部分的一层有机低k电介质。
图1b是一个过程的总流程图,该过程用于刻蚀通过晶片堆积(stack)的特征,该晶片堆积结合了由沟槽停止层分开的两层有机低k电介质并结合了硬掩模。
图2a是通过一个测试晶片的截面图,在刻蚀之前已向其应用了光致抗蚀剂的图形化层。
图2b是在第一刻蚀步骤之后通过所述测试晶片的截面图。
图2c是在第二、非选择性刻蚀步骤之后通过所述测试晶片的截面图。
图2d是在采用氨作为最终的刻蚀剂以形成特征的第三刻蚀步骤之后通过所述测试晶片的截面图。
图3是通过一个测试晶片的显微照片,显示了通过本发明实现的轮廓控制。
参考数字指的是在所有几个附图中本发明的相同或等效部分。
优选实施例详述
本发明讲授了一种新的刻蚀化学,用于刻蚀结合有机低k电介质的晶片中的各种各样的特征尺寸和形状。在此所讲的方法学产生了最小的RIE滞后、刻蚀过程形成的沟槽和通孔的最小弯曲、好的刻蚀轮廓、以及晶片上好的刻蚀均匀性。
为了刻蚀包括有机低k电介质层的晶片中的各种特征,包括但具体不局限于沟槽和通孔,本发明将氨实施为刻蚀剂。
参考图1a,为了实践本发明的过程100,晶片被置于能形成刻蚀等离子体的反应容器内。该反应容器或室可以是一项单一目的的刻蚀设备,或者可以是多目的的处理系统。特别适合于实践本发明的一个设备是ExelanTM干刻蚀系统,其可从Lam Research Corporation,Fremont,CA获得。ExelanTM能在单个室中在原地执行硬掩模打开、无机和有机ARC刻蚀、以及光致抗蚀剂剥离。当然,可以利用可替换的设备。
先前已具有被应用于其上表面的一层图形化光致抗蚀剂的晶片在102处被安装于室内,刻蚀剂气体的流在104处被引入到室内,并且刻蚀等离子体在106处被轰击。如先前所讨论的,该刻蚀剂气体包括氨NH3。
本发明可在常规上被实施为多步骤刻蚀方案的一部分,例如,如图1b和2a-d所示。现在参考图2,具有光致抗蚀剂的图形化层的示例晶片1被示出。在该实例中,晶片1包括在其上淀积了碳化硅阻挡层20的硅基片22。在阻挡层20上淀积的是有机低k电介质例如DowChemical的SiLKTM的第一层18。未示出的金属化结构可被形成于阻挡层20之下。薄碳化硅沟槽停止层16被淀积于第一有机低k层18和第二有机低k层14之间以形成双波纹结构,未示出。亦由SiLKTM制成的第二有机低k层14被淀积于沟槽停止层16上。PEARLTM的硬掩模层,亦可从Novellus System,Inc.SanJose,CA获得的等离子体强化抗反射层,被淀积于第二有机硅酸盐(organosilicate)层14上,从而完成晶片堆积中的实例。先前讨论的图形化的光致抗蚀剂层10被应用于硬掩模12上。当然,本领域的技术人员将认识到,这种晶片堆积只是示例性的。本领域技术人员已知的可替换结构和膜可被用于实施可替换的集成电路设计。
现在参考图1b和2a-d,公开了一个多步骤刻蚀过程200,其利用了采用先前讨论的双频刻蚀设备的氨刻蚀步骤。本发明的几个过程参数可被修改以适合于变化的条件、刻蚀剂气体组合和晶片堆积成分。特定的优选实施例及其替换将在以下被讨论。
在102处,晶片被置于反应室内。在120处,第一、选择性刻蚀剂气体的流被引入到先前所讨论的双频刻蚀设备的室内。在104处,刻蚀等离子体被击。依照一个实施例,第一刻蚀剂气体是包括Ar、氧、四氟化碳(carbon tetrafluoromethane)CF4和八氟环丁烷(octafluorocyclobutane)C4F8的混合物。该混合物当然是高度专用的,并且实施可替换刻蚀剂和稀释剂的可替换刻蚀步骤可被用于依照本发明的NH3刻蚀步骤之前或之后。
依照本发明的一个实施例,第一、选择性、刻蚀步骤在0和250mTorr之间的室压力下进行,较优选的是在10和100mTorr之间,更优选的是在40和80mTorr之间,最优选的是在大约70mTorr。
等离子体的较高频率被形成于从大约250W到大约2500W的功率水平。较优选的是,较高功率水平从大约250W到大约1500W形成。更优选的是,该功率水平被设置于大约250到1000W之间。最优选的是,较高频率功率被设置于大约500W。
较低频率功率水平被设置于从大约250W到大约2500W的功率水平。较优选的是,较高功率水平从大约500W到大约2000W形成。更优选的是,该功率水平被设置于大约750到2000W之间。最优选的是,较低频率功率被设置于大约1000W。
第一刻蚀剂气体的混合物优选地包括组分刻蚀气体的流。这些包括氧O2,其具有从大约3sccm到大约300sccm的流,较优选的是从大约5sccm到大约75sccm,更优选的是从大约10sccm到大约50sccm,而最优选的是大约15sccm。这种第一刻蚀剂气体亦包含作为稀释剂的氩,其具有从大约10sccm到大约500sccm的流,较优选的是从大约50sccm到大约250sccm,更优选的是从大约100sccm到大约200sccm,而最优选的是大约160sccm。
刻蚀剂进一步包括八氟环丁烷C4F8流,从大约1sccm到大约50sccm,较优选的是从大约3sccm到大约30sccm,更优选的是从大约5sccm到大约20sccm,而最优选的是大约5sccm。该实施例中最后的刻蚀气体组分是CF4四氟化碳,其具有从大约1sccm到大约100sccm的流率,较优选的是从大约10sccm到大约75sccm,更优选的是从大约20sccm到大约50sccm,而最优选的是大约40sccm。
刻蚀在受控的温度下进行特定的时间段。在讨论中的范例中,第一刻蚀可在0℃和60℃之间的温度下进行。较特别的是从大约5℃到大约50℃。更特别的是从大约10℃到大约40℃,而最优选的是大约40℃。第一刻蚀时间可进一步从一秒的小分数到大约10分钟变化,并且是情况相关的。在这里所提出的实例中,在以最优选的功率设置、气体流和温度进行刻蚀的情况下,第一、选择性刻蚀在大约28秒内完成。该刻蚀步骤提供了有机硅酸盐电介质14和停止层16之间的高程度选择性。
为了完成前述的温度控制,晶片的温度由通过卡盘的冷却剂气体流来热维持,该卡盘在反应容器中保持晶片,有时被称为ESC或静电卡盘。冷却剂气体例如氦的这个流动处于从大约1sccm到大约50sccm的流率,较优选的是从大约2sccm到大约30sccm,更优选的是从大约10sccm到大约20sccm,而最优选的是大约15sccm。刻蚀继续进行,直到遇见所需的刻蚀结果。在该实例中,第一刻蚀步骤继续进行,直到刻蚀到达刻蚀停止层16,如图2b所示。这对应于步骤122。
为完成在该实例中是通过停止层16的非选择性刻蚀的第二刻蚀步骤124,几个先前讨论的过程参数被改变。第二刻蚀在0和250mTorr之间的室压力下进行,较优选的是在10和100mTorr之间,更优选的是在40和90mTorr之间,最优选的是在大约55mTorr。
等离子体的较高频率被形成于从大约250W到大约2500W的功率水平。较优选的是,较高功率水平从大约500W到大约2000W形成。更优选的是,该功率水平被设置于大约1000到1500W之间。最优选的是,较高频率功率被设置于大约1400W。
较低频率功率水平被设置于从大约250W到大约2500W的功率水平。较优选的是,较高功率水平从大约500W到大约2000W形成。更优选的是,该功率水平被设置于大约750到2000W之间。最优选的是,较低频率功率被设置于大约1000W。
第二刻蚀剂气体的混合物再次优选地包括组分刻蚀气体的流。这些包括氧O2,其具有从大约3sccm到大约300sccm的流,较优选的是从大约5sccm到大约150sccm,更优选的是从大约7sccm到大约50sccm,而最优选的是大约9sccm。这种第二刻蚀剂气体亦包含作为稀释剂的氩,其具有从大约10sccm到大约500sccm的流,较优选的是从大约50sccm到大约250sccm,更优选的是从大约100sccm到大约200sccm,而最优选的是大约140sccm。
刻蚀剂进一步包括八氟环丁烷C4F8的流,从大约1sccm到大约50sccm,较优选的是从大约5sccm到大约30sccm,更优选的是从大约10sccm到大约20sccm,而最优选的是大约15sccm。
同样,刻蚀在受控的温度下进行特定的时间段。在讨论中的范例中,第二刻蚀可在0℃和60℃之间的温度下进行。较特别的是从大约5℃到大约50℃。更特别的是从大约10℃到大约40℃,而最优选的是大约40℃。同样,刻蚀温度由被应用于过程卡盘中的晶片背侧的的冷却剂气体流来维持。过程时间可进一步从一秒的小分数到大约10分钟变化,并且是情况相关的。在这里所提出的实例中,在以最优选的功率设置、气体流和温度进行处理的情况下,第二刻蚀在大约10秒内完成。该刻蚀步骤提供了有机硅酸盐电介质18和停止层16之间的低程度选择性。刻蚀步骤124继续进行,至少直到已刻蚀经过停止层16,如图2c所示。此时到达步骤126。
为完成对特征的刻蚀,第三选择性刻蚀步骤106被进行。为执行步骤106,即通过OSG层18的剩余部分的刻蚀,几个先前讨论的过程参数再次被改变。第三刻蚀在0和500mTorr之间的室压力下进行,较优选的是在10和250mTorr之间,更优选的是在100和200mTorr之间,最优选的是在大约160mTorr。
等离子体的较高频率被形成于从大约150W到大约2500W的功率水平。较优选的是,较高功率水平从大约250W到大约1500W形成。更优选的是,该功率水平被设置于大约250到1000W之间。最优选的是,较高频率功率被设置于大约500W。
较低频率功率水平被设置于从大约0W到大约2500W的功率水平。较优选的是,较低功率水平从大约0W到大约1000W形成。更优选的是,该功率水平被设置于大约0到100W之间。最优选的是,较低频率功率被设置于大约0W。
第三刻蚀剂气体的混合物再次优选地包括刻蚀气体流。在一个优选实施例中,该刻蚀剂气体包括氨NH3,从大约5sccm到大约1500sccm,较优选的是从大约100sccm到大约1000sccm,更优选的是从大约300sccm到大约800sccm,而最优选的是大约600sccm。
尽管本发明的一个实施例预期将NH3单独用作刻蚀剂,可替换实施例仍预期了稀释剂的使用。替换可包含氦或其它已知的刻蚀剂气体稀释剂。
再一次,刻蚀在受控的温度下进行特定的时间段。在讨论中的范例中,第三刻蚀可在0℃和60℃之间的温度下进行。较特别的是从大约5℃到大约50℃。更特别的是从大约10℃到大约40℃,而最优选的是大约40℃。同样,刻蚀温度由被应用于过程卡盘中的晶片背侧的的冷却剂气体流来维持。过程时间可进一步从一秒的小分数到大约10分钟变化,并且是情况相关的。在这里所提出的实例中,在以最优选的功率设置、气体流和温度进行处理的情况下,第三刻蚀在大约205秒内完成。该刻蚀步骤提供了有机硅酸盐电介质18和阻挡20之间的高程度选择性。在刻蚀步骤106之后,刻蚀在108处被完成,而晶片可用于110处的进一步处理。
此时,在刻蚀方案中,例如由光致抗蚀剂层10限定的24和26的特征现在已刻蚀经过硬掩模层12、第一OSG电介质层14、沟槽停止层16和第二OSG电介质层20。如图2d所示,当到达阻挡层20时,特征被完全刻蚀。此时,先前讨论的刻蚀和剥离步骤已被完成,特征24和26被形成于晶片堆积1中,并且光致抗蚀剂层10从那个晶片堆积被剥离。晶片堆积现在已准备好完成集成电路器件所需的进一步的图形化、掺杂或淀积步骤。
过程200提供了几个新优点。其中第一个是由本发明的方法学使能的轮廓控制的突出的控制程度。这被示出于图3,依照本发明而刻蚀的梳状结构的显微照片。由此使能的极度各向异性的刻蚀轮廓是显而易见的。
第二个优点是在第三刻蚀步骤中,所有的光致抗蚀剂已由NH3从晶片剥离。这排除了对晶片制造中单独的光致抗蚀剂剥离步骤的需要。
在检验本发明期间注意到的一个优点是明显没有由NH3刻蚀产生的弯曲。假定在离子轰击不足的地方,例如在通孔和沟槽的侧壁上,NH3与低k电介质反应以形成聚合体,可能是有终结(terminating)-NH2组的叠氮化物。这个所合成的聚合体钝化侧壁并防止轮廓弯曲。聚合体形成看来是温度相关的并且可能是反应速率受控的。侧壁聚合体厚度和完整性随着温度的增加而增加。
本发明的另一个实施例预期在最后的刻蚀步骤106期间添加甲基氟化物CH3F。这种添加已被证明减小了先前讨论的微屏蔽效应。在一个实施例中,从大约1sccm到大约50sccm的CH3F流被添加给先前讨论的NH3刻蚀步骤。较优选的是,该流从大约5sccm到大约30sccm,更优选的是从大约10sccm到大约20sccm,而最优选的是大约10sccm。
为了完成前述的温度控制,晶片的温度由通过卡盘的冷却剂气体的流用热方法维持,该卡盘在反应容器中保持晶片。冷却剂气体例如氦的这个流处于从大约1sccm到大约50sccm的流率,较优选的是从大约2sccm到大约30sccm,更优选的是从大约10sccm到大约20sccm,而最优选的是大约15sccm。
该图中未示出的是先前讨论的铜特征。通过使用NH3刻蚀剂,铜特征的氧化被排除,并且预防了器件的晶体管效应随之的铜中毒。
本发明的特定特征是其以下新能力:以极佳的轮廓控制并以最小的RIE滞后、由刻蚀过程形成的通孔的最小弯曲、好的刻蚀轮廓、好的抗蚀剂选择性和晶片上好的刻蚀均匀性同时形成广泛变化尺寸的特征。
对本领域的技术人员来说,显然是将是,先前讨论的功率水平、压力、流率和温度只是为了举例。在晶片堆积中以变化的厚度放置的不同电介质材料可能需要功率、压力、流量和温度的不同组合。本发明中的原理具体预期所有这样的组合。
本发明已参照其特征的特定优选实施例而被具体示出和描述。然而,对本领域的技术人员来说,显而易见的将是,可在如所附权利要求中提出的本发明的精神和范围内进行形式和细节上的各种改动和修改。具体而言,本发明的原理具体预期在由许多不同的层限定的变化的晶片堆积配置而形成的各种各样的集成电路器件上结合在此所讲的各种特征的一个或多个。先前讨论的过程变量当然能由本领域的技术人员进行修改以实现不同的集成电路器件。每个这些替换具体都是本发明的原理所预期的。
Claims (19)
1.一种刻蚀基片上的有机电介质层的方法,包括:
将基片置于刻蚀室中;
将包括NH3的刻蚀剂气体提供到刻蚀室中;以及
从NH3产生等离子体,其刻蚀所述有机电介质层。
2.权利要求1的方法,其中NH3具有5sccm到1500sccm之间的流率。
3.权利要求2的方法,进一步包括将硬掩模置于有机电介质层上。
4.权利要求3的方法,进一步包括:
将图形化的光致抗蚀剂层置于硬掩模层上;以及
在刻蚀有机电介质层期间同时剥离光致抗蚀剂层。
5.权利要求4的方法,进一步包括提供CH3F,同时提供包括NH3的刻蚀剂气体。
6.权利要求5的方法,其中CH3F具有1sccm到50sccm之间的流率。
7.权利要求6的方法,进一步包括在提供包括NH3的刻蚀剂气体之前,提供利用包括CF4的刻蚀剂气体的刻蚀。
8.权利要求7的方法,其中包括CF4的刻蚀剂气体进一步包括C4F8。
9.权利要求8的方法,其中包括CF4的刻蚀剂气体进一步包括O2。
10.权利要求9的方法,其中O2具有3sccm和300sccm之间的流率。
11.权利要求10的方法,其中有机电介质层由有机低k材料制成。
12.权利要求1的方法,进一步包括将硬掩模置于有机电介质层上。
13.权利要求12的方法,进一步包括:
将图形化的光致抗蚀剂层置于硬掩模层上;以及
在刻蚀有机电介质层期间同时剥离光致抗蚀剂层。
14.权利要求1的方法,进一步包括提供CH3F,同时提供包括NH3的刻蚀剂气体。
15.权利要求14的方法,进一步包括在提供包括NH3的刻蚀剂气体之前,提供借助包括CF4的刻蚀剂气体的刻蚀。
16.权利要求1的方法,其中有机电介质层由有机低k材料制成。
17.一种由基片上的经刻蚀的有机电介质层形成的集成电路,其由以下步骤制成,包括:
将基片置于刻蚀室中;
将包括NH3的刻蚀剂气体提供到刻蚀室中;以及
从NH3产生等离子体,其刻蚀所述有机电介质层。
18.权利要求17的集成电路,其中NH3具有5sccm到1500sccm之间的流率。
19.权利要求18的集成电路,进一步包括:
将硬掩模置于有机电介质层上;
将图形化的光致抗蚀剂层置于硬掩模层上;以及
在刻蚀有机电介质层期间同时剥离光致抗蚀剂层。
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KR (1) | KR100887911B1 (zh) |
CN (1) | CN1331198C (zh) |
AU (1) | AU2002243799A1 (zh) |
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Families Citing this family (174)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777344B2 (en) | 2001-02-12 | 2004-08-17 | Lam Research Corporation | Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications |
US7183201B2 (en) * | 2001-07-23 | 2007-02-27 | Applied Materials, Inc. | Selective etching of organosilicate films over silicon oxide stop etch layers |
US8349241B2 (en) | 2002-10-04 | 2013-01-08 | Molecular Imprints, Inc. | Method to arrange features on a substrate to replicate features having minimal dimensional variability |
JP2004214336A (ja) * | 2002-12-27 | 2004-07-29 | Tokyo Electron Ltd | プラズマエッチング方法およびプラズマエッチング装置 |
US6780756B1 (en) * | 2003-02-28 | 2004-08-24 | Texas Instruments Incorporated | Etch back of interconnect dielectrics |
US7049052B2 (en) * | 2003-05-09 | 2006-05-23 | Lam Research Corporation | Method providing an improved bi-layer photoresist pattern |
US6989105B2 (en) * | 2003-06-27 | 2006-01-24 | International Business Machines Corporation | Detection of hardmask removal using a selective etch |
US20050230350A1 (en) * | 2004-02-26 | 2005-10-20 | Applied Materials, Inc. | In-situ dry clean chamber for front end of line fabrication |
US20060051966A1 (en) * | 2004-02-26 | 2006-03-09 | Applied Materials, Inc. | In-situ chamber clean process to remove by-product deposits from chemical vapor etch chamber |
KR20050122427A (ko) * | 2004-06-24 | 2005-12-29 | 동부아남반도체 주식회사 | 반도체 장치의 금속 배선 형성 방법 |
US20060118519A1 (en) * | 2004-12-03 | 2006-06-08 | Applied Materials Inc. | Dielectric etch method with high source and low bombardment plasma providing high etch rates |
KR100672661B1 (ko) * | 2004-12-28 | 2007-01-24 | 동부일렉트로닉스 주식회사 | 시모스 이미지 센서의 제조방법 |
US7253123B2 (en) * | 2005-01-10 | 2007-08-07 | Applied Materials, Inc. | Method for producing gate stack sidewall spacers |
DE102005030588B4 (de) * | 2005-06-30 | 2008-10-16 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum Reduzieren des Ätzschadens während der Herstellung von Kontaktdurchführungen und Gräben in Zwischenschichtdielektrika |
US7601651B2 (en) * | 2006-03-31 | 2009-10-13 | Applied Materials, Inc. | Method to improve the step coverage and pattern loading for dielectric films |
US7780865B2 (en) * | 2006-03-31 | 2010-08-24 | Applied Materials, Inc. | Method to improve the step coverage and pattern loading for dielectric films |
US20070287301A1 (en) | 2006-03-31 | 2007-12-13 | Huiwen Xu | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
US7807219B2 (en) * | 2006-06-27 | 2010-10-05 | Lam Research Corporation | Repairing and restoring strength of etch-damaged low-k dielectric materials |
CN101622376B (zh) * | 2007-01-30 | 2012-04-04 | 朗姆研究公司 | 使用超临界溶剂在半导体基片上形成金属膜的组合物和方法 |
US8617301B2 (en) * | 2007-01-30 | 2013-12-31 | Lam Research Corporation | Compositions and methods for forming and depositing metal films on semiconductor substrates using supercritical solvents |
US8058176B2 (en) * | 2007-09-26 | 2011-11-15 | Samsung Electronics Co., Ltd. | Methods of patterning insulating layers using etching techniques that compensate for etch rate variations |
EP2205775A1 (en) * | 2007-09-26 | 2010-07-14 | Silverbrook Research Pty. Ltd | Reactive ion etching process for etching metals |
US20090078674A1 (en) * | 2007-09-26 | 2009-03-26 | Silverbrook Research Pty Ltd | Reactive Ion Etching Process for Etching Metals |
DE102009039416A1 (de) * | 2009-08-31 | 2011-03-17 | Globalfoundries Dresden Module One Llc & Co. Kg | Abgesenktes Zwischenschichtdielektrikum in einer Metallisierungsstruktur eines Halbleiterbauelements |
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8771539B2 (en) | 2011-02-22 | 2014-07-08 | Applied Materials, Inc. | Remotely-excited fluorine and water vapor etch |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US8450212B2 (en) * | 2011-06-28 | 2013-05-28 | International Business Machines Corporation | Method of reducing critical dimension process bias differences between narrow and wide damascene wires |
US8771536B2 (en) | 2011-08-01 | 2014-07-08 | Applied Materials, Inc. | Dry-etch for silicon-and-carbon-containing films |
US8679982B2 (en) | 2011-08-26 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and oxygen |
US8679983B2 (en) | 2011-09-01 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and nitrogen |
US8927390B2 (en) | 2011-09-26 | 2015-01-06 | Applied Materials, Inc. | Intrench profile |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
WO2013070436A1 (en) | 2011-11-08 | 2013-05-16 | Applied Materials, Inc. | Methods of reducing substrate dislocation during gapfill processing |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
US9034770B2 (en) | 2012-09-17 | 2015-05-19 | Applied Materials, Inc. | Differential silicon oxide etch |
US9023734B2 (en) | 2012-09-18 | 2015-05-05 | Applied Materials, Inc. | Radical-component oxide etch |
US9390937B2 (en) | 2012-09-20 | 2016-07-12 | Applied Materials, Inc. | Silicon-carbon-nitride selective etch |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US8765574B2 (en) | 2012-11-09 | 2014-07-01 | Applied Materials, Inc. | Dry etch process |
US8969212B2 (en) | 2012-11-20 | 2015-03-03 | Applied Materials, Inc. | Dry-etch selectivity |
US8980763B2 (en) | 2012-11-30 | 2015-03-17 | Applied Materials, Inc. | Dry-etch for selective tungsten removal |
US9064816B2 (en) | 2012-11-30 | 2015-06-23 | Applied Materials, Inc. | Dry-etch for selective oxidation removal |
US9111877B2 (en) | 2012-12-18 | 2015-08-18 | Applied Materials, Inc. | Non-local plasma oxide etch |
US8921234B2 (en) | 2012-12-21 | 2014-12-30 | Applied Materials, Inc. | Selective titanium nitride etching |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
US9040422B2 (en) | 2013-03-05 | 2015-05-26 | Applied Materials, Inc. | Selective titanium nitride removal |
US8801952B1 (en) | 2013-03-07 | 2014-08-12 | Applied Materials, Inc. | Conformal oxide dry etch |
US10170282B2 (en) | 2013-03-08 | 2019-01-01 | Applied Materials, Inc. | Insulated semiconductor faceplate designs |
US20140271097A1 (en) | 2013-03-15 | 2014-09-18 | Applied Materials, Inc. | Processing systems and methods for halide scavenging |
US8895449B1 (en) | 2013-05-16 | 2014-11-25 | Applied Materials, Inc. | Delicate dry clean |
US9114438B2 (en) | 2013-05-21 | 2015-08-25 | Applied Materials, Inc. | Copper residue chamber clean |
US9493879B2 (en) | 2013-07-12 | 2016-11-15 | Applied Materials, Inc. | Selective sputtering for pattern transfer |
US9773648B2 (en) | 2013-08-30 | 2017-09-26 | Applied Materials, Inc. | Dual discharge modes operation for remote plasma |
US8956980B1 (en) | 2013-09-16 | 2015-02-17 | Applied Materials, Inc. | Selective etch of silicon nitride |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9236265B2 (en) | 2013-11-04 | 2016-01-12 | Applied Materials, Inc. | Silicon germanium processing |
US9576809B2 (en) | 2013-11-04 | 2017-02-21 | Applied Materials, Inc. | Etch suppression with germanium |
US9520303B2 (en) | 2013-11-12 | 2016-12-13 | Applied Materials, Inc. | Aluminum selective etch |
US9245762B2 (en) | 2013-12-02 | 2016-01-26 | Applied Materials, Inc. | Procedure for etch rate consistency |
US9117855B2 (en) | 2013-12-04 | 2015-08-25 | Applied Materials, Inc. | Polarity control for remote plasma |
US9287095B2 (en) | 2013-12-17 | 2016-03-15 | Applied Materials, Inc. | Semiconductor system assemblies and methods of operation |
US9263278B2 (en) | 2013-12-17 | 2016-02-16 | Applied Materials, Inc. | Dopant etch selectivity control |
US9190293B2 (en) | 2013-12-18 | 2015-11-17 | Applied Materials, Inc. | Even tungsten etch for high aspect ratio trenches |
US9287134B2 (en) | 2014-01-17 | 2016-03-15 | Applied Materials, Inc. | Titanium oxide etch |
US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
US9293568B2 (en) | 2014-01-27 | 2016-03-22 | Applied Materials, Inc. | Method of fin patterning |
US9385028B2 (en) | 2014-02-03 | 2016-07-05 | Applied Materials, Inc. | Air gap process |
US9499898B2 (en) | 2014-03-03 | 2016-11-22 | Applied Materials, Inc. | Layered thin film heater and method of fabrication |
US9299575B2 (en) | 2014-03-17 | 2016-03-29 | Applied Materials, Inc. | Gas-phase tungsten etch |
US9299537B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9299538B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9136273B1 (en) | 2014-03-21 | 2015-09-15 | Applied Materials, Inc. | Flash gate air gap |
US9903020B2 (en) | 2014-03-31 | 2018-02-27 | Applied Materials, Inc. | Generation of compact alumina passivation layers on aluminum plasma equipment components |
US9269590B2 (en) | 2014-04-07 | 2016-02-23 | Applied Materials, Inc. | Spacer formation |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9847289B2 (en) | 2014-05-30 | 2017-12-19 | Applied Materials, Inc. | Protective via cap for improved interconnect performance |
US9378969B2 (en) | 2014-06-19 | 2016-06-28 | Applied Materials, Inc. | Low temperature gas-phase carbon removal |
US9406523B2 (en) | 2014-06-19 | 2016-08-02 | Applied Materials, Inc. | Highly selective doped oxide removal method |
US9425058B2 (en) | 2014-07-24 | 2016-08-23 | Applied Materials, Inc. | Simplified litho-etch-litho-etch process |
US9496167B2 (en) | 2014-07-31 | 2016-11-15 | Applied Materials, Inc. | Integrated bit-line airgap formation and gate stack post clean |
US9378978B2 (en) | 2014-07-31 | 2016-06-28 | Applied Materials, Inc. | Integrated oxide recess and floating gate fin trimming |
US9159606B1 (en) | 2014-07-31 | 2015-10-13 | Applied Materials, Inc. | Metal air gap |
US9165786B1 (en) | 2014-08-05 | 2015-10-20 | Applied Materials, Inc. | Integrated oxide and nitride recess for better channel contact in 3D architectures |
US9659753B2 (en) | 2014-08-07 | 2017-05-23 | Applied Materials, Inc. | Grooved insulator to reduce leakage current |
US9553102B2 (en) | 2014-08-19 | 2017-01-24 | Applied Materials, Inc. | Tungsten separation |
US9355856B2 (en) | 2014-09-12 | 2016-05-31 | Applied Materials, Inc. | V trench dry etch |
US9355862B2 (en) | 2014-09-24 | 2016-05-31 | Applied Materials, Inc. | Fluorine-based hardmask removal |
US9368364B2 (en) | 2014-09-24 | 2016-06-14 | Applied Materials, Inc. | Silicon etch process with tunable selectivity to SiO2 and other materials |
US9613822B2 (en) | 2014-09-25 | 2017-04-04 | Applied Materials, Inc. | Oxide etch selectivity enhancement |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US9299583B1 (en) | 2014-12-05 | 2016-03-29 | Applied Materials, Inc. | Aluminum oxide selective etch |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US9502258B2 (en) | 2014-12-23 | 2016-11-22 | Applied Materials, Inc. | Anisotropic gap etch |
US9343272B1 (en) | 2015-01-08 | 2016-05-17 | Applied Materials, Inc. | Self-aligned process |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9373522B1 (en) | 2015-01-22 | 2016-06-21 | Applied Mateials, Inc. | Titanium nitride removal |
US9449846B2 (en) | 2015-01-28 | 2016-09-20 | Applied Materials, Inc. | Vertical gate separation |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US9881805B2 (en) | 2015-03-02 | 2018-01-30 | Applied Materials, Inc. | Silicon selective removal |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US9865484B1 (en) | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
US10062575B2 (en) | 2016-09-09 | 2018-08-28 | Applied Materials, Inc. | Poly directional etch by oxidation |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US9721789B1 (en) | 2016-10-04 | 2017-08-01 | Applied Materials, Inc. | Saving ion-damaged spacers |
US10062585B2 (en) | 2016-10-04 | 2018-08-28 | Applied Materials, Inc. | Oxygen compatible plasma source |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US9947549B1 (en) | 2016-10-10 | 2018-04-17 | Applied Materials, Inc. | Cobalt-containing material removal |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10043684B1 (en) | 2017-02-06 | 2018-08-07 | Applied Materials, Inc. | Self-limiting atomic thermal etching systems and methods |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10049891B1 (en) | 2017-05-31 | 2018-08-14 | Applied Materials, Inc. | Selective in situ cobalt residue removal |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
TWI716818B (zh) | 2018-02-28 | 2021-01-21 | 美商應用材料股份有限公司 | 形成氣隙的系統及方法 |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0484414A (ja) * | 1990-07-27 | 1992-03-17 | Sony Corp | ドライエッチング方法 |
JPH04142738A (ja) | 1990-10-04 | 1992-05-15 | Sony Corp | ドライエッチング方法 |
US5877032A (en) * | 1995-10-12 | 1999-03-02 | Lucent Technologies Inc. | Process for device fabrication in which the plasma etch is controlled by monitoring optical emission |
US5741396A (en) | 1994-04-29 | 1998-04-21 | Texas Instruments Incorporated | Isotropic nitride stripping |
JPH0936089A (ja) | 1995-07-19 | 1997-02-07 | Toshiba Corp | アッシング方法及びその装置 |
US5814563A (en) * | 1996-04-29 | 1998-09-29 | Applied Materials, Inc. | Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas |
KR19980064028A (ko) | 1996-12-12 | 1998-10-07 | 윌리엄비.켐플러 | 금속의 사후 에칭 탈플루오르 저온 공정 |
JPH11150101A (ja) * | 1997-11-18 | 1999-06-02 | Nec Corp | 半導体装置の製造方法 |
US6143476A (en) * | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
US5970376A (en) | 1997-12-29 | 1999-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer |
JP3501937B2 (ja) | 1998-01-30 | 2004-03-02 | 富士通株式会社 | 半導体装置の製造方法 |
US6340435B1 (en) * | 1998-02-11 | 2002-01-22 | Applied Materials, Inc. | Integrated low K dielectrics and etch stops |
US6352937B1 (en) * | 1998-04-27 | 2002-03-05 | Sony Corporation | Method for stripping organic based film |
US6105588A (en) | 1998-05-27 | 2000-08-22 | Micron Technology, Inc. | Method of resist stripping during semiconductor device fabrication |
US6040248A (en) | 1998-06-24 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | Chemistry for etching organic low-k materials |
US6194128B1 (en) | 1998-09-17 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Method of dual damascene etching |
US6245663B1 (en) * | 1998-09-30 | 2001-06-12 | Conexant Systems, Inc. | IC interconnect structures and methods for making same |
JP3657788B2 (ja) | 1998-10-14 | 2005-06-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6352918B1 (en) | 1998-11-24 | 2002-03-05 | United Microelectronics Corp. | Method of forming inter-metal interconnection |
US6184142B1 (en) * | 1999-04-26 | 2001-02-06 | United Microelectronics Corp. | Process for low k organic dielectric film etch |
US6037255A (en) | 1999-05-12 | 2000-03-14 | Intel Corporation | Method for making integrated circuit having polymer interlayer dielectric |
US6235453B1 (en) | 1999-07-07 | 2001-05-22 | Advanced Micro Devices, Inc. | Low-k photoresist removal process |
JP2001077086A (ja) * | 1999-08-31 | 2001-03-23 | Oki Electric Ind Co Ltd | 半導体装置のドライエッチング方法 |
WO2001029879A2 (en) | 1999-10-20 | 2001-04-26 | Mattson Technology, Inc. | Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing |
US6316354B1 (en) * | 1999-10-26 | 2001-11-13 | Lsi Logic Corporation | Process for removing resist mask of integrated circuit structure which mitigates damage to underlying low dielectric constant silicon oxide dielectric layer |
US20010024769A1 (en) * | 2000-02-08 | 2001-09-27 | Kevin Donoghue | Method for removing photoresist and residues from semiconductor device surfaces |
US6797633B2 (en) * | 2000-11-09 | 2004-09-28 | Texas Instruments Incorporated | In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning |
US6743732B1 (en) * | 2001-01-26 | 2004-06-01 | Taiwan Semiconductor Manufacturing Company | Organic low K dielectric etch with NH3 chemistry |
US6620733B2 (en) | 2001-02-12 | 2003-09-16 | Lam Research Corporation | Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics |
-
2001
- 2001-02-12 US US09/782,446 patent/US6893969B2/en not_active Expired - Fee Related
-
2002
- 2002-01-30 WO PCT/US2002/003138 patent/WO2002065528A2/en not_active Application Discontinuation
- 2002-01-30 AU AU2002243799A patent/AU2002243799A1/en not_active Abandoned
- 2002-01-30 KR KR1020037010535A patent/KR100887911B1/ko not_active IP Right Cessation
- 2002-01-30 CN CNB028081536A patent/CN1331198C/zh not_active Expired - Fee Related
- 2002-02-05 TW TW091102018A patent/TWI297179B/zh not_active IP Right Cessation
-
2004
- 2004-01-21 US US10/762,969 patent/US7105454B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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WO2002065528A3 (en) | 2003-02-13 |
WO2002065528A2 (en) | 2002-08-22 |
US6893969B2 (en) | 2005-05-17 |
CN1331198C (zh) | 2007-08-08 |
US7105454B2 (en) | 2006-09-12 |
AU2002243799A1 (en) | 2002-08-28 |
TWI297179B (en) | 2008-05-21 |
KR100887911B1 (ko) | 2009-03-12 |
US20020108929A1 (en) | 2002-08-15 |
KR20030093205A (ko) | 2003-12-06 |
US20050003676A1 (en) | 2005-01-06 |
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