CN1519913A - 形成金属导线的板及使用该板形成金属导线的方法 - Google Patents
形成金属导线的板及使用该板形成金属导线的方法 Download PDFInfo
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- CN1519913A CN1519913A CNA2003101235237A CN200310123523A CN1519913A CN 1519913 A CN1519913 A CN 1519913A CN A2003101235237 A CNA2003101235237 A CN A2003101235237A CN 200310123523 A CN200310123523 A CN 200310123523A CN 1519913 A CN1519913 A CN 1519913A
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000002184 metal Substances 0.000 title claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 38
- 239000010949 copper Substances 0.000 claims description 55
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 51
- 229910052802 copper Inorganic materials 0.000 claims description 51
- 239000004020 conductor Substances 0.000 claims description 47
- 238000009792 diffusion process Methods 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 238000005498 polishing Methods 0.000 claims description 29
- 238000005516 engineering process Methods 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 23
- 239000012774 insulation material Substances 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000010276 construction Methods 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- 150000003376 silicon Chemical class 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000003870 refractory metal Substances 0.000 claims description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 1
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- 230000008569 process Effects 0.000 abstract description 21
- 238000000206 photolithography Methods 0.000 abstract description 3
- 230000009467 reduction Effects 0.000 abstract description 2
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- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000000280 densification Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
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- 238000012545 processing Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 230000008485 antagonism Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
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- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12361—All metal or with adjacent metals having aperture or cut
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/249921—Web or sheet containing structurally defined element or component
- Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (19)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0085483A KR100475537B1 (ko) | 2002-12-27 | 2002-12-27 | 금속배선 형성용 원판 및 그를 이용한 금속배선 형성 방법 |
KR10-2002-0085482A KR100480477B1 (ko) | 2002-12-27 | 2002-12-27 | 금속배선 형성용 원판 및 그를 이용한 금속배선 형성 방법 |
KR85482/02 | 2002-12-27 | ||
KR85483/02 | 2002-12-27 | ||
KR85482/2002 | 2002-12-27 | ||
KR85483/2002 | 2002-12-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1519913A true CN1519913A (zh) | 2004-08-11 |
CN1271704C CN1271704C (zh) | 2006-08-23 |
Family
ID=32658671
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2003101235237A Expired - Fee Related CN1271704C (zh) | 2002-12-27 | 2003-12-24 | 形成金属布线的板及使用该板形成金属布线的方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7128946B2 (zh) |
CN (1) | CN1271704C (zh) |
TW (1) | TW200411791A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105529317A (zh) * | 2014-10-16 | 2016-04-27 | 台达电子工业股份有限公司 | 嵌入式封装装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006173460A (ja) * | 2004-12-17 | 2006-06-29 | Renesas Technology Corp | 半導体装置の製造方法 |
US7915735B2 (en) * | 2005-08-05 | 2011-03-29 | Micron Technology, Inc. | Selective metal deposition over dielectric layers |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5858869A (en) * | 1997-06-03 | 1999-01-12 | Industrial Technology Research Institute | Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers |
US6100184A (en) * | 1997-08-20 | 2000-08-08 | Sematech, Inc. | Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
JPH11224880A (ja) | 1998-02-05 | 1999-08-17 | Seiko Epson Corp | 半導体装置の製造方法 |
WO2001071776A2 (en) * | 2000-03-20 | 2001-09-27 | N.V. Bekaert S.A. | Materials having low dielectric constants and methods of making |
US6716754B2 (en) * | 2002-03-12 | 2004-04-06 | Micron Technology, Inc. | Methods of forming patterns and molds for semiconductor constructions |
-
2003
- 2003-07-11 US US10/617,473 patent/US7128946B2/en active Active
- 2003-07-14 TW TW92119133A patent/TW200411791A/zh unknown
- 2003-12-24 CN CNB2003101235237A patent/CN1271704C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105529317A (zh) * | 2014-10-16 | 2016-04-27 | 台达电子工业股份有限公司 | 嵌入式封装装置 |
CN105529317B (zh) * | 2014-10-16 | 2018-06-01 | 台达电子工业股份有限公司 | 嵌入式封装装置 |
Also Published As
Publication number | Publication date |
---|---|
US7128946B2 (en) | 2006-10-31 |
CN1271704C (zh) | 2006-08-23 |
US20040123921A1 (en) | 2004-07-01 |
TW200411791A (en) | 2004-07-01 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: MAGNACHIP CO., LTD. Free format text: FORMER OWNER: HYNIX SEMICONDUCTOR INC. Effective date: 20070518 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20070518 Address after: North Chungcheong Province Patentee after: Magnachip Semiconductor, Ltd. Address before: Gyeonggi Do, South Korea Patentee before: HYNIX SEMICONDUCTOR Inc. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20201019 Address after: Han Guozhongqingbeidao Patentee after: Key Foundry Co.,Ltd. Address before: Han Guozhongqingbeidao Patentee before: Magnachip Semiconductor, Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060823 |
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CF01 | Termination of patent right due to non-payment of annual fee |