CN1485893A - 封装基板制造方法及其结构 - Google Patents

封装基板制造方法及其结构 Download PDF

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CN1485893A
CN1485893A CNA031549411A CN03154941A CN1485893A CN 1485893 A CN1485893 A CN 1485893A CN A031549411 A CNA031549411 A CN A031549411A CN 03154941 A CN03154941 A CN 03154941A CN 1485893 A CN1485893 A CN 1485893A
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contact
welding
power supply
passive component
carrier
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CN1234158C (zh
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张文远
许志行
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Via Technologies Inc
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    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
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Abstract

本发明涉及一种封装基板制造方法及其结构,该制造方法至少包括:提供一承载器,其具有一表面以及多个接点,其中该些接点配置于表面;跨接至少一无源元件于该些接点之间,且无源元件具有多个焊接端,其分别电连接至该些接点;以及形成一金属层于该些焊接端的表面以及该些接点所暴露的表面,以利于后续引线键合工艺时,引线的两端可分别连接在芯片的一焊接垫以及无源元件的一焊接端上,以提高芯片封装工艺的合格率及可靠性。

Description

封装基板制造方法及其结构
技术领域
本发明涉及一种芯片封装方法及其结构,且特别是有关于一种运用于引线键合型态的封装基板制造方法及其结构。
背景技术
由于半导体技术的发展,在市场需求提高下,使得半导体产业不断地开发出更精密、更快速的电子元件,以目前半导体封装的技术而言,比如芯片构装的技术、芯片载板(chip carrier)的制作以及无源元件(passive component)的组装等,均在半导体产业中占有不可或缺的地位。
就芯片构装的技术而言,每一颗由晶片(wafer)切割所形成的裸芯片(die),例如以引线键合(wire bonding)或倒装芯片焊接(flip chip bonding)等方式,配置于一承载器(carrier)的表面,其中承载器例如为引线架(1eadframe)或基板(substrate),而芯片则具有多个焊接垫,使得芯片的焊接垫得以经由承载器的传输线路及接点,而电连接至外部的电子装置。此外,利用引线键合的芯片,其焊接垫与基板的接点作电连接之后,再形成一封胶材料将芯片及引线加以包覆,用来保护芯片以及引线,如此即完成一芯片封装工艺及其结构。
图1A~1C依序显示现有一种引线键合型态的芯片封装工艺的流程示意图。请参考图1A,首先提供一承载器110,其表面具有一芯片焊接区112,且承载器110的表面至少配置一电源接点116、一接地接点114以及一信号接点118。此外,电源接点116以及接地接点114位于芯片焊接区112的同一侧,而信号接点118位于电源接点116以及接地接点114的较远离芯片焊接区112的外侧。其中,电源接点116、接地接点114以及信号接点118例如由图案化的一引线层所构成,而引线层的表面还可覆盖图案化的一焊罩层140,且焊罩层140具有多个开口142,其分别暴露出电源接点116、接地接点114以及信号接点118的表面。另外,为了避免接点与外界空气产生氧化作用,承载器110的表面可藉由电镀的方式形成一金属层144,此金属层144例如为镍、金或其它合金,其覆盖于电源接点116、接地接点114以及信号接点118的所暴露的表面,以提高后续引线键合工艺中的可靠性。
请参考图1B,配置一芯片120于承载器110的表面,而芯片120以背面122贴附在芯片焊接区112上,且芯片120的有源表面124具有多个焊接垫126,其分别对应于电源接点116、接地接点114以及信号接点118。
请参考图1C,分别连接引线134、136、138的两端至芯片120的一焊接垫126以及其所对应的电源接点116、接地接点114以及信号接点118。此外,为了有效提高芯片封装结构100的电气特性,通常是利用表面安装技术(Surface Mount Technology,SMT)将小型无源元件130贴附在承载器110的表面,用来减少信号在切换时所产生的噪声串音干扰(crosstalk),并维持信号传输品质。其中,无源元件130例如为电感元件(inductor)或电容元件(capacitor),而无源元件130跨置于承载器110的电源接点116以及接地接点114之间,且无源元件130的两焊接端132a、132b分别连接至电源接点116以及接地接点114。
同样请参考图1C,值得注意的是,无源元件130例如配置在信号引线138的下方,且信号引线138可横跨于无源元件130的上方而不会接触到无源元件130的焊接端132a,因此可提高信号引线138的布设空间。然而,连接于焊接垫126以及电源接点116之间的引线136,必须先跨过无源元件130的上方,之后再焊接至电源接点116的表面上。由于引线136必须先拉长弧线,才能跨过无源元件130的上方,所以相对导致引线136本身的长度增加,而信号行经引线136的传输路径增长,将使芯片120的电气性能降低,且影响邻近引线的布设空间。
发明内容
有鉴于此,本发明的目的是提供一种封装基板制造方法,用来提高后续引线键合工艺的合格率以及可靠性。
为达本发明的上述目的,本发明提供一种封装基板制造方法,首先提供一承载器,此承载器的表面具有一芯片焊接区,且形成图案化的一引线层于承载器的表面,其中引线层具有一电源接点、一接地接点以及一信号接点,接着跨接至少一无源元件于电源接点以及接地接点之间,无源元件具有至少两焊接端,其分别电连接至电源接点以及接地接点。最后,形成一金属层于这些焊接端的表面以及电源接点、接地接点以及信号接点的所暴露的表面。
依照本发明的优选实施例所述,上述的金属层例如以电镀的方式所形成,且金属层的材料可选自于由镍、金及该等合金所组成群组的一种材料。此外,无源元件例如为电感元件或电容元件,且无源元件的焊接端可藉由表面安装技术(SMT)而分别焊接在电源接点以及接地接点的表面。
为让本发明的上述和其它目的、特征、和优点能更明显易懂,下文特举一优选实施例,并配合附图,作详细说明如下。
附图说明
图1A~1C依序显示现有一种引线键合型态的芯片封装工艺的流程示意图;
图2A~2C依序显示本发明一优选实施例的一种引线键合型态的芯片封装工艺的流程示意图。
附图标记说明
110   承载器                 112    芯片焊接区
114   接地接点               116    电源接点
118   信号接点               120    芯片
122   背面                   124    有源表面
126   焊接垫                 130    无源元件
132a  焊接端                 132b   焊接端
134   引线                   136    引线
138   引线                   140    焊罩层
142   开口                   144    金属层
210   承载器                 212    芯片焊接区
214   接地接点               216    电源接点
218   信号接点               220    芯片
222   背面                   224    有源表面
226a  焊接垫                 226b   焊接垫
226c  焊接垫                 230    无源元件
232a  焊接端                 232b   焊接端
236a  第一引线               236b   第一引线
238  第二引线    240    焊罩层
242  开口        244    金属层
具体实施方式
图2A~2C依序显示本发明一优选实施例的一种引线键合型态的芯片封装工艺的流程示意图。请参考图2A,首先提供一承载器210,此承载器例如为基板,其表面具有一芯片焊接区212,且承载器210的表面至少配置一电源接点216、一接地接点214以及一信号接点218。此外,电源接点216以及接地接点214位于芯片焊接区212的同一侧,且两者例如分别由环绕于芯片焊接区212的外围的一电源环(未显示)以及一接地环(未显示)的局部线段所形成,而信号接点218位于电源接点216以及接地接点214的较远离芯片焊接区212的外侧。其中,电源接点216、接地接点214以及信号接点218例如由图案化的一引线层所构成,而引线层的表面还可覆盖图案化的一焊罩层240,且焊罩层240具有多个开口242,其分别暴露出电源接点216、接地接点214以及信号接点218的表面。
同样请参考图2A,在本实施例中,跨接至少一无源元件230于电源接点216以及接地接点214之间,而无源元件230具有至少两焊接端232a、232b,其可藉由表面安装技术(SMT)而分别焊接在电源接点216以及接地接点214的表面,用来减少信号在切换时所产生的噪声串音干扰,并维持信号传输品质。其中,无源元件230例如为小型电感元件或电容元件,其焊接端的材料例如为锡铅合金。
接着请参考图2B,同时形成一金属层244于焊接端232a、232b的表面以及电源接点216、接地接点214及信号接点218的所暴露的表面,用来避免接点214、216、218与外界空气产生氧化的作用。其中,金属层244的材料例如为镍、金或其合金,其可藉由电镀的方式形成于焊接端232a、232b的表面以及接点214、216、218的所暴露的表面。另外,金属层244采用与金线键合性佳的金属材料,故可提高后续引线键合工艺的可靠性。
请参考图2C,配置一芯片220于承载器210的表面,而芯片220以背面222贴附在芯片焊接区212上,且芯片220的有源表面224具有多个焊接垫226,其分别对应于电源接点216、接地接点214以及信号接点218。
同样请参考图2C,为了缩短第一引线236a、236b的长度,本实施例直接将至少一第一引线236a的一端焊接在无源元件230的焊接端232a上,其中第一引线236a的两端可对应连接至芯片220的一焊接垫226a以及无源元件220的远离芯片220的焊接端232a,而另一第一引线236b的两端可对应连接至芯片220的另一焊接垫226b以及无源元件230的邻近芯片220的焊接端232b上或接地接点214上。由于外层的第一引线236a不须拉长弧线来跨过无源元件230的上方,而是直接焊接在无源元件230的焊接端232a上,因此外层的第一引线236a的长度将可有效的缩短,而信号行经第一引线236a的传输路径缩短,将使芯片220的电气性能提高,且增加邻近引线的布设空间。此外,第二引线238的两端可对应连接芯片220的又一焊接垫236c以及承载器210最外围的信号接点218,且第二引线238还可横跨于无源元件230的上方,而不会接触到无源元件230的任一焊接端232a、232b。
由以上的说明可知,本发明的封装基板制造方法先跨置至少一无源元件于承载器的电源接点以及接地接点之间,且无源元件的两焊接端分别连接电源接点以及接地接点,并同时形成一金属层于无源元件的焊接端以及电源接点、接地接点及信号接点的所暴露的表面。
综上所述,本发明的封装基板制造方法具有下列优点:
(1)利用电镀的方式,同时形成一金属层于无源元件的接点表面以及电源接点、接地接点及信号接点的所暴露的表面,以利于后续将引线的一端直接连接在无源元件的焊接端上,藉以提高芯片封装工艺的合格率以及可靠性。
(2)引线的一端可直接焊接在无源元件的一焊接端上,因此引线的长度将可有效的缩短,而信号行经引线的传输路径缩短,将提高芯片的电气性能,并增加邻近引线的布线空间。
虽然本发明已结合一优选实施例披露如上,然其并非用来限定本发明,本领域内的技术人员,在不脱离本发明的精神和范围内,当可作少许的更动与润饰,因此本发明的保护范围以权利要求所界定的为准。

Claims (9)

1.一种封装基板制造方法,至少包括:
提供一承载器,其具有一表面以及多个接点,其中该些接点配置于该表面;
跨接至少一无源元件于该些接点之间,且该无源元件具有多个焊接端,其分别电连接至该些接点;以及
形成一金属层于该些焊接端的表面以及该些接点所暴露的表面。
2.如权利要求1所述的封装基板制造方法,其中在提供该承载器之后,还包括形成图案化的一焊罩层于该承载器的该表面,且该焊罩层暴露出该些接点的表面。
3.如权利要求1所述的封装基板制造方法,其中该金属层以电镀的方式所形成。
4.如权利要求1所述的封装基板制造方法,其中该金属层的材料选自于由镍、金及该等合金所组成群组的一种材料。
5.如权利要求1所述的封装基板制造方法,其中该无源元件为电感元件以及电容元件其中之一。
6.一种封装基板结构,适于承载引线键合型态的一芯片,该封装基板结构至少包括:
一承载器,具有一表面、一电源接点、一接地接点以及一信号接点,该表面具有一芯片焊接区,且该电源接点、该接地接点以及该信号接点均配置于该芯片焊接区之外的区域;以及
至少一无源元件,跨置于该承载器的该电源接点以及该接地接点之间,该无源元件具有至少两焊接端,其分别电连接至该电源接点以及该接地接点;以及
一金属层,覆盖于该些焊接端的表面以及该电源接点、该接地接点以及该信号接点的所暴露的表面。
7.如权利要求6所述的封装基板结构,还包括图案化的一焊罩层,配置于该承载器的该表面,且该焊罩层暴露出该电源接点、该接地接点以及该信号接点的表面。
8.如权利要求6所述的封装基板结构,其中该无源元件为电感元件以及电容元件其中之一。
9.如权利要求6所述的封装基板结构,其中该金属层的材料选自于由镍、金及该等合金所组成群组的一种材料。
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* Cited by examiner, † Cited by third party
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CN104576589A (zh) * 2013-10-11 2015-04-29 联发科技股份有限公司 半导体封装
US9806053B2 (en) 2013-10-11 2017-10-31 Mediatek Inc. Semiconductor package
US10163767B2 (en) 2013-10-11 2018-12-25 Mediatek Inc. Semiconductor package
CN109411462A (zh) * 2018-10-31 2019-03-01 广东美的制冷设备有限公司 高集成功率模块和电器
CN115831935A (zh) * 2023-02-15 2023-03-21 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576589A (zh) * 2013-10-11 2015-04-29 联发科技股份有限公司 半导体封装
US9806053B2 (en) 2013-10-11 2017-10-31 Mediatek Inc. Semiconductor package
US10163767B2 (en) 2013-10-11 2018-12-25 Mediatek Inc. Semiconductor package
CN109411462A (zh) * 2018-10-31 2019-03-01 广东美的制冷设备有限公司 高集成功率模块和电器
CN115831935A (zh) * 2023-02-15 2023-03-21 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法

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