CN1463041A - 半导体集成电路装置 - Google Patents
半导体集成电路装置 Download PDFInfo
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Abstract
一种半导体集成电路装置,防止半导体集成电路装置的无用配线的交叉,且实现LSI配线的低阻抗。该半导体集成电路装置具有和内部含有多个电阻元件或晶体管及电容元件等的电路部件2电导通的焊盘3以及和焊盘3电导通的保护电路5,焊盘3和保护电路5邻接形成单元6,电路部件2的周边配置多个单元6。并且,单元6的外侧环绕供给电源电压Vcc的最上层金属7,且利用电路部件2和单元6之间的空间等,在整个该空间宽幅地形成供给接地电压GND的最下层金属8,从而实现LSI1整体的低阻抗。
Description
技术领域
本发明涉及半导体集成电路装置中的保护电路,特别是省略半导体集成电路装置内部不需要的配线,并且实现配线的低阻抗化的电路。
背景技术
一般的,半导体集成电路装置中,当由外部施加过大的输入电压至输入端子时,有可能破坏内部电路,为了将其破坏防患于未然,内装有输入保护电路。
例如,在多晶硅栅的MOS型集成电路中,设有如图6所示的保护电路80。该保护电路80由串联连接两个保护二极管D3、D4构成。将该保护二极管D3的阴极侧连接Vcc(电源电压),保护二极管D4的阳极侧与GND(接地电压)连接。而后,两个保护二极管D3、D4的连接点83连接输入端子81,由连接点83取出输出端子82连接至内部电路。
一般地,在保护电路80的输入端子81会由外部通过静电等输入过大的电压。在此,施加比Vcc还高的电压时,保护二极管D3导通,固定接点83的电压电平,从而抑制自输出端子82向前方的内部电路施加高电压。另外,在施加了低于GND电平的负的高电压时,保护二极管D4导通,固定接点83的电压电平,从而抑制自输出端子82向前方的内部电路施加负的高电压。
图7是显示LSI100内具备了保护电路80的现有半导体集成电路装置的平面图。同图中,作为一例,显示了在LSI100上配置了3个电路部件101A~101C和16个焊盘102A~102P及16个保护电路104A~104P的装置。在此,所谓电路部件是指其内部含有多个电阻元件或晶体管、电容元件等的电路。
各焊盘102A~101P介由电路部件101A~101C和配线103连接。另外,各保护电路104A~104P介由配线105连接,与各焊盘102A~102P分别一一电导通。
此时,保护电路104A~104P的各保护电路是内部具备了图6所示的保护电路80的电路,该保护电路104A~104P为了和LSI 100上形成的Vcc配线及GND配线电导通,必须有上下两条配线(无图示)。另外,该保护电路104A~104P的1个电路所占的面积是焊盘102A~102P的1个所占的面积的大约1/3~1/2左右。
通常,决定图7所示的半导体集成电路装置的图案配置时,由以下的顺序决定各自的元件配置。
第一,将3个电路部件101A~101C在LSI 100上大略中央位置配置。该3个电路部件的位置关系考虑芯片尺寸或其功能面来决定。在图7中,相对于面积最大的电路部件101C,平行配置具有相同面积的两个电路部件101A、101B。
第二,将焊盘102A~102P在3个电路部件101A~101C的周围进行大概等间隔地配置。
第三,将保护电路104A~104P配置在LSI100内。此时,由于保护电路104A~104P的1个电路所占的面积比焊盘102A~102P的1个所占的面积小,故各保护电路104A~104P就利用上述电路部件101A~101C和焊盘102A~102P形成的间隙即所谓死角进行配置。
其后,为了使电路部件101A~101C和焊盘102A~102P电导通配置配线103,为了使各焊盘102A~102P和各保护电路104A~104P各自电导通而配置配线105。并且,保护电路104A~104P还另外配置和Vcc配线、GND配线导通的配线。
上述的技术在例如以下专利文献中所述。
专利文献特开2001-127249号公报。
但是,要配置上述的图7所示的现有半导体集成电路装置的各元件,可列举以下的问题。
第一,由于利用LSI 100上所谓的死角配置保护电路104A~104P,会产生配线103和配线105交叉的位置。例如,着眼于图7的LSI 100右下端的焊盘102A、保护电路104A,则配线103和配线105就交叉。
这样,当配线103和配线105交叉时,就可能产生未预期的故障(例如,信号线短路或相互干扰)。并且,这些配线103、105和用于使保护电路104A~104P分别与Vcc配线和GND配线导通的配线产生复杂的相互缠绕。由此,会使配线间的层间绝缘膜的膜厚进一步加厚,或配线通孔的数量必须在预定以上,产生在配线图案设计阶段不可预想的各种弊端。
第二,近年的半导体集成电路装置为层积结构,其结果,制造工艺也变得复杂。由此,存在下述缺点,在半导体集成电路装置中,配线数增大,配线阻抗变高,不能充分发挥LSI 100的特性。
发明内容
由此,本发明是鉴于上述缺点而发明的装置,本发明提供一种半导体集成电路装置,其包括:和电路部件电连接的焊盘、和该焊盘电连接的保护电路、向该保护电路供给第一电位的第一金属配线、向该保护电路供给与上述第一电位不同的第二电位的第二金属配线。而且,在本发明中,焊盘和保护电路相互邻接配置,或焊盘和保护电路由一个单元构成,将多个该单元配置在电路部件的周边。另外,在本发明中,第一金属配线配置在多个单元的外侧,在多个电路部件和多个单元之间的整个区域形成第二金属配线,通过提供该半导体集成电路装置实现GND配线的低阻抗化。
附图说明
图1是显示本发明的半导体集成电路装置的实施例的平面图;
图2是显示本发明的半导体集成电路装置的实施例的立体图;
图3是显示本发明的半导体集成电路装置的实施例的平面图;
图4是显示本发明的半导体集成电路装置的实施例的剖面图;
图5是显示本发明的半导体集成电路装置的实施例的剖面图;
图6是显示保护电路的电路图;
图7是显示现有半导体集成电路的平面图。
具体实施方式
参照图1~图5说明本发明的实施例。
图1是本发明的半导体集成电路装置(以下称LSI1)的平面图。
在电路部件2的周围形成焊盘3,电路部件2和焊盘3介由配线4电导通。此时,所谓电路部件2是其内部含有多个电阻元件或晶体管、电容元件等的电路。
配线4是连接电路部件2和焊盘3两者的金属配线。和焊盘3邻接配置的保护电路5,作为等价电路和图6所示的保护电路80相同,由串联连接的两个晶体管构成。
在本实施例中,说明在大致中央配置3个电路部件2和16个焊盘3的装置。另外,这里电路部件2和焊盘3的数量没有特别的限定。
在本实施例中,和各焊盘3邻接形成防静电破坏用的各保护电路5,将这些同样作为单元6处理。
图1所示的半导体集成电路装置为积层结构,其内部形成多个金属配线。在本实施例中,该多个金属配线中最上层金属7和最下层金属8形成于规则排列的多个单元6的外侧及内侧。在此,向最上层金属7上供给Vcc(电源电压),向最下层金属8上供给GND(接地电压)。另外,最上层金属7形成Vcc配线,最下层金属8形成GND配线。并且,Vcc配线和GND配线向电路部件2和保护电路5供给Vcc、GND。
该最下层金属8在未作为该LSI1的电路部件2和单元6之间的电路区域利用的整个空间宽幅形成。具体的,该最下层金属8直至接近电路部件2及多个单元6的位置无间隙形成,只要不产生短路即可。
另外,根据需要,在电路部件2和单元6之间形成最下层金属8的基础上,在邻接的各单元6之间未利用的空间,也可贯穿整个该空间作为GND配线形成最下层金属8。根据需要,在电路部件2和单元6之间形成最下层金属8的基础上,在邻接的各电路部件2之间未利用的空间,也可贯穿整个该空间作为GND配线形成最下层金属8。
图2是由斜上方看图1的LSI1的立体图。为了便于说明,省略了图1的配线4。层闸绝缘膜9是LSI1的表面上形成的层间绝缘膜。另外,各单元6是沿LSI的各边按各边形成同一方向、维持一定规则性形成的焊盘3和保护电路5的一体化物。
在此,最上层金属7采用铝喷射形成,在保持一定宽度不变的情况下沿多个单元6的外侧环绕,并和各保护电路5外侧的二极管D1连接。
这样,最上层金属7沿多个单元6外侧环绕形成,谋求该最上层金属7宽度的增大,以实现和该最上层金属7连接的Vcc配线的低阻抗化。
另外,最下层金属8和最上层金属7同样采用铝喷射形成,图1中如上所述,在多个各电路部件2和多个各单元6之间的整个空间宽幅形成。并且,该最下层金属8和各保护电路5的内侧的二极管D2连接。
这样,形成GND配线的最下层金属8在多个单元6的内侧宽幅形成,谋求最下层金属8的宽度扩大,以实现和该最下层金属8连接的GND配线的低阻抗化。
图3是将单元6放大的平面图。
最上层金属7维持一定宽度不变,沿单元6的外侧在集成电路芯片的周边形成,是和保护电路5的二极管D1的表面连接的金属配线。
另外,最下层金属8是在单元6的内侧形成的宽的金属配线。在此,该最下层金属8比层闸绝缘膜9深,在后述的氧化膜24的表面形成。
单元6由焊盘3和保护电路5构成。焊盘8连续地形成面积大的矩形焊盘设置部3a和面积小的矩形焊盘环绕部3b。
该焊盘设置部3b通过配线4和图1所示的电路部件2电连接,在其上形成接合线(无图示)。焊盘环绕部3b和焊盘设置部3a连续形成,与其下形成的保护电路5直接连接。保护电路5由串联连接的两个二极管D1、D2构成。
最下层金属8和二极管D2的最下层连续,并且贯穿单元6及其内侧相对的电路部件2之间的整个空间宽幅形成。
以下,参照图4、图5说明上述单元6的剖面图。图4是图3的X1-X2线的剖面图,图5是图3的Y1-Y2线的剖面图。但是,图4、图5为了说明方便,显示比图3的同一构成要素放大的图。
以下说明图4。
在P型半导体衬底20上形成N型半导体层21。半导体层21通过元件分离层23、23a电分割。元件分离层23a是分隔保护电路5的两个二极管D1、D2的元件分离层。即,元件分离层23a的前侧配置二极管D1,在后侧配置二极管D2。氧化膜24是在半导体层21的主表面通过热氧化形成的硅氧化膜。
层间绝缘膜9是该氧化膜24上形成的层间绝缘膜,在其内部形成由金属形成的多个金属层(例如图中的最下层金属8、26及中间层金属27)和电导通该金属层的多个接触孔28A、28B。
其次说明层间绝缘膜9内部的各金属层等。在氧化膜24表面所希望的位置形成最下层金属26,和作为保护电路5的二极管D1、D2的接点接触。在此,所谓最下层金属26是和图3的最下层金属8连续的同一平面上的金属配线,是保护二极管D2内的最下层金属。
最下层金属26介由接触孔28A、中间层金属27、接触孔28B和焊盘3导通。在此,层间绝缘膜9内的金属层展示了2层(最下层金属26和中间层金属27)的例子,但在本实施例中其金属层数没有限制。图4中位于左边的最下层金属8是单元6外的最下层金属8,延伸至邻接的和另外的单元6间的元子分离层23的上方。
焊盘3在层间绝缘层9的表面所希望的位置形成,在焊盘设置部3a上形成接合线29。在此,在该焊盘设置部3a下没有特别限定,即使设置深沟道等结构也没有什么问题。
形成Vcc配线的最上层金属7在保护电路5外侧的层间绝缘膜9上形成,具有一定的宽度。
在本实施例中,图1、图2的最上层金属7和焊盘3也包括由同一喷射形成的情况,此时,该焊盘3和最上层金属7有相同的膜厚。另外,也可将最上层金属7和该焊盘3分别形成,并使其膜厚不同。
以下说明图5。
P型的半导体衬底20上形成的半导体层21由多个元件分离层23及23a电分割。通过该元件分离层23a分离二极管D1和二极管D2,在该半导体层21的主表面覆盖氧化膜24。
两二极管D1、D2都具有由半导体层21的主表面扩散形成的P层30A、30B。该P层30A是二极管D1的P型扩散层,P层30B是二极管D2的P型扩散层。
最下层金属26A、26B、26C是同一平面(相同金属层)上的金属配线,在氧化膜24上形成,为了和作为二极管D1、D2的N型半导体层21及P型扩散层的P层30A、30B接触,在该氧化膜24上各自形成图案。
在此,最下层金属26A是将二极管D1的P层30A和二极管D2的N层电连接的金属配线。该最下层金属26A介由接触孔28A与中间金属层27连接,该中间金属层27介由另外的接触孔28B与焊盘3的环绕部3b连接。
另外,最下层金属26B是和二极管D1的N层连接的金属配线,同样的,介由接触孔28A、中间金属层27、接触孔28B和层间绝缘膜9上形成的最上层金属7电连接。
另外,最下层金属26C是和二极管D2的P层30B电连接的金属配线,在该最下层金属26C中二极管D2的外侧(图中右侧),延伸至接近和该单元6邻接的另一单元6的位置。另外,介由最上层金属7向最下层金属26B供给电源电压Vcc,向最下层金属26C供给接地电压GND。
在此,分别向构成上述的各保护电路的各二极管D1和各二极管D2供给接地电压GND及电源电压Vcc的GND配线及Vcc配线(无图示)与各电路部件2连接。
如上所述,在本实施例中,将多个具有图4、图5剖面的图3的单元6整齐地配置,形成图1、图2所示的半导体集成电路装置。
在此,在图4、图5中,在将最上层金属7和焊盘3由另外的工序形成时,也可将最上层金属7和焊盘3形成不同的膜厚。例如,在Vcc配线的阻抗特别低时,最上层金属7的膜厚与焊盘3的膜厚比也可极端地厚(例如为其2倍左右)。
如上所述,本发明具有以下效果。
由于焊盘3和保护电路5是成为一体的单元6,故不需要连接焊盘3和保护电路5的配线。由此,单元6和各电路部件2由一条配线连接,不产生无用配线间的交叉,可降低短路等故障的可能性。另外,可省略由另外的途径形成现有技术存在的将保护电路连接在电源电压Vcc、接地电压GND上的金属配线的工序。
另外,由于焊盘3和保护电路5是成为一体的单元6,故只要在图案设计阶段,制作一次相同的部件,则以后只需多个复制即可。但是,在现有技术中,需要将各保护电路104A-104P配置在LSI 100内的死角的步骤。因此,在本发明中,由已经形成一体的单元6处理,故可省去这些无用的步骤,提高工作效率。可以大大缩短由设计到完成的时间。
另外,因为没有保护电路用的配线和信号用配线的交叉,故可以进行非常高性能的信号配线。
并且,在多个各单元6的内侧,以设计上可能大的最下层金属8的宽度形成最下层金属8,可以将GND配线的阻抗设定得很低。
另外,形成Vcc配线的最上层金属7沿多个各单元的外侧形成,且由于很大地形成该最上层金属7的宽度,故可以将Vcc配线的阻抗设定得很低。并且,通过设计上可能厚地形成最上层金属7的膜厚,可以更低地设定Vcc配线的阻抗。
另外,通过根据需要选择实施在单元6的外侧环绕上述最上层金属7、较厚地形成该最上层金属7的膜厚和在单元6的内侧环绕最下层金属8并尽可能大地形成该最下层金属8的宽度,或同时实施这些,可具有更加降低本发明的半导体集成电路装置配线阻抗的相乘效果。
在本发明中,就整齐配置图1的单元6的情况进行了说明。此时,所谓整齐是指在LSI的内侧配置与GND配线连接的、最下层金属26c连接的二极管2,在LSI的外侧配置与Vcc配线连接的中间层金属27连接的二极管D1。另外,将焊盘和保护电路相互邻接配置的情况,或等间隔配置焊盘和保护电路一体化的各单元6的情况也含在本发明中。
在本实施例中,说明了在单元6外侧的最上层金属7连接电源电压Vcc、在内侧最下层金属8上供给接地电压GND的装置,相反的在最上层金属7供给接地电压,在最下层金属8供给电源电压Vcc也可以。此时,保护电路二极管的朝向和上述的实施例相反。
另外,在本发明的实施例中,展示了是保护电路5是二极管时的例子,也可以是MOS晶体管、双极性晶体管、PIN二极管和箝位电路等。
采用本发明的半导体集成电路装置,由于焊盘和保护电路相互邻接配置,或焊盘和保护电路单元化,在电路部件的周边配置多个,故可以防止配线间交叉并防止对电路特性的恶劣影响。另外,如采用本发明的半导体集成电路装置,通过利用电路部件和单元之间的空间等,在整个该空间宽幅地形成GND配线,可以实现接地配线的低阻抗化。
Claims (14)
1.一种半导体集成电路装置,其特征在于,包括:电路部件;和上述电路部件电连接的焊盘;和上述焊盘电连接的保护电路;向上述保护电路供给第一电位的第一金属配线;向上述保护电路供给和上述第一电位不同的第二电位的第二金属配线,沿上述电路部件的周边互相邻接配置上述焊盘和上述保护电路,在上述焊盘和上述保护电路外侧配置上述第一金属配线,上述第二金属配线形成在多个上述电路部件和多个上述焊盘之间的整个区域。
2.如权利要求1所述的半导体集成电路装置,其特征在于:所述多个电路部件相互之间的区域也形成有上述第二金属配线。
3.如权利要求1所述的半导体集成电路装置,其特征在于:在上述多个单元相互之间的区域也形成有上述第二金属配线。
4.如权利要求1所述的半导体集成电路装置,其特征在于:上述第一金属配线和上述第二金属配线以不同的配线层形成。
5.如权利要求1所述的半导体集成电路装置,其特征在于:上述保护电路具有串联连接的第一二极管及第二二极管。
6.如权利要求1所述的半导体集成电路装置,其特征在于:具有向上述第一二极管的阴极供给电源电压的电源配线和向上述第二二极管的阳极供给接地电压的接地配线。
7.如权利要求6所述的半导体集成电路装置,其特征在于:由最上层金属形成上述电源配线,由最下层金属形成上述接地配线。
8.一种半导体集成电路装置,其特征在于,包括:电路部件;和上述电路部件电连接的焊盘;和上述焊盘电连接的保护电路;向上述保护电路供给第一电位的第一金属配线;向上述保护电路供给和上述第一电位不同的第二电位的第二金属配线,上述焊盘和上述保护电路由相互邻接配置的一个单元构成,在上述电路部件的周边配置多个该单元,同时,在上述多个单元的外侧配置上述第一金属配线,在多个上述电路部件和上述多个单元之间的整个区域形成上述第二金属配线。
9.如权利要求8所述的半导体集成电路装置,其特征在于:在上述多个电路部件相互间的区域也形成上述第二金属配线。
10.如权利要求8所述的半导体集成电路装置,其特征在于:在上述多个单元相互间的区域也形成上述第二金属配线。
11.如权利要求8所述的半导体集成电路装置,其特征在于:上述第一金属配线和上述第二金属配线由不同的配线层形成。
12.如权利要求8所述的半导体集成电路装置,其特征在于:上述保护电路具有串联连接的第一二极管及第二二极管。
13.如权利要求12所述的半导体集成电路装置,其特征在于:具有向上述第一二极管的阳极供给电源电压的电源配线和向上述第二二极管的阴极供给接地电压的接地配线。
14.如权利要求13所述的半导体集成电路装置,其特征在于:由最上层金属形成上述电源配线,由最下层金属形成上述接地配线。
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CN100428462C (zh) * | 2004-06-01 | 2008-10-22 | 松下电器产业株式会社 | 半导体集成电路器件 |
CN1971912B (zh) * | 2005-11-25 | 2011-07-06 | 松下电器产业株式会社 | 半导体集成电路及其设计方法 |
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CN1930676B (zh) * | 2004-03-12 | 2010-06-16 | 罗姆股份有限公司 | 半导体装置 |
JP5728171B2 (ja) * | 2009-06-29 | 2015-06-03 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2011171680A (ja) | 2010-02-22 | 2011-09-01 | Panasonic Corp | 半導体集積回路装置 |
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TW200305272A (en) * | 2002-03-29 | 2003-10-16 | Sanyo Electric Co | Semiconductor integrated circuit device |
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CN100428462C (zh) * | 2004-06-01 | 2008-10-22 | 松下电器产业株式会社 | 半导体集成电路器件 |
CN1971912B (zh) * | 2005-11-25 | 2011-07-06 | 松下电器产业株式会社 | 半导体集成电路及其设计方法 |
CN102222659B (zh) * | 2005-11-25 | 2012-10-31 | 松下电器产业株式会社 | 半导体集成电路 |
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