CN1447420A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

Info

Publication number
CN1447420A
CN1447420A CN03120784A CN03120784A CN1447420A CN 1447420 A CN1447420 A CN 1447420A CN 03120784 A CN03120784 A CN 03120784A CN 03120784 A CN03120784 A CN 03120784A CN 1447420 A CN1447420 A CN 1447420A
Authority
CN
China
Prior art keywords
coating
oxide skin
layer
semiconductor device
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN03120784A
Other languages
English (en)
Inventor
张国华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of CN1447420A publication Critical patent/CN1447420A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Abstract

一种半导体器件的制造方法，此方法先定义一基底，以使此基底包括一周边区域与一核心区域。之后，将基底的周边区域遮蔽住，再于基底的核心区域之上成长第一介电层。接着，于第一介电层之上沉积一第一多晶硅层，以用以形成至少一栅极结构。之后，于第一多晶硅层上成长第一氧化物层，再于第一氧化物层上沉积氮化物层。接着，植入氧离子至氮化物层中，再移除基底的周边区域的遮蔽。之后，于氮化物层上成长第二氧化物层，其中第二氧化物层的成长速率因氮化物层中所植入的氧离子而增加成长速率。

Description

半导体器件的制造方法
技术领域
本发明是关于一种半导体的制造方法，且特别是关于一种在氮化物层上形成氧化层的制造方法。
背景技术
在闪存器件中，器件的基底上通常具有两种晶体管。第一种晶体管为用以储存数据的快闪存储单元。此快闪存储元件包括多个相邻的快闪存储单元所构成的一内存数组。此内存数组有时可以称之为闪存器件的「核心(core)」。第二种晶体管为用于闪存器件的各种电路的传统金属-氧化物-硅化物晶体管(简称MOS晶体管)例如是读出放大器(sense amplifier)及电荷泵(charge pump)等。MOS晶体管一般位于闪存数组的周围或是装置基底的「周边(peripheral)」区域上。
快闪存储单元与传统的MOS晶体管在快闪存储单元中具有结构上的差异。快闪存储单元包括额外的多晶硅栅极，此多晶硅闸称为「浮栅(floating gate)」，其位于基底与第二多晶硅栅极之间。此第二多晶硅栅极为快闪存储单元的「控制闸(control gate)」。快闪存储单元的控制闸通过氧化物-氮化物-氧化物层(简称ONO层)而与浮栅分离。此ONO层包括第一氧化物层、氮化物层及第二氧化物层。此第一氧化物层经过高温制作工艺而成长于浮栅之上。氮化物层沉积于前述第一氧化物层之上。第二氧化物层成长于氮化物层之上。对MOS晶体管而言，其传统栅极结构中并不包括浮栅及「第二多晶硅栅极」。即使MOS晶体管与快闪存储单元有结构上的差异，但是，在闪存器件的制造过程中，其二者几乎是同时形成的。
在制造的过程中，ONO层的顶层，亦即是第二氧化物层的厚度难以控制，此因部分第二氧化物层会被后续制造步骤中所使用的某些化学溶液侵蚀，例如是在定义核心区域或蚀刻周边区域之际，使用氟化氢(hydrogen-fluoride，HF)溶液所造成的侵蚀。公知，氟化氢溶液非常容易侵蚀氧化物层。公知一种解决此问题的方法，形成较厚的第二氧化物层以补偿后续制造步骤中所所造成的层损失。然而，此公知的解决方法对在氮化物层上成长氧化物层的公知技术而言，为困难的且耗时的。因此，公知的制造流程需要花费额外的时间、能量、资源等来增加第二氧化物层的厚度。另外，如果第二氧化物层在后续的制造步骤中不是以预设的方法或速率被蚀刻时，则ONO层将会大于预期的厚度，使得在形成控制闸的期间，部分的ONO层无法依照设计而完全被移除，而形成一个ONO「栅栏」影响后续的制作工艺。
发明内容
本发明提出一种半导体器件的制造方法，此方法先定义一基底，以使此基底包括一周边区域与一核心区域。之后，将基底的周边区域遮蔽住，再于基底的核心区域之上成长第一介电层。接着，于第一介电层之上沉积一第一多晶硅层，以用以形成至少一栅极结构。之后，于第一多晶硅层上成长第一氧化物层，再于第一氧化物层上沉积氮化物层。接着，植入氧离子至氮化物层中，再移除基底的周边区域的遮蔽。之后，于氮化物层上成长第二氧化物层，其中第二氧化物层的成长速率因氮化物层中所植入的氧离子而增加成长速率。
另外，本方法也包括在氧离子的植入步骤之后，进行清除该氮化物层的步骤。
再者，本方法还包括在成长第二氧化物层的同时，于基底的周边区域上成长栅氧化物。
另外，本发明再提出一种半导体器件的制造方法，此方法先定义一基底，再于基底的核心区域之上成长第一介电层。接着，于第一介电层之上沉积一第一多晶硅层，以用以形成至少一栅极结构。之后，于第一多晶硅层上成长第一氧化物层，再于第一氧化物层上沉积氮化物层。接着，植入氧离子至氮化物层中。之后，于氮化物层上成长第二氧化物层，其中第二氧化物层的成长速率因氮化物层中所植入的氧离子而增加成长速率。
本发明的其它目的及优点将说明如下，且可以明显的从说明书中得知或由本发明的实际操作中习得。本发明的目的及优点可以由权利要求所特别指出的构件及结合而了解及达成。
虽然本发明可由上述说明及下列叙述的示范及说明中得知，然其并非如同权利要求以限定本发明。
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合所附图式，作详细说明如下。
附图说明
图1至图3所示为本发明的制造流程的剖面示意图。图式标记说明：
10：基底
12：第一介电层
14：多晶硅层
16：第一氧化物层
18：氮化物层
22：第二氧化物层
24：ONO层
具体实施方式
配合图式进行说明的实例用以对本发明的具体实例进行详细说明。而且，在本说明书中所提及的标号与图式中所使用的标号一致。
图1至图3所示为本发明的制造流程的剖面示意图。请参照图1所示，基底10被定义成包括一个周边区域(未图标)及一个核心区域(部分被图标)。以光阻(未图标)遮蔽基底的周边区域，并暴露出基底10的核心区域。于基底10的核心区域之上成长第一介电层12。此第一介电层12也可以为公知的由二氧化硅所构成的穿隧氧化物。于前述第一介电层12之上沉积第一多晶硅层14。此第一多晶硅层14将被图案化及蚀刻，以形成闪存数组中快闪存储单元的浮栅。
本发明的方法于第一多晶硅层14之上形成ONO层结构。请参照图2所示，第一氧化物层16形成在于第一多晶硅层14之上。此第一氧化物层16用以作为ONO层的底层，且其形成方法于温度接近摄氏700度至摄氏850度左右的情形下，利用SiH2Cl2及N2O的混合物而形成。由于第一氧化物层16于高温下成长，因此，其为公知的高温氧化物(High TemperatureOxide，HTO)。
接着，于第一氧化物层16之上沉积氮化物层18。此氮化物层18可以使用传统的低压化学气相淀积(low-pressure chemical vapordeposition，LPCVD)法，在温度接近摄氏600度至摄氏750度左右的情形下，利用SiH2Cl2及NH3的混合物沉积而成。之后，进行氧离子植入步骤，以将氧离子(O2)植入氮化物层18中。一般来说，在形成快闪存储单元的ONO层时，必需在氮化物层上成长氧化层，然而，在氮化物层上并无法以非常有效的方式成长氧化层。此植入的氧离子可以促进氮化物层上的氧化物的成长。所植入的氧离子的剂量视所需而定。在一较佳实施例中，氧离子的植入剂量可以增加氧化物的成长速率，其所增加的厚度为60埃。在前述离子植入步骤之后，可选择性地进行清除步骤，以清除氮化物层18表面被离子植入所伤害的部分。由于氮化物可以抵抗氟化氢溶液的侵蚀，因此在此清除步骤中，可以使用氟化氢溶液。接着，移除位于周边区域(未图标)的掩模。
请参照图3所示，于氮化物层18之上成长第二氧化物层22。此第二氧化物层22作为ONO层24的顶氧化物层。由于氮化物层18植入有氧离子，因此，第二氧化物层22的成长速率会增加。在一较佳实施例中，此氧化物层22可以在与传统顶氧化物层成长过程相同的时间内，额外成长60埃。而且在氮化物层18之上成长第二氧化物层22的同时，在基底周边区域的基底的上会成长栅氧化物。
之后，在核心区域及周边区域上沉积第二多晶硅层(未图标)。将沉积于核心区域的第二多晶硅层图案化并蚀刻，以形成快闪存储单元的控制闸。将沉积于周边区域的第二多晶硅层图案化并蚀刻形成MOS晶体管的栅极结构。之后，进行传统的制作工艺步骤，以形成快闪存储单元及MOS晶体管的源极区域及漏极区域。
虽然本发明已以一较佳实施例公开如上，然其并非用以限定本发明，任何熟悉此技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求界定为准。

Claims (16)

1.一种半导体器件的制造方法，其特征在于：该方法包括：
定义一基底，以使该基底包括一周边区域及一核心区域；
遮蔽该基底的该周边区域；
于该基底的该核心区域之上成长一第一介电层；
于该第一介电层之上沉积一第一多晶硅层，且该第一多晶硅层用以形成至少一栅极结构；
于该第一多晶硅层之上成长一第一氧化物层；
于该第一氧化物层之上沉积一氮化物层；
植入一氧离子至该氮化物层中；
移除该基底的该周边区域的遮蔽；以及
于该氮化物层之上成长一第二氧化物层，其中于该氮化物层中所植入的该氧离子增加该第二氧化物层的成长速率。
2、如权利要求1所述的半导体器件的制造方法，其特征在于：在该氧离子之植入步骤之后，还包括清除该氮化物层的一清除步骤。
3、如权利要求2所述的半导体器件的制造方法，其特征在于：该清除步骤使用一氟化氢溶液。
4、如权利要求1所述的半导体器件的制造方法，其特征在于：该第一氧化物层、该氮化物层及该第二氧化物层组成一晶体管的一氧化物-氮化物-氧化物层。
5、如权利要求4所述的半导体器件的制造方法，其特征在于：该晶体管为形成于该基底的该核心区域的一快闪存储单元。
6、如权利要求1所述的半导体器件的制造方法，其特征在于：还包括在成长该第二氧化物层的同时，于该基底的该周边区域上成长一闸氧化物。
7、如权利要求6所述的半导体器件的制造方法，其特征在于：该闸氧化物为位于该基底的该周边区域的一金属-氧化物-硅晶体管的氧化物。
8、如权利要求1所述的半导体器件的制造方法，其特征在于：该第二氧化物层增加60埃的成长速率。
9、如权利要求1所述的半导体器件的制造方法，其特征在于：于成长该第一氧化物层的步骤中，完成时的温度为摄氏700度至摄氏850度。
10.一种半导体器件的制造方法，其特征在于：该方法包括：
定义一基底；
于该基底的一核心区域之上成长一第一介电层；
于该第一介电层之上沉积一第一多晶硅层，且该第一多晶硅层用以形成至少一栅极结构；
于该第一多晶硅层之上成长一第一氧化物层；
于该第一氧化物层之上沉积一氮化物层；
植入一氧离子至该氮化物层中；以及
于该氮化物层之上成长一第二氧化物层，其中该第二氧化物层的成长速率因为该氮化物层中所植入的该氧离子而增加。
11、如权利要求10所述的半导体器件的制造方法，其特征在于：在该氧离子的植入步骤之后，还包括一清除该氮化物层的步骤。
12、如权利11项所述的半导体器件的制造方法，其特征在于：该清除步骤使用一氟化氢溶液。
13.如权利要求10所述的半导体器件的制造方法，其特征在于：该第一氧化物层、该氮化物层及该第二氧化物层组成一晶体管的一氧化物-氮化物-氧化物层。
14、如权利要求13所述的半导体器件的制造方法，其特征在于：该晶体管为形成于该基底的该核心区域的一快闪存储单元。
15、如权利要求10所述的半导体器件的制造方法，其特征在于该第二氧化物层的成长速率增加60埃。
16、如权利要求10所述的半导体器件的制造方法，其特征在于：成长该第一氧化物层的步骤于摄氏700度至摄氏850度进行。
CN03120784A 2002-03-21 2003-03-19 半导体器件的制造方法 Pending CN1447420A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/101,931 2002-03-21
US10/101,931 US6551879B1 (en) 2002-03-21 2002-03-21 Method for forming an oxide layer on a nitride layer

Publications (1)

Publication Number Publication Date
CN1447420A true CN1447420A (zh) 2003-10-08

Family

ID=22287230

Family Applications (1)

Application Number Title Priority Date Filing Date
CN03120784A Pending CN1447420A (zh) 2002-03-21 2003-03-19 半导体器件的制造方法

Country Status (4)

Country Link
US (1) US6551879B1 (zh)
JP (1) JP3802455B2 (zh)
CN (1) CN1447420A (zh)
TW (1) TW591706B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577223B (zh) * 2008-05-05 2011-03-23 中芯国际集成电路制造(北京)有限公司 栅极、半导体器件及栅极、掺杂区、含氮侧墙基层形成方法
CN104752177A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 一种制作嵌入式闪存栅极的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541157B1 (ko) * 2004-02-23 2006-01-10 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0751559B1 (en) * 1995-06-30 2002-11-27 STMicroelectronics S.r.l. Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC
TW374939B (en) * 1997-12-19 1999-11-21 Promos Technologies Inc Method of formation of 2 gate oxide layers of different thickness in an IC
US6103576A (en) * 1999-04-13 2000-08-15 Microchip Technology Incorporated Dielectric layer of a memory cell having a stacked oxide sidewall and method of fabricating same
US6265267B1 (en) * 1999-11-04 2001-07-24 United Microelectronics Corp. Fabricating method for a semiconductor device comprising gate oxide layers of various thicknesses

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577223B (zh) * 2008-05-05 2011-03-23 中芯国际集成电路制造(北京)有限公司 栅极、半导体器件及栅极、掺杂区、含氮侧墙基层形成方法
CN104752177A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 一种制作嵌入式闪存栅极的方法
CN104752177B (zh) * 2013-12-27 2017-11-10 中芯国际集成电路制造(上海)有限公司 一种制作嵌入式闪存栅极的方法

Also Published As

Publication number Publication date
US6551879B1 (en) 2003-04-22
JP2003282562A (ja) 2003-10-03
TW200304672A (en) 2003-10-01
TW591706B (en) 2004-06-11
JP3802455B2 (ja) 2006-07-26

Similar Documents

Publication Publication Date Title
CN1217404C (zh) 制造闪存单元的方法
US7183185B2 (en) Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
CN1447420A (zh) 半导体器件的制造方法
US6746921B2 (en) Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array
US6399443B1 (en) Method for manufacturing dual voltage flash integrated circuit
US8450199B2 (en) Integrating diverse transistors on the same wafer
US6579763B1 (en) Methods of forming an array of FLASH field effect transistors and circuitry peripheral to the array
US6207502B1 (en) Method of using source/drain nitride for periphery field oxide and bit-line oxide
US6759298B2 (en) Methods of forming an array of flash field effect transistors and circuitry peripheral to such array
CN1218385C (zh) 一种嵌入式存储器的制作方法
CN113161361B (zh) 或非型闪存器件及其制造方法
KR100237014B1 (ko) 플래쉬 이이피롬 셀 제조 방법
CN1153275C (zh) 改善分离栅极式闪存氧化层品质的方法
KR20050068901A (ko) 비 휘발성 메모리 소자의 제조방법
KR100361211B1 (ko) 플래쉬 이이피롬 셀의 제조 방법
KR100998959B1 (ko) 비휘발성 메모리 소자의 제조 방법
US8975185B2 (en) Forming charge trap separation in a flash memory semiconductor device
KR100575361B1 (ko) 플래시 게이트 및 고전압 게이트 형성 방법
KR100424171B1 (ko) 플래쉬 메모리 소자의 제조방법
CN116033755A (zh) 一种优化sonos存储器ono栅介质阻挡氧化层均匀性的方法
KR100325618B1 (ko) 선택적 에피탁시 성장을 이용하여 제조된 플래쉬 메모리및 그 제조방법
CN114843172A (zh) 一种sonos存储器ono光刻返工工艺集成方法
CN114864587A (zh) 嵌入式闪存及其制备方法
KR100223891B1 (ko) 플래쉬 메모리 소자의 제조방법
KR101305727B1 (ko) ＥＴＯＸ 셀을 갖는 ＳｏＣ 소자 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication