CN1414821A - 具有高质良率的电路基板 - Google Patents

具有高质良率的电路基板 Download PDF

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CN1414821A
CN1414821A CN01136818A CN01136818A CN1414821A CN 1414821 A CN1414821 A CN 1414821A CN 01136818 A CN01136818 A CN 01136818A CN 01136818 A CN01136818 A CN 01136818A CN 1414821 A CN1414821 A CN 1414821A
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weld pad
high quality
signal
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CN1191001C (zh
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林蔚峰
吴忠儒
梁桂珍
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Silicon Integrated Systems Corp
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Silicon Integrated Systems Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种具有高质良率的电路基板，包括一晶片、一基板、复数第一及第二焊线；晶片上具有复数接地焊垫与电源焊垫；基板上具有一接地环与电源环；该些第一及第二焊线分别将该些接地焊垫与电源焊垫连接至该接地环与电源环；其中，该些接地焊垫与电源焊垫在该晶片上成群连续排列，而分隔该些第一与第二焊线。经由晶片上焊垫与基板上铜箔的特殊排列，可改变产品的电气特性与降低焊线短路的机率。

Description

具有高质良率的电路基板
技术领域
本发明涉及线路器件，特别是一种电路基板。
背景技术
图1显示了一传统电路基板的一部，其中包括一基板11、在基板上以铜箔形成的接地环(ground ring)111、电源环(power ring)112、讯号接脚113及防焊材料层114、镶于基板上的晶片(die)12、晶片12上的接地焊垫(ground pad)121、电源焊垫(power pad)122及讯号焊垫123、分别连接接地焊垫121至接地环111、电源焊垫122至电源环112及讯号焊垫123至讯号接脚113的焊线(Bonding wire)131、132、133。其中，晶片12上的接地焊垫121、电源焊垫122及讯号焊垫123分别用以接收晶片12所需的接地与供应电压，以及讯号的输入及输出。
在传统电路基板与晶片焊垫上的设计，如图1所示，接地焊垫121、电源焊垫122及讯号焊垫123在晶片12上成交错排列的状态，此种排列方式使得连接接地焊垫121至接地环111、电源焊垫122至电源环112及讯号焊垫123至讯号接脚113的焊线131、132、133交错着。
然而，为了避免在焊线形成后灌模(molding)时，因焊线歪斜而发生短路现象，相邻的两条焊线必需具有不同的弧高设定，亦必需将接地环111与电源环112间的间距加大。如此，扯长了焊线的长度而增加了其电感值，降低了产品的电气特性。
发明内容
为了解决上述问题，本发明提供一种电路基板，在可避免发生短路的情况下，可以有相同的焊线弧高设定，亦可以缩短焊线的长度，提高焊线的电气特性。
本发明的目的在于提供一种具有高质良率的电路基板，包括一晶片、一基板、复数第一及第二焊线。晶片上具有复数接地焊垫与电源焊垫。基板上具有一接地环与电源环。该些第一及第二焊线分别将该些接地焊垫与电源焊垫连接至该接地环与电源环。其中，该些接地焊垫与电源焊垫在该晶片上成群连续排列，而分隔该些第一与第二焊线。
籍此，本发明将连接接地焊垫至接地环、电源焊垫至电源环及讯号焊垫至讯号接脚的焊线分群排列，由于连接电源焊垫至电源环、接地焊垫至接地环的焊线即使分别短路亦不会造成晶片中电路的操作错误，因此可以具有相同的弧高设定，接地环与电源环的间距亦可以缩短，使焊线长度减小而提高其电气特性。
本发明更包括有复数第三焊线，该晶片与该基板分别更具有复数讯号焊垫与复数讯号接脚，该些第三焊线将该些讯号焊垫连接至该些讯号接脚，且该些讯号焊垫与讯号接脚成群连续排列，而分隔该些第三焊线与该些第一、第二焊线；以及
该电源环具有一凸出部，该些电源焊垫籍由该些第二焊线于该凸出部与该电源环连接，使该些第一与第二焊线的弧高相同；
该接地环具有一与该电源环凸出部相对的凹入部；
更包括一防焊材料层，位于该晶片与该基板之间及该电源环与该接地环之间；
更包括一位于该防焊材料层与该晶片间的用以固定该晶片的环氧化物层。
综上所述，本发明利用晶片上电源焊垫、接地焊垫及讯号焊垫成群的排列及具有凸出部的电源环，使得本发明具有焊线弧高设定相同、焊线长度缩短及降低电源与接地环短路的机率，远较传统的电路基板表现优良。
附图说明
图1一传统电路基板的一部；
图2本发明一实施例中电路基板的一部；
图3图2中沿XX’切线的剖面图。件号说明：
11、21  电路基板；
12、22  晶片：
131、132、133、231、232、233  焊线：
111、211  接地环；
112、212  电源环；
113、213  讯号接脚；
114、214  防焊材料层；
121、221  接地焊垫；
122、222  电源焊垫；
123、223  讯号焊垫。
具体实施方式
图2、3显示了本发明一实施例的电路基板的一部，其中包括一基板21、在基板上以铜箔形成的接地环211、电源环212及讯号接脚213、镶于基板上的晶片22、晶片22上的接地焊垫221、电源焊垫222、讯号焊垫223及防焊材料层214、分别连接接地焊垫221至接地环211、电源焊垫222至电源环212及讯号焊垫223至讯号接脚213的焊线231、232、233。其中，晶片22上的接地焊垫221、电源焊垫222及讯号焊垫223分别用以接收晶片22所需的接地与供应电压，以及讯号的输入及输出。
此外，电源环212亦具有一凸出部2121，接地环211亦有一相对的凹入部(其标号省略)，可拉近电源环212与晶片22上电源焊垫222的距离，使连接电源环212及电源焊垫22的焊线长度缩短，提高其电气特性。
图3显示了图2中沿XX’切线的剖面图。其中相同的元件系使用相同的符号表示。在基板21上具有接地环211、电源环212及置于接地环211上与铜箔间距间的防焊材料层214、在防焊材料层214与晶片22之间的环氧化物层(Epoxy)24。环氧化物层24系用以将晶片22固定于防焊材料层214之上。
在本实施例中的电路基板与晶片焊垫上的设计，如图2所示，接地焊垫221、电源焊垫222及讯号焊垫223在晶片22上以成群连续的方式排列，此种排列方式使得连接接地焊垫221至接地环211、电源焊垫222至电源环212及讯号焊垫223至讯号接脚213的焊线231、232、233分成三组分隔的焊线群，相邻的两条焊线系属于同一连接目的的焊线。
此时，连接接地环211及接地焊垫221的三条焊线231即使因灌模歪斜而相互接触短路，由于其连接至同一接地环211，所以并不会对晶片22中电路的操作有影响，连接电源环212  及电源焊垫22  的焊线亦有同样的情形，因此焊线231、232及233可以有相同的弧高设定而不必担心其可能发生短路的问题；同时，由于电源环212具有凸出部2121，减小了焊线232的长度，使其电气特性较传统较长的焊线为佳。

Claims (6)

1、一种具有高质良率的电路基板，至少包含：
一晶片，具有复数接地焊垫与电源焊垫；
一基板，具有一接地环与电源环；以及
复数第一及第二焊线，分别将该些接地焊垫与电源焊垫连接至该接地环与电源环；
其中，该些接地焊垫与电源焊垫在该晶片上成群连续排列，而分隔该些第一与第二焊线。
2、如权利要求1所述具有高质良率的电路基板，其特征在于，更包括有复数第三焊线，该晶片与该基板分别更具有复数讯号焊垫与复数讯号接脚，该些第三焊线将该些讯号焊垫连接至该些讯号接脚，且该些讯号焊垫与讯号接脚成群连续排列，而分隔该些第三焊线与该些第一、第二焊线。
3、如权利要求1所述具有高质良率的电路基板，其特征在于，该电源环具有一凸出部，该些电源焊垫籍由该些第二焊线于该凸出部与该电源环连接，使该些第一与第二焊线的弧高相同。
4、如权利要求3所述具有高质良率的电路基板，其特征在于，该接地环具有一与该电源环凸出部相对的凹入部。
5、如权利要求1所述具有高质良率的电路基板，其特征在于，更包括一防焊材料层，位于该晶片与该基板之间及该电源环与该接地环之间。
6、如权利要求5所述具有高质良率的电路基板，其特征在于，更包括一位于该防焊材料层与该晶片间的用以固定该晶片的环氧化物层。
CNB011368187A 2001-10-24 2001-10-24 一种电路基板 Expired - Fee Related CN1191001C (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781898B2 (en) 2007-01-24 2010-08-24 Chipmos Technologies Inc. IC package reducing wiring layers on substrate and its chip carrier
WO2016044993A1 (zh) * 2014-09-23 2016-03-31 华为技术有限公司 射频功率组件及射频信号收发设备

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781898B2 (en) 2007-01-24 2010-08-24 Chipmos Technologies Inc. IC package reducing wiring layers on substrate and its chip carrier
US8026615B2 (en) 2007-01-24 2011-09-27 Chipmos Technologies Inc. IC package reducing wiring layers on substrate and its carrier
WO2016044993A1 (zh) * 2014-09-23 2016-03-31 华为技术有限公司 射频功率组件及射频信号收发设备
US10347596B2 (en) 2014-09-23 2019-07-09 Huawei Technologies Co., Ltd. Radio frequency power component and radio frequency signal transceiving device

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