CN1407619A - 高密度的电路小片间互连结构 - Google Patents
高密度的电路小片间互连结构 Download PDFInfo
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Abstract
一种把第一集成电路制备结构上的间距紧密的多个电气元件和第二集成电路制备结构上的工作电路相连的互连结构。在一个实施例中,第一集成电路制备结构包括多个光敏器件。第一集成电路制备结构上的导电互连元件提供单个光敏器件和第二集成电路制备结构上的工作电路之间的电连接。
Description
技术领域
本发明涉及半导体小片(die)的互连结构,更具体地说,本发明涉及电路小片的互连结构,其中至少一个电路小片上的电路能够独立工作并且彼此具有较小的间距。
背景技术
目前使用着各种成像器或图像传感器,包括电荷耦合器件(CCD)图像传感器和互补金属氧化物半导体(CMOS)图像传感器。这些基于半导体的图像传感器广泛用在许多图像输入装置中,因为可利用先进的精细图案平板印刷技术批量生产这样的图像传感器。应用包括数字照相机、用于资料捕捉的计算机外围设备、可视通信设备和传真机。
CCD图像传感器使用一系列的光敏器件形成正比于接收的光强度的电荷包(charge packet)。这些光敏器件一般是位于图像传感器表面上的光电晶体管或光电二极管。每个电荷包构成合成图像的一个像素。通过逐一像素地把这些模拟电荷包从CCD阵列的内部移动到外围,从CCD阵列中读出图像数据。为了起动读出过程,把第一行的电荷转移到读出寄存器中,从读出寄存器把信号输入放大器,并且在大多数应用中把放大后的信号输入模-数转换器。一旦读取了一行,则可删除该行在读出寄存器行上的电荷。随后下一行进入读出寄存器,上面的各行下移一行。这样,各行被读取,每次读取一行。由于一行像素中所有的像素被同时读取,因此CCD阵列中的像素是不能单独寻址的。
由于电压、电容和工艺约束条件的缘故,在CMOS集成电路中可能的高度集成的情况下,CCD阵列不是很适合于集成。因此,通常在一个或多个独立芯片上设置CCD图像传感器所需的任意辅助信号处理电路(例如保存和传感器有关信息的存储器)。从而增大了系统成本和尺寸。另外已知和常规的CMOS信号处理电路相比,CCD图像传感器需要较大的功耗和较高的工作电压。
CMOS图像传感器一般利用一系列的活动像素图像传感器和一排寄存器或放大器对指定的一行像素图像传感器的输出采样并保存采样结果。CMOS像素的工作原理是根据起因于照射光的(例如二极管的)反偏PN结电容的调制。吸附到反偏PN结的耗尽区中的光子产生电子-空穴对,所述电子-空穴对使反偏电容放电。较大的PN结收集更多的光子并且对光更为灵敏,但是较大的PN结也会降低传感器的分辨率,因为可在可用表面积上布置的像素较少。
和CCD图像传感器相比,CMOS图像传感器具有几个优点。和操纵CMOS图像传感器所需的相关电路一样,CMOS图像传感器由相同的CMOS工艺技术形成,于是传感器和配套电路易于集成到单个芯片上。单一芯片集成易于小型化,降低生产成本并且提高可靠性。利用CMOS图像传感器,能够产生不仅提供传感器,而且还提供控制逻辑和计时、图像处理和信号处理电路的单片集成电路。从而通过利用常规的CMOS集成电路制备工艺,能够和CCD图像传感器相比,以较低的成本制造CMOS图像传感器。另外CMOS图像传感器工作电压较低,并且能耗也低,允许包含CMOS图像传感器的系统借助电池工作更长的时间,对于手持式图像产品来说这是一个主要优点。最后,通过x-y线的坐标网络,而不是利用电荷耦合器件的移位寄存器方法,能够访问各个CMOS图像传感器。和常规的RAM读出方法相似的CMOS图像传感器的列和行可寻址性使得能够实现图像的开窗(windowing)功能。CMOS图像传感器只需要一个电源可驱动图像传感器和相关的电路。相反,CCD图像传感器一般需要三种不同的输入电压。另外,由于制造加工缺点,CCD图像传感器缺少一致的黑度电压(dark level voltage)。已知CMOS图像传感器也表现出不一致的黑度,但是相关的CMOS信号处理电路能够在信号处理功能中跟踪每个CMOS图像传感器的黑度,并且提供补偿因子,从而在CMOS图像传感器阵列中能够获得均匀的黑度。
但是,CMOS图像传感器也不是没有缺点。把目前水平的CMOS集成电路制备技术应用于相关的信号处理电路和CMOS图像传感器会危及CMOS光敏器件的结构,从而降低图像信号的质量。例如,在CMOS工艺中通常使用的典型基片和源极/漏极掺杂水平(或者逆向掺杂的电子管,即表面的掺杂水平低于表面之下的掺杂水平)高于提供最佳图像传感器质量的掺杂水平。降低掺杂水平以获得较好的传感器灵敏度、动态范围或者颜色谐调性会显著恶化CMOS处理电路的性能。于是较高程度的组件集成(即图像传感器和工作的信号处理电路在同一芯片上)是不切实际的。
此外,在CMOS图像传感器及其信号处理电路共同位于同一集成电路上的情况下,相关电路占用一部分可用像素区,导致整体芯片面积更大,降低图像充填因数(活动像素面积与总像素面积的比值)。从而不利地降低CMOS图像传感器阵列的效率、分辨率和灵敏度。另外,某些CMOS材料层(例如salicide层)可能部分或者完全不透光,从而降低图像传感器的灵敏度。就克服当结合CMOS图像传感器使用现有水平的CMOS工艺技术时产生的缺陷的努力来说,已产生了除去加工步骤或者改变器件物理特性从而提高图像传感器信号质量的某些改进CMOS工艺。虽然除去这些加工步骤可提高图像传感器的信号质量,但是一般会危及CMOS技术。总之,可以认为目前水平的CMOS图像传感器加工技术比现今的CMOS加工技术落后几代。
发明内容
为了克服上面所说明的关于CMOS图像传感器和相关的CMOS工作电路的使用的缺点,本发明提供第一集成电路结构和第二CMOS(或者其它集成电路类型,例如BiCMOS)集成电路结构之间的互连系统,所述第一集成电路结构具有形成于其中的多个图像传感器,所述第二集成电路结构具有和图像传感器一起工作的信号处理电路。通过把图像传感器结构和操作信号处理电路分开,可利用特别适合于图像传感器的加工技术制备图像传感器结构,可利用唯一最优的制备技术和器件特性制造信号处理电路。互连系统包括化学镀镍凸点、焊点或者其它众所周知的电路小片互连结构,尤其是间距细微的互连结构。在图像传感器结构上形成使各个图像传感器或者像素元件与位于独立结构上的与之相关的信号处理电路互连的凸点。在信号处理电路上也包括与图像传感器结构的各个像素元件相连的配套电路小片互连结构。在制备这两种独立的结构之后,借助配套电路小片互连结构使图像传感器结构和信号处理结构结合。根据本发明的教导,使用独立的图像传感器和信号处理结构能够利用最有利的制备加工步骤和器件特性,优化各个结构的功能特性和加工方法。
附图说明
结合优选实施例和下述附图的说明,能够更容易地理解本发明,并且更易于明白本发明的其它优点和应用,其中:
图1图解说明典型的CMOS图像传感器阵列;
图2图解说明现有的CMOS图像传感器电路;
图3是表示图2的CMOS图像传感器电路的工作阶段的时间线;
图4是按照本发明的教导互连的第一和第二集成电路结构的横截面图;
图5图解说明CMOS图像传感器电路的掺杂区。
具体实施方式
本发明的加工步骤和硬件组件由附图中的常规过程和部件表示,图中只表示了与本发明有关的那些具体细节,以便不会因对本领域的技术人员来说易于明白的细节使本公开文献难以理解。示例性的器件层没有按比例表示。附图中相同的附图标记表示相同的结构部件。
块状半导体材料可用作半导体电阻随着照射光波的波长和强度而变化的光敏电阻(也称为光敏器件或者图像传感器)。(本征半导体材料)价带中处于束缚态的电子或者(非本征半导体材料)禁带内处于掺杂确定的能级中的电子吸收来自入射光光子的能量,并且被激发成导带中的自由态。在特征寿命内电子保持激发态。由于导带中电子的移动或者价带中形成的空穴的移动,产生电流的传导。从而半导体材料的电阻反比于照度,并且这种电阻变化被转换成流过器件输出电路的电流的变化。
代替简单的半导体块状光敏器件,光敏器件结装置(photo sensorjunction devices)可用于提高检测器对光学辐射的响应速度和灵敏度。设计成响应光子吸收的这种两端器件被称为光电二极管。在常规的反偏二极管中,由于电场的缘故,在耗尽区内产生的载流子漂离耗尽区;于是电子集中到n区中,空穴集中到p区中。这些载流子形成反向电流。另外,在跃迁区边缘的扩散长度内热生成的少量载流子扩散到耗尽区,并且被电场扫掠到另一侧。如果该结也被能量高于半导体材料带隙的光子均匀照射,则这些电子-空穴对也参与反向电流。这是反编二极管检测光线的基本原理。虽然在耗尽区外也产生电子-空穴对,但是它们不会产生电流流动。
通常,可应用本发明的教导的CMOS图像传感器是通过检测由光敏器件产生的电压变化来测量入射光的集成电路。具体地说,光敏器件被充电到预定电压,并且随后累积入射光线,其结果是在该器件两端之间获得更高的电压。随后光敏电压的电压值被读出电路读出,其中该电压值代表入射光。
图1图解说明常规的CMOS图像传感器阵列100的方框图。阵列中的各个元件(例如阵列元件161、162和163)是单个的CMOS图像传感器电路,下面将结合图2说明其细节。单个的CMOS图像传感器电路也称为像素电路或像素元件。
CMOS图像传感器阵列100由行解码器110和列解码器120控制,行解码器110和列解码器120被单独激活,以便选择要激活的具体CMOS图像传感器电路。激活的CMOS图像传感器电路的输出沿着列输出线164被传送给读出和保持电路130。读出和保持电路130读出被激活的CMOS图像传感器电路的电压值。最后,由模-数转换器140把读出的电压值转换成数字值。模-数转换器140的输出信号是代表光强的数字信号。
除了CMOS图像传感器具有被设置成初始电压值、并且随后在暴露于入射光之下之后被读出的单个CMOS图像传感器电路取代被设置并且稍后被读出的单个存储单元之外,诸如阵列100之类的CMOS图像传感器阵列类似于动态随机存取存储器。此外,CMOS图像传感器阵列与动态随机存取存储器的不同之处在于模拟数值保存在各个CMOS图像传感器内,并且随后通过模-数转换器140中的转换被量化。
图2图解说明示例性的CMOS图像传感器电路161,它包括复位晶体管230、光敏器件(photo sensor)220、源极跟随器晶体管240和行选择晶体管250。图2中还图解说明了处理CMOS图像传感器电路161的输出信号的示例性输出电路。具体地说,该输出电路包括电流源晶体管280和传感器电路290。
CMOS图像传感器电路161在三个不同的阶段工作:复位、累积和读出。下面参考图3说明CMOS图像传感器电路161的操作阶段,图3表示在CMOS图像传感器电路161的工作过程中,源极跟随器晶体管240的栅压。
一开始,在复位阶段310(参见图3)中,光敏器件220通过复位晶体管230被电压源VDD充电,即反偏至复位电平。光敏器件的阴极端子的实际电压为VDD-VTN,这里VTN是复位晶体管230两端的压降。充电电平被称为基准黑”电平(VRB)。
接下来,在累积阶段330(参见图3)中,光敏器件220暴露于要测量的入射光之下。如上所述,撞击光敏器件220的耗尽区的光子导致流向源极跟随器240的栅极端子的反向电流的增大。光敏器件220上剩余电荷的电压正比于撞击光敏器件220的光子的数目。从而在累积阶段330中,源极跟随器240的栅极的电压下降。当光敏器件220的阴极端子逼近负极电源电压,这种情况下为接地电压时,达到基准白电平。当没有任何光子被累积时产生黑电平,以致光敏器件电压基本上保持初始的基准黑电平VRB=VDD-VTN。
最后,在读出阶段350(参见图3)中,行选择晶体管250被激活,从而由传感器电路290测量源极跟随器晶体管240的栅压。在一个实施例中,利用相关复式抽样电路测量光敏器件电压。首先对累积的光敏器件电压信号进行抽样。随后使CMOS图像传感器电路161复位,并且对复位电压抽样,从而获得基准黑电平。代表入射光的所需信号是累积的光敏器件电压和光敏器件复位电压之间的差值。
根据本发明的教导,最好把光敏器件220和诸如图2中图解说明的晶体管之类的相关电路和传感器电路290分开。这样,在光敏器件阵列的制备过程中,可采用优化光敏器件220的特性所需的制备工艺。类似地,当制备相关电路时,可采用优化相关电路的功能所需的制备工艺。随后按照本发明教导的那样互连这两种结构。
反装晶片(flip chip)互连技术采用在芯片或者单片半导体器件的一个表面上形成的珠状端子把反装晶片连接到另一电子器件,例如电路板上。也称为凸点(bump)的珠状端子既用于把反装晶片机械固定到电路板上,又用于把反装晶片电路电互连到电路板导线分布图上。
参见图4,图中表示了具有连接到CMOS图像传感器阵列370的表面390上的多个凸点或端子372的CMOS图像传感器阵列370的横截面。凸点372使CMOS图像传感器阵列370上的电路和集成电路374的信号处理电路互连。在一个实施例中,集成电路374包括采用CMOS技术的电路。入射光在CMOS图像传感器阵列370的表面380被CMOS图像传感器阵列370接收。在一个实施例中,CMOS图像传感器阵列包括图2中图解说明的光敏二极管220,其位置通常由附图标记382表示。图2中的其它组件(以及所需的其它电路元件)被装配到集成电路374中。
滤光器可放置在CMOS图像传感器阵列370的入射面(即表面380)附近,以便滤出依据滤光器的特性确定的特定波长的光线。例如,通过在表面380上放置阻止其它光谱颜色的滤光器,可使CMOS图像传感器阵列370中的大多数光敏器件220只对红光敏感。按照类似的方法,借助适当的光谱过滤,可使其它光敏器件220只响应蓝光或绿光。可在基片374的电路内组合源自于相应光敏器件的代表红光、绿光和蓝光强度的信号,从而产生颜色信号。
在一个实施例中,CMOS图像传感器阵列370的像素的间距约为几微米级,于是为了单独访问每个图像传感器,则连接的间距(如果被配置成提供单独的像素访问)必须具有相同的间距。在本发明的另一实施例中,相邻或者成组的像素必须被制备成具有不同的性质,例如一组n个像素中的各个像素必须具有对选定波长的最佳频率响应。在这样的实施例中,可能不需要访问单个的像素,但是相反通过单个互连凸点可访问一组n个像素。在另一实施例中,本发明的教导可应用于成行排列的多个图像传感器,而不是图1中图解说明的二维阵列。
可利用几种不同的技术形成凸点372的阵列,所述这些技术都会在凸点间距、成本和制备简单性之间做出折衷。在一个实施例中,可通过丝网印刷工艺或者通过一般利用平板印刷(lithographic)技术有选择地除去导电物质,形成凸点。常见的丝网印刷工艺也可用于构成凸点阵列。
也可通过在半导体基片中的先前暴露的金属或导电区上进行电镀或化学镀,有选择地形成凸点。掩模(它是支承凸点图案的透明二氧化硅片)被用于暴露要形成凸点的区域。空白掩模被涂覆紫外光吸收层,例如氧化铁,从而使整个掩模对紫外光是不透明的。在二氧化硅片上放置一薄层电子束抗敏材料(electron beam sensitive resist material),并且使选择的部分暴露于电子束之下;暴露部分经历化学变化。暴露之后,通过在化学溶液中冲洗,除去保护层的暴露部分。随后在暴露的保护层已被除去的区域中有选择地从掩模上蚀刻除去氧化铁物质。
为了制备集成电路,利用对紫外光敏感的有机材料,称为光敏抗蚀剂涂覆图像传感器370的表面390。随后把掩模放置成与光敏抗蚀剂覆盖的晶片接触,并且使组件暴露于紫外光之下。紫外光通过没有氧化铁的那些掩模部分照射并酸化暴露的光敏抗蚀剂。在氢氧化钠的碱性溶液中冲洗图像传感器阵列370,蚀刻掉暴露的光敏抗蚀剂。这样,掩模上的图案被转移到表面390上。通过加热处理剩余的光敏抗蚀剂。
随后通过在暴露区域中电镀或电沉积导电材料,在带图案的表面390中形成凸点372。在常规的电沉积技术中,一些金属(例如镍)被准确地电沉积到掩模开口点。如果焊锡用作凸点的材料,则把焊锡放入开口中,并加热到其熔点之上,从而形成焊点。凸点的最终形状取决于形成凸点的技术和构成凸点的材料。焊点特质上为半球状。通过电镀沉积或化学沉积的凸点可能具有矩形横截面。在形成凸点372之后,除去掩模,并对整个表面390,包括凸点372涂覆防腐剂。例如焊点被涂上金以抑制腐蚀。
在表面390上形成的凸点的类型还决定用于把凸点372固定到基片374上的技术。当由焊锡构成凸点时,采用回流焊固定工艺(solder reflowatrachment process)使单个的焊点372电连接并且牢固地连接到基片374上的导电图形上。回流焊工艺包括首先使焊点372对准基片374上它们相应的配套导电区,并且重新加热或回流焊锡,以便使焊点372和基片374的对应导体冶金结合,从而使焊点372和基片374的对应导体电连接。如果凸点材料是化学沉积或者电沉积的,则通过丝网印刷工艺涂覆的导电粘合剂可用于连接两个表面。也可使用非均质(anisotrophic)粘合剂(即基本上沿一个方向导电)。在整个表面上涂覆该粘合剂,但是当使凸点和其配套表面物理接触时,只在施加了挤压力的区域中才导电。
可能必须抛光并深腐蚀表面380,以便入射光能够通过表面380并到达形成光敏器件220的掺杂半导体区。如果利用硅衬底材料制造CMOS图像传感器阵列370,则CMOS图像传感器阵列370对可透过硅的那些频率,即光谱的红外部分的波长起反应。本领域的技术人员已知其中形成光敏器件220的半导体材料的带隙(band gap)确定半导体光敏器件220对其响应的波长,从而确定CMOS图像传感器阵列370的频率灵敏度。
根据本发明的教导,图4中图解说明的互连结构适应对各个像素元件或光敏器件220的单独访问和控制。从而,在光敏器件阵列370中可实现特殊的光学效果。另外,制备工艺方面的异常可在不同的光敏器件220之间产生各种变化。具体地说,对于相同的入射光能量来说,掺杂程度的轻微变化会影响输出的光敏器件电压。制备之后,可利用已知的入射光来校准单个光敏器件,之后可把与各个像素相关的信号处理电路设计成补偿相对于相同入射光的输出电压方面的变化。
图5图解说明代表光敏器件220的三个示例性的间隔一定距离的掺杂区。具体地说,PN结包括具有沿着表面403形成于其中的间隔一定距离的n+区402和n-区404的p型基片材料400。n-区的使用为入射光子的收集提供较大的耗尽区。可利用n型基片和形成于其中的p型掺杂区制备相同的结构。
除了上述CMOS图像传感器之外,也可以肖特基势垒二极管、金属-半导体-金属光电二极管、p-i-p二极管、雪崩二极管和异质结光电晶体管的形式实现本发明的光敏器件。另外场效应和双极结器件也可用作图像传感器。
虽然参考优选实施例说明了本发明,但是本领域的技术人员应当理解在不脱离本发明的范围的情况下可做出各种变化,并且可用相同的元件替代该优选实施例的元件。本发明的范围还包括这里陈述的各种实施例的元件的任意组合。另外,在不脱离本发明的范围的情况下,可做出各种修改,使特殊的情形适应本发明的教导。特别地,可在包括利用III-IV化合物和其它半导体材料形成的结构的各种电路结构中,以各种方式实现本发明。于是,本发明并不局限于公开的特定实施例,相反本发明将包括这里没有明确指出的在附加权利要求范围内的所有其它结构。
Claims (34)
1、一种集成电路器件,包括:
第一集成电路,它包括可独立工作的多个电气元件和与一个或多个所述可独立工作的电气元件电连接的多个导电互连元件;
第二集成电路,它包括工作电路和形成于其表面上并且与所述多个导电互连元件电连接的多个连接区(pad)。
2、按照权利要求1所述的集成电路器件,其中可独立工作的电气元件的数目等于互连元件的数目。
3、按照权利要求1所述的集成电路器件,其中所述多个互连元件的间距等于所述多个连接区的间距。
4、按照权利要求1所述的集成电路器件,其中第二集成电路的工作电路和第一集成电路的多个电气元件一起工作。
5、按照权利要求1所述的集成电路器件,其中所述多个互连元件等于所述可独立工作的多个电气元件。
6、按照权利要求1所述的集成电路器件,其中所述多个互连元件包括多个导电凸点。
7、按照权利要求7所述的集成电路器件,其中通过在所述多个电气元件上形成导电层,并且有选择地除去导电层的某些区域以使剩余的区域构成导电凸点,形成多个导电凸点。
8、按照权利要求7所述的集成电路器件,其中借助利用掩模识别要除去的区域的平板印刷工艺控制导电层的区域的选择性去除。
9、按照权利要求1所述的集成电路器件,其中所述可独立工作的多个电气元件均包括工作电路和与所述工作电路电连接的导电区,其中所述多个导电区均和所述多个互连元件之一电连接,并且通过作用于第一集成电路的表面的平板印刷工艺暴露所述多个导电区中的各个导电区,从而形成与之电连接的多个互连元件。
10、按照权利要求1所述的集成电路器件,其中通过利用导电粘合剂,所述多个导电互连元件中的各个导电互连元件被固定到所述多个连接区中的一个连接区上。
11、按照权利要求1所述的集成电路器件,其中所述多个电气元件被排列成阵列。
12、按照权利要求1所述的集成电路器件,其中所述多个电气元件被排列成线性图形。
13、按照权利要求1所述的集成电路器件,其中使第一集成电路上专用于所述多个电气元件的面积最大化。
14、一种集成电路器件,包括:
第一集成电路,它包括可独立工作的多个光敏器件,其中各个光敏器件的工作参数与入射在所述第一集成电路上的光线有关,并且其中所述第一集成电路还包括均与一个或多个所述光敏器件电连接的多个导电互连元件;
第二集成电路,它具有形成于其表面上并且与所述多个导电互连元件电连接的多个连接区。
15、按照权利要求14所述的集成电路器件,其中第二集成电路包括确定光敏器件的与入射光相关的工作参数的工作电路。
16、按照权利要求14所述的集成电路器件,其中处理暴露于入射光之下的第一集成电路的表面,以使被多个光敏器件接收的光线达到最大。
17、按照权利要求14所述的集成电路器件,其中第一集成电路包括第一传导类型的半导体基片和在半导体基片的表面中形成的间隔一定距离的多个第二传导类型的掺杂半导体区,其中对半导体基片和掺杂区施加反偏电压,以便在其间产生耗尽区。
18、按照权利要求14所述的集成电路器件,其中第一集成电路包括图像传感器阵列,其中使图像传感器阵列的充填因数达到最大。
19、按照权利要求14所述的集成电路器件,其中所述多个导电互连元件的数目和所述多个光敏器件相同。
20、按照权利要求14所述的集成电路器件,其中所述多个导电互连元件中的每个元件包括在第一集成电路的表面上方延伸的导电表面。
21、按照权利要求20所述的集成电路器件,其中在第一集成电路的表面上方延伸的导电表面包括导电凸点。
22、按照权利要求21所述的集成电路器件,其中通过在多个电气元件上形成导电层,并且有选择地除去某些区域的导电层以使剩余区域形成导电凸点,从而形成导电凸点。
23、按照权利要求22所述的集成电路器件,其中借助利用掩模识别要除去的区域的平板印刷工艺控制导电层区域的选择性去除。
24、按照权利要求14所述的集成电路器件,其中可独立工作的多个光敏器件均包括工作电路和与所述工作电路电连接的导电区,其中所述多个导电区中的各个导电区还与多个互连元件之一电连接,其中通过作用于第一集成电路的表面的平板印刷工艺暴露所述多个导电区中的各个导电区,从而形成与之电连接的多个互连元件。
25、按照权利要求14所述的集成电路器件,其中利用导电粘合剂,所述多个导电互连元件中的各个导电互连元件被固定到所述多个连接区中的一个连接区上。
26、按照权利要求14所述的集成电路器件,其中所述多个光敏器件被排列成阵列。
27、按照权利要求14所述的集成电路器件,其中所述多个光敏器件元件被排列成线性图形。
28、一种制造集成电路器件的方法,包括:
制备包括可独立工作的多个电气元件的第一集成电路;
制备与所述可独立工作的多个电气元件电连接的多个导电互连元件;
制备具有形成于其表面上的多个连接区的第二集成电路;和
对各个导电互连元件中的每个元件定位,使之与多个连接区之一电连接。
29、按照权利要求28所述的方法,其中制备多个导电互连元件的步骤包括在多个电气元件上形成导电层,有选择地除去某些区域的导电层,使得剩余的区域构成导电互连元件。
30、按照权利要求29所述的方法,其中有选择地除去导电层的步骤还包括把平板印刷掩模贴到导电层的表面上,并且在平板印刷掩模控制下除去导电层区域。
31、按照权利要求28所述的方法,其中所述多个电气元件均包括工作电路和与所述工作电路电连接的导电区,其中所述多个导电区中的各个导电区还与多个互连元件之一电连接,其中所述方法还包括通过利用施加在第一集成电路的工作表面的平板印刷掩模,暴露所述多个导电区中的各个导电区,并且通过掩模形成与之电连接的多个互连元件。
32、按照权利要求28所述的方法,其中定位步骤还包括利用导电粘合剂把多个导电互连元件中的各个元件固定到多个连接区之一上。
33、按照权利要求28所述的方法,其中可独立工作的多个电气元件均包括一个光敏器件。
34、按照权利要求28所述的方法,其中借助利用第二传导类型的掺杂剂掺杂第一传导类型的基片的步骤,制备所述多个光敏器件。
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- 2002-07-31 CN CN02127289A patent/CN1407619A/zh active Pending
- 2002-09-03 DE DE10240471A patent/DE10240471A1/de not_active Withdrawn
- 2002-09-05 SG SG200205386A patent/SG120885A1/en unknown
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- 2002-09-10 KR KR1020020054448A patent/KR20030022724A/ko not_active Application Discontinuation
- 2002-09-10 FR FR0211170A patent/FR2829615B1/fr not_active Expired - Fee Related
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CN103208501A (zh) * | 2012-01-17 | 2013-07-17 | 奥林巴斯株式会社 | 固体摄像装置及其制造方法、摄像装置、基板、半导体装置 |
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CN103208501B (zh) * | 2012-01-17 | 2017-07-28 | 奥林巴斯株式会社 | 固体摄像装置及其制造方法、摄像装置、基板、半导体装置 |
CN111400988A (zh) * | 2018-12-27 | 2020-07-10 | 北京忆芯科技有限公司 | 集成电路芯片的凸点(Bump)盘布局方法 |
CN111400988B (zh) * | 2018-12-27 | 2023-08-22 | 北京忆芯科技有限公司 | 集成电路芯片的凸点(Bump)盘布局方法 |
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JP2003133513A (ja) | 2003-05-09 |
KR20030022724A (ko) | 2003-03-17 |
GB2381379A (en) | 2003-04-30 |
US20060166395A1 (en) | 2006-07-27 |
SG120885A1 (en) | 2006-04-26 |
FR2829615B1 (fr) | 2006-12-08 |
GB0214019D0 (en) | 2002-07-31 |
FR2829615A1 (fr) | 2003-03-14 |
US20040026771A1 (en) | 2004-02-12 |
TW543132B (en) | 2003-07-21 |
US7045835B2 (en) | 2006-05-16 |
US20030049925A1 (en) | 2003-03-13 |
DE10240471A1 (de) | 2003-06-05 |
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