CN1392602A - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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Publication number
CN1392602A
CN1392602A CN02123158A CN02123158A CN1392602A CN 1392602 A CN1392602 A CN 1392602A CN 02123158 A CN02123158 A CN 02123158A CN 02123158 A CN02123158 A CN 02123158A CN 1392602 A CN1392602 A CN 1392602A
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China
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mentioned
conducting film
circuit arrangement
manufacture method
wiring layer
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CN02123158A
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CN1193417C (zh
Inventor
五十岚优助
坂本则明
小林义幸
中村岳史
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

本发明提供一种电路装置的制造方法，使用通过绝缘树脂(2)使第一导电膜(3)和第二导电膜(4)贴合的绝缘树脂片，用第一导电膜(3)形成第一导电配线层(5)，用第二导电膜(4)形成第二导电配线层(6)，使两者用多层连接手段(12)连接。将半导体元件(7)固定在覆盖第一导电配线层(5)的涂层树脂(8)上，借此用第一导电配线层(5)和第二导电配线层(6)实现多层配线构造，并且由于使形成厚的第二导电膜(4)在模塑后通过蚀刻减薄，而使第二导电配线层(6)也微细图形化。本发明解决了在制造工序中的绝缘树脂片的翘起严重的问题。

Description

电路装置的制造方法
                          技术领域
本发明涉及电路装置的制造方法，特别是涉及利用二个导电膜的箔型也能实现多层配线的电路装置的制造方法。
                          背景技术
近年来，IC组件随着在组装便携式机器和小型·高密集度组装机器上采用，而也必将使过去的IC组件及其组装概念发生大的改变，例如特开平2000-133678号公报中所描述的是关于采用作为绝缘树脂片的一例的即柔性片的聚酰胺树脂片的半导体装置的技术。
图13～图15采用柔性片50作为中间母材基片。另外，在各图上面所示的图面是平面图，在下面所示的图面是沿A-A线的剖视图。
首先准备在图13所示的柔性片50上通过粘接剂贴合铜箔图形51。该铜箔图形51随着组装的半导体元件是晶体管，IC的不同，其图形也不同，一般地说，形成焊接点51A，岛51B。而符号52是用于从柔性片50的里面取出电极的开口部，上述铜箔图形51露出。
接着把该柔性片50运送到芯片焊接器，如图14所示，组装半导体元件53。其后该柔性片50运送给引线焊接器，用金属细线54电连接焊接点51A和半导体元件53的焊接点。
最后如图15A所示，在柔性片50的表面上准备密封树脂55密封，在此为了被覆焊接点51A、岛51B、半导体元件53和金属细线54而进行连续自动模塑。
然后，如图15所示，设置焊锡和焊锡孔等连接手段，使其通过锡焊软融炉借助开口部52形成焊接点51和熔融着的球状焊锡56。然而因在柔性片50上半导体元件53形成为矩阵状，所以被切割成图14那样，彼此分别分开。
另外，在图15C中所示的剖视图是在柔性片50的两面上形成51A和51D作为电极。该柔性片50一般在两面形成图形后由制造商供给。
由于利用上述的柔性片50的半导体装置不用公知的金属框架，而且有能实现非常小型且薄的封装构造的优点，但因只用形成在大致为柔性片50的表面上的一层铜箔图形51进行配线，而存在不能实现多层配线构造的问题。
另外，为了实现多层配线构造而保持支持强度，又必需使柔性片50达到约200μ的足够的厚度，这又是与薄形化逆行的问题。
另外，关于制造方法，柔性片50运送到上述的制造装置例如芯片焊接器、引线焊接器、连续自动模塑装置、软熔炉等中后，要安装在所谓台或平台的部分上。
然而，当构成柔性片50的基材的绝缘树脂的厚度薄到50μm左右时，在形成在表面上的铜箔图形51的图形51的厚度也薄到9～35μm的情况下，存在如图16所示那样因翘起而使运送性变得非常差，并且使在上述的台或平台上的安装性也变得很差的缺点。这被认为是因绝缘树脂本身非常薄而产生翘起，因铜箔51与绝缘树脂的热膨胀系数的差引起翘起的结果。特别是在当不用玻璃交叉纤维作为芯材的结实的绝缘材料如图16中所示那样翘起时，从上方简单加压就会使其破裂。
另外，开口部52的部分因在模塑时从上面加压而使焊接点51A的周边向上翘起的力起作用，并且还使焊点51的连接性能变差。
另外，当构成柔性片50的树脂材料本身无柔性，并为提高导热性而掺入填加物时则会变硬，在该状态下存在用引线焊接器焊接时在焊接部分中出现裂纹的情况，而且即使在自动模塑时，在模具接触的部分上也存在出现裂纹的情况，该裂纹如图16所示那样因发生翘起而变得更严重。
迄今为止说明的柔性片50虽然是在里面上不形成电极的，但如图15C所示，也有在柔性片50的里面上形成电极51D的情况。这时电极51D与上述制造装置接触，由于与该制造装置间的运送手段的运送面接触，而存在在电极51D的里面上发生损伤的问题，因该损伤按原样作为电极构成，所以也存在以后因加热等在电极51D本身上出现裂纹的问题。
另外，当电极51D形成在柔性片50的里面上时，在自动模塑时，发生不能与台面接触的问题。这时，当如上所述那样柔性片50由硬的材料构成时，电极51D变成支点，由于电极51的周围被向下方加压，而存在使柔性片50上产生裂纹的问题。
本发明人为了解决这些问题而曾建议采用用绝缘树脂使薄的第一导电膜和厚的第二导电膜贴合的绝缘树脂片。
然而，在实现多层配线构造上用薄的第一导电膜形成细的图形，厚的第二导电膜在形成微细的图形时也存在不合适的问题。
                          发明内容
本发明的电路装置的制造方法通过由下述工序组成的方法解决上述的问题，这些工序包括：准备用绝缘树脂粘接第一导电膜和第二导电膜的绝缘树脂片的工序；在上述绝缘树脂片的所希望的位置上形成贯通第一导电膜和上述绝缘树脂的贯通孔，以使上述第二导电膜的里面选择地露出的工序；在上述贯通孔中形成多层连接手段，并使第一导电膜和第二导电膜电连接的工序；通过把上述第一导电膜蚀刻成所希望的图形来形成第一导电配线层的工序；在上述第一导电配线层上电绝缘地固定半导体元件的工序；用密封树脂层被覆上述第一导电配线层和上述半导体元件的工序；在为了使上述第二导电膜全面减薄而蚀刻上述第二导电膜后，通过蚀刻上述第二导电膜形成第二导电配线层的工序；在上述第二导电配线层的所希望位置上形成外部电极的工序。
由于第一导电膜和第二导电膜形成的厚，而即使绝缘树脂变薄，也能维持片状的电路基板的扁平性。
另外在用密封树脂层被覆第一导电配线层和半导体元件的工序中由第二导电膜保持机械强度，因其后由密封树脂层保持机械强度而可以容易地用第二导电膜形成第二导电配线层，结果使绝缘树脂不需要机械强度，可以薄到能保持电绝缘的厚度。
另外，由于运送模塑装置的下模具能通过面与第二层导电膜全部接触，而没有局部受压并能防止绝缘树脂发生裂纹。
另外，由于第一导电膜在通孔中形成多层连接手段后形成第一电导电配线层，而可不用掩模形成多层连接手段。
还有，由于使第二导电膜通过蚀刻减薄后加工第二导电配线层的图形，而可以同时实现第二导电配线层的微细图形化。
                           附图说明
图1是说明本发明的电路装置的制造方法的剖面图。
图2是说明本发明的电路装置的制造方法的剖面图。
图3是说明本发明的电路装置的制造方法的剖面图。
图4是说明本发明的电路装置的制造方法的剖面图。
图5是说明本发明的电路装置的制造方法的剖面图。
图6是说明本发明的电路装置的制造方法的剖面图。
图7是说明本发明的电路装置的制造方法的剖面图。
图8是说明本发明的电路装置的制造方法的剖面图。
图9是说明本发明的电路装置的制造方法的剖面图。
图10是说明本发明的电路装置的制造方法的剖面图。
图11是说明按照本发明制造的电路装置的平面图。
图12是说明本发明的电路装置的造方法的剖面图。
图13是说明现有技术中的半导体装置制造方法的图。
图14是说明现有技术中的半导体装置制造方法的图。
图15是说明现有技术中的半导体装置制造方法的图。
图16是说明现有技术中的柔性片的图。
                         具体实施方式
下面参照图1～图12说明本发明的电路装置的制造方法。
本发明的电路装置的制造方法包括：准备用绝缘树脂粘接第一导电膜和第二导电膜的绝缘树脂片的工序；在上述绝缘树脂片的所希望的位置上形成贯通第一导电膜和上述绝缘树脂的贯通孔，以使上述第二导电膜的里面选择地露出的工序；在上述贯通孔中形成多层连接手段，并使第一导电膜和第二导电膜电连接的工序；通过把上述第一导电膜蚀刻成所希望的图形来形成第一导电配线层的工序；在上述第一导电配线层上电绝缘地固定半导体元件的工序；用密封树脂层被覆上述第一导电配线层和上述半导体元件的工序；在为了使上述第二导电膜全面减薄而蚀刻上述第二导电膜后，通过蚀刻上述第二导电膜形成第二导电配线层的工序；在上述第二导电配线层的所希望位置上形成外部电极的工序。
本发明的第一工序在于：如图1所示那样准备用绝缘树脂2形成第一导电膜3和第二导电膜4粘接的绝缘树脂片1。
绝缘树脂片1的表面的大致全范围上形成第一导电膜，在其里面上也大致全范围上形成第二导电膜4。另外，绝缘树脂2和材料是由聚酰亚胺树脂或环氧树脂等高分子组成的绝缘材料，另外，第一导电膜3和第二导电膜4最好是以Cu为主材料的材料，或者是公知的引线构成材料，通过电镀法、蒸镀法或溅射法被覆在绝缘树脂2上，也可以把通压延法或电镀法形成的金属箔贴在绝缘树脂2上。
另外，绝缘树脂片1也可以用铸塑法形成，下面简单描述该制造方法。首先在平坦膜的第一导电膜3上涂敷糊状聚酰亚胺树脂，在平膜状的第二导电膜4上也涂敷糊状聚酰亚胺树脂。然后在使两个聚酰亚胺树脂半固化后互相贴合时，就制成绝缘树脂片1。因此具有在绝缘树脂片1上不要加强用的玻璃交叉纤维的优点。
本发明的特点在于使第二导电膜4比第一导电膜3形成的厚。
第一导电膜3的厚度形成为5～35μm左右，关照第一导电膜3以便尽可能薄的形成微细图形。第二导电膜4的厚度可以为70～200μm左右，以重视保持支持强度这一点。
因此，由于使第二导电膜形成的厚，而可以维持绝缘树脂片1的平坦性，可以防止在绝缘树脂2上诱发缺陷，裂纹等。
另外，第二导电膜4因经过各个工序而发生伤痕，但因为是在使厚的第二导电膜4全面减薄后形成图形，而可以除去该伤痕，并且由于能边维持平坦性边使密封树脂固化，而使密封部分的里面也变平坦，使形成在绝缘树脂片1的里面上的电极配置成扁平状。从而可以使组装基片上的电极与绝缘树脂片1的里面的电极接触，并可以防止焊接不良。
绝缘树脂2最好是聚酰亚胺树脂、环氧树脂等。在通过涂敷膏状物制成层的铸塑法的情况下，该膜厚为10μm～100μm左右。另外，在作为层形成的情况下，市售的片最薄膜厚是25μm，并且考虑热传导性，也可以在其中掺入填加物。作为填充材料可以考虑玻璃、氧化锡、氧化铝、氮化铝、碳化硅、氮化硼等。
这样可以把绝缘树脂2选择为掺入上述填料的低热阻树脂。超低热阻树脂或聚酰亚胺树脂，可以根据形成的电路装置的性质区分使用。
本发明的第二工序在于如图2所示那样，在绝缘树脂片1的所希望位置上形成贯通第一导电膜3和绝缘树脂2的贯通孔21，使第二导电膜选择地露出。
只使形成第一导电膜3的通孔21的部分露出后用光致抗蚀剂被覆全面，然后借助该光致抗蚀剂蚀刻第一导电膜。因为第一导电膜3是以铜为主材料的膜，所以用氯化亚铁或氯化亚铜作为蚀刻液进行化学蚀刻。通孔21的开口直径随着光刻法的分辩率而变化，但在此为50～100μm左右。另外，在进行该蚀刻时，第二导电膜4被粘接性的层覆盖保护与蚀刻液隔开。另外如果第二导电膜4本身充分的厚，且是在蚀刻后能维持平坦的膜厚，则即使稍许被蚀刻也没关系。另外，作为第一导电膜3也可以用Al、Fe、Fe-Ni等公知的引线骨架材料。
接着在除去光致抗蚀剂后，把第一导电膜3作为掩模，利用激光除去贯通孔2的正下方的绝缘树脂2，在通孔21的底上使第二导电膜4的里面露出，作为激光最好用二氧化碳激光。另外，在用激光使绝缘树脂蒸发后，在开口部的底部有残碴时，用高锰酸碳酸钠或过硫酸铵等湿法蚀刻，以除去残碴。
在本工序中当第一导电膜3薄到10μm左右时，可以在用光致抗蚀剂被覆通孔21以外的地方之后，用二氧化碳激光使第一导电膜3和绝缘树脂成批形成通孔21。在这种情况下必需预先进行粗化第一导电膜3的表面的黑化处理工序。
本发明的第三工序在于：如图3所示，在通孔21中形成多层连接手段，使第一导电膜3和第二导电膜4电连接。
在包含通孔21的第一导电膜3的全面上形成使第二导电膜4和第一导电膜3进行电连接的多层连接手段12即镀膜。该镀膜通过非电解镀和电解镀两种方法形成，在此通过非电解镀至少在含通孔21的第一导电膜3的整个面上形成约2μm的Cu。因此，为了使第一导电膜3和第二导电膜4电导通，而再次通过把该第一和第二导电膜3、4作为电极进行电解镀，镀约20μm的铜，借此用铜埋入通孔21，形成多层连接手段12。另外，如果采用商品外为工バラュ一ジラィト电镀液，则也可以选择地只埋入通孔21。并且镀膜在此是采用Cu，但也可以采用Au、Ag、Pd等，并且也可以使用掩模进行局部电镀。
本发明的第四工序在于：如图4和图5所示那样，使第一导电膜蚀刻成所希望的图形，以便形成第一导电配线层5。
在第一导电膜3上用所希望的图形的光致抗蚀剂被覆，通过化学蚀刻形成从焊接接点10和从焊接接点10向中心延伸的第一导电配线层5。因第一导电膜3以Cu为主材料，所以蚀刻液可以用氯化亚铁或氯化亚铜。
由于第一导电膜3的厚度形成为5～35μm左右，所以第一导电配电线层5可以形成为50μm以下的微细图形。
接着使第一导电配线层5的焊接接点10露出，其它部分用涂层树脂8被覆。使涂层树脂8通过丝网印刷附着被溶剂溶解的环氧树脂等，然后使其固化。
另外如图5所示，在焊接接点10上考虑焊接性能而形成Au、Ag等镀膜22，该镀膜22以涂层树脂8为掩模通过无电场镀选择地附着在焊接接点10上。
本发明的第五工序在于：如图6所示，在第一导电配线层5上电绝缘地固定半导体元件7。
半导体元件7用绝缘粘接树脂25模按一对芯片的原样接合在涂层树脂8上，因半导体元件7和其下面的第一导电配线层5被涂层树脂5电绝缘，所以虽然第一导电配线层5在半导体元件7的下面，也能自由配线，从而实现多层配线构造。
另外，半导体元件7的各电极接点9通过连接引线11连接在形成在周边的第一导电配线层5的一部分即焊接接点10上。半导体元件7也可以面朝下安装。这时焊锡孔和凸出设置在半导体元件7的各电极接点9的表面上，在绝缘树脂片1的表面上的与焊锡孔的位置对应的部分上设置与焊接接点10相同的电极(见图12)。
下面就使用引线焊接时的绝缘树脂片1的优点进行说明。通常焊接金属线引线时，加热到200℃～300℃。这时如第二导电膜很薄，则绝缘树脂片1就翘起，当在该状态下通过焊接接点对绝缘树脂片1加压时，绝缘树脂可能发生龟裂。如果在绝缘树脂2中掺入填加材料时，则因材料本身变硬失去柔软性，龟裂发生更严重。并且因为树脂与金属比柔软，所以在焊接Au和Al时，加压和超声波的能量发散掉。并且通过使绝缘树脂2变薄并使第二导电膜4本身形成的厚，可以解决这些问题。
本发明的第六工序在于：如图7所示那样，用密封树脂层13被覆第一导电配线层5和半导体元件7。
将绝缘树脂片1放置在模塑装置中进行树脂模塑。作为模塑方法，可以用连续自动模塑、喷射模塑、涂敷、浸涂等。但如考虑成批生产性，自动连续模塑和喷射模塑是适合的。
在本工序中，绝缘树脂片1必需在扁平状态下与模腔的下模具接触，厚的第二导电膜起这个作用。并且在从模腔中取出后，通过第二导电膜4维持封装部分的平坦性，直到密封树脂层13的收缩全部完成为止。
也就是说，本工序中的绝缘树脂片1的机械支持的任务由第二导电膜4承担。
本发明的第七工序在于：如图8和图9所示那样，在为了使第二导电膜4全面减薄而进行蚀刻后，通过把第二导电膜4蚀刻成所希望的图形来形成第二导电配线层6。
如图8所示，不用掩模蚀刻第二导电膜4，以使其全面变薄。蚀刻可以用氯化亚铁或氯化亚铜的化学蚀刻，将第二导电膜4的厚度从当初的70～200μm左右均匀地减薄到约一半的厚度35μm左右。这时可以除去在以前的工序中在第二导电膜上引起的伤痕。
接着如图9所示，使第二导电膜被覆所希望图形的光致抗蚀剂，用化学蚀刻形成第二导电配线层6。由于第二导电膜在本工序中被减薄，所以可以实现50μm以下的微细图形。第二导电配线层6如图2所示那样以一定间隔配列，分别通过多层连接手段12与第一导电配线层5和电连接来实现多层配线构造。另外根据需要也可以在剩余空白部分上形成用于使第一导电配线层5交叉的第二导电配线层6。
本发明的第八工序在于：如图10所示那样在第二导电配线层6的所希望的位置上形成外部电极14。
通过使形成外部电极14的部分露出用丝网印刷通过溶剂溶解的环氧树脂等，用涂层树脂15被覆第二导电配线层15的大部分。接着通过焊锡软熔或焊锡膏的丝网印刷同时在该露出部分上形成外部电极14。
最后，因为多个电路装置在绝缘树脂片1上形成为矩阵状，所以可以通过切割密封树脂层13和绝缘树脂片1，把这些电路装置分离成单个电路装置。
下面参照图11说明利用具体化的本发明的制造方法的电路装置。首先用实线表示的图形是第一导电配线层5，用虚线表示的图形是第二导电配线层6。在第一导电配线层5在周边设置焊接接点10以使它们包围半导体元件7，并在一部分上与配置成两段并具有多接点的半导体元件7相对应。焊接接点10通过连接引线11与半导体元件7所对应的电极接点9相连接，微细图形的第一导电配线层5从焊接接点10多数向半导体元件7的下面延伸。通过用黑圆圈表示的多层连接手段12与第二导电配线层6连接。并且第二导电配线层6也形成微细图形，还形成多个外部电极14。
按照该构造，即使具有200个以上连接点的半导体元件，也能利用第一导电配线层5的微细图形用多层配线构造延伸到微细图形化的所希望的第二导电配线层6上，并从设置在第二导电配线层6上的外部电极向外部电路进行连接。
在图12中示出了半导体元件7以面朝下的方式组装的构造。凡与图10相同的构成要素赋予相同的符号。在半导体元件7上设置凸出电极31，该凸出电极31与连接点电极相连。涂层树脂8与半导体元件7的间隙被末充满的树脂32充填。按照该构造可以没有连接引线，从而可以使密封树脂层13的厚度进一步变薄。并且外部电极14也能在蚀刻第二导电膜后用金或钯镀膜33被覆的凸出电极来实现。
本发明具有以下的优点：
第一，在直到用密封树脂层模塑之前可以用第二导电膜消除翘起作为绝缘树脂片，并使运送性能等提高。
第二，由于用二氧化碳激光形成在绝缘树脂中形成的通孔，而可以在其后立即进行多层连接手段的镀敷，使工序变得非常简单。如用铜镀层作为多层连接手段，则与铜的第一导电膜和第二导电膜变为同一材料，使其后的工序变简单。
第三，因为可以用镀膜实现多层连接手段，所以在形成第一导电配线层之前不用掩模就可形成多层膜连接手段，并且可在第一导电配线层形成的同时形成图形，从而使多层连接手段的形成非常容易。
第四，因为用第二导电膜进行绝缘树脂片的机械支持直到密封树脂层形成时，并且第二导电配线层形成后用密封树脂层进行支持绝缘树脂片，所以可以实现绝缘树脂的机械强度不受限制地非常薄型的组装方法。
第五，即使绝缘树脂本身是硬的，并且即使因掺入填充料而变硬，但因为用第一和第二导电膜覆盖两面，而在制造工序中绝缘树脂片本身的扁平性提高，从而可以防止发生裂纹。
第六，由于绝缘树脂片在里面上形成厚的第二导电膜，所以可以作为用于芯片的模连接引线焊接，半导体元件密封的支持基板使用。并且即使在绝缘树脂材料本身柔软的情况下，也能提高引线焊接时的能量的传送和提高引线焊接性能。
第七，蚀刻第二导电膜，以使在用密封层后模塑后使第二导电膜厚度减少一半，所以可实现第二导电配线层微细化，可以与第一导电配线层一起实现非常微细图形的电路装置。

Claims (18)

1.一种电路装置的制造方法，其特征在于，包括：
准备用绝缘树脂粘接第一导电膜和第二导电膜的绝缘树脂片的工序；
在上述绝缘树脂片的所希望的位置上形成贯通第一导电膜和上述绝缘树脂的贯通孔，以使上述第二导电膜的里面选择地露出的工序；
在上述贯通孔中形成多层连接手段，并使第一导电膜和第二导电膜电连接的工序；
通过把上述第一导电膜蚀刻成所希望的图形来形成第一导电配线层的工序；
在上述第一导电配线层上电绝缘地固定半导体元件的工序；
用密封树脂层被覆上述第一导电配线层和上述半导体元件的工序；
在为了使上述第二导电膜全面减薄而蚀刻上述第二导电膜后，通过蚀刻上述第二导电膜形成第二导电配线层的工序；
在上述第二导电配线层的所希望位置上形成外部电极的工序。
2.如权利要求1所述的电路装置的制造方法，其特征在于：上述第一导电膜和第二导电膜由铜箔制成。
3.如权利要求1所述的电路装置的制造方法，其特征在于：使上述第一导电膜比上述第二导电膜形成得薄，使上述第一导电配线层微细图形化。
4.如权利要求1所述的电路装置的制造方法，其特征在于：使上述第二导电膜比上述第一导电膜形成得厚，用上述第二导电膜机械地支持直到用上述密封树脂层被覆的工序为止。
5.如权利要求1所述的电路装置的制造方法，其特征在于：在用上述密封树脂层被覆的工序后，用上述密封树脂层机械地支持。
6.如权利要求1所述的电路装置的制造方法，其特征在于：上述贯通孔是在蚀刻上述第一导电膜后，把上述第一导电膜作为掩模，用激光蚀刻上述绝缘树脂而形成。
7.如权利要求6所述的电路装置的制造方法，其特征在于：上述激光蚀刻用二氧化碳气体激光。
8.如权利要求1所述的电路装置的制造方法，其特征在于：上述多层连接手段用导电金属的无电场镀层和电场镀层形成在上述通孔和上述第一导电膜表面上。
9.如权利要求1所述的电路装置的制造方法，其特征在于：在上述第一导电配线层形成后，留下所希望的位置，用涂层树脂被覆。
10.如权利要求9所述的电路装置的制造方法，其特征在于：在从上述第一导电配线层的上述涂层树脂中露出的位置上形成金或银镀层。
11.如权利要求9所述的电路装置的制造方法，其特征在于：在上述涂层树脂上固定上述半导体元件。
12.如权利要求10所述的电路装置的制造方法，其特征在于：通过连接引线连接上述半导体元件的电极和上述金或银镀层。
13.如权利要求1所述的电路装置的制造方法，其特征在于：上述密封树脂层用连续自动模塑形成。
14.如权利要求1所述的电路装置的制造方法，其特征在于：使上述第二导电膜不用掩模全面均匀蚀刻减薄。
15.如权利要求1所述的电路装置的制造方法，其特征在于：用涂层树脂被覆上述第二导电配线层的大部分。
16.如权利要求1所述的电路装置的制造方法，其特征在于：上述外部电极通过焊锡的丝网印刷附着焊锡后加热熔融形成。
17.如权利要求1所述的电路装置的制造方法，其特征在于：上述外部电极通过焊锡的软熔形成。
18.如权利要求1所述的电路装置的制造方法，其特征在于：上述外部电极通过蚀刻成所希望的图形，然后将其表面镀金或钯来形成。
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JP2004335710A (ja) * 2003-05-07 2004-11-25 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2005095977A (ja) * 2003-08-26 2005-04-14 Sanyo Electric Co Ltd 回路装置
TWI255672B (en) * 2004-03-03 2006-05-21 Sanyo Electric Co Manufacturing method of multilayer substrate
JP4235834B2 (ja) * 2005-07-12 2009-03-11 セイコーエプソン株式会社 半導体装置の製造方法
JP4907178B2 (ja) * 2006-01-26 2012-03-28 パナソニック株式会社 半導体装置およびそれを備えた電子機器
US7830024B2 (en) * 2008-10-02 2010-11-09 Advanced Semiconductor Engineering, Inc. Package and fabricating method thereof
CN102204418B (zh) * 2008-10-30 2016-05-18 At&S奥地利科技及系统技术股份公司 用于将电子部件集成到印制电路板中的方法
US8220143B2 (en) * 2009-05-22 2012-07-17 Kuang Hong Precision Co., Ltd Method for a plastic lead frame with reflective and conductive layer
JP6402217B2 (ja) * 2017-03-15 2018-10-10 アオイ電子株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
FI982568A (fi) * 1997-12-02 1999-06-03 Samsung Electro Mech Menetelmä monikerroksisen painetun piirilevyn valmistamiseksi
JP2003007918A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
JP2003007916A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100358101C (zh) * 2004-03-17 2007-12-26 三洋电机株式会社 电路装置及其制造方法
CN102439704A (zh) * 2009-05-06 2012-05-02 马维尔国际贸易有限公司 封装技术及封装配置
CN102439704B (zh) * 2009-05-06 2016-11-16 马维尔国际贸易有限公司 封装技术及封装配置
CN103579190A (zh) * 2012-08-02 2014-02-12 英飞凌科技股份有限公司 芯片封装件和用于制造芯片封装件的方法
CN114501856A (zh) * 2021-12-13 2022-05-13 深圳市华鼎星科技有限公司 多层导电线路及其制作方法及显示模组

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