CN1354285A - 高锡焊料隆起的电化学腐蚀 - Google Patents

高锡焊料隆起的电化学腐蚀 Download PDF

Info

Publication number
CN1354285A
CN1354285A CN01137197A CN01137197A CN1354285A CN 1354285 A CN1354285 A CN 1354285A CN 01137197 A CN01137197 A CN 01137197A CN 01137197 A CN01137197 A CN 01137197A CN 1354285 A CN1354285 A CN 1354285A
Authority
CN
China
Prior art keywords
concentration
tin
lead
plan
weight percent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01137197A
Other languages
English (en)
Other versions
CN1184362C (zh
Inventor
L·A·范蒂
J·M·科特
D·E·艾斯塔特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ultratech Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1354285A publication Critical patent/CN1354285A/zh
Application granted granted Critical
Publication of CN1184362C publication Critical patent/CN1184362C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01084—Polonium [Po]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)
  • Preventing Corrosion Or Incrustation Of Metals (AREA)

Abstract

一种含水的电化学腐蚀剂,在存在有一种或多种不打算腐蚀的金属的情况下用来对一些金属进行腐蚀,该腐蚀剂包括:甘油,其浓度为1.30－1.70M;硫酸盐化合物,其硫酸根的离子浓度为0－0.5M;磷酸盐化合物,其磷酸根的离子浓度为0.1－0.5M。

Description

高锡焊料隆起的电化学腐蚀
发明背景
本发明涉及金属的选择性腐蚀，更具体地说，涉及在存在有各种焊料的情况下金属的电化学腐蚀。
C4是一种先进的微电子芯片的包装和连接技术。“C4”代表可控塌陷芯片连接(Controlled Collapse Chip Connection)。C4也叫“焊料隆起(solder bump)”，“焊料球”，以及“倒扣片(flip chip)”，而且这些术语也可联合起来使用，如“C4焊料隆起”。
C4的基本思想是将芯片(半导体器件)，芯片封组，或这样的其它单元连接起来，它是通过这些单元的两表面之间的一些焊料隆起来完成的。这些导电焊料的细小隆起将把连接单元上的相应两金属垫之间的间隙跨接起来。每块金属垫都在另一单元的表面上有一金属垫与之对应；该等金属垫的排列都呈镜象。当将这些单元压在一起并加热时，该第一单元的金属垫上的焊料隆起就会与该第二单元上的相应导电金属垫(没有焊料隆起)接触并被软熔，就会使该焊料隆起局部塌陷并在相应金属垫之间形成一些连接。
在C4中该等焊料隆起被直接做在一个单元的那些金属垫上。这些金属垫与其它零件之间被每块金属垫周围的绝缘基片电绝缘。该基片可以是硅(Si)，也可是某种其它的材料。该金属垫的底部是与该芯片电路电连接的。
C4的主要应用是将一些芯片与载体或封组连结起来。芯片通常都是以矩形阵列的形式做在被称作“晶片”的单晶硅片上。在每块晶片上制做很多芯片，然后将该晶片分裂成一些单个的芯片并将这些芯片“封装”在一些足够大的单元中，以便操作处理。将该等C4焊料隆起放置在这些芯片上，同时还将它们连接在晶片中。
将晶片做得尽可能大，以便减少为制备一定数目的芯片所必须处理的晶片数。为了同样的理由，(其中)还将这些芯片做得尽可能小。这样，最好的C4制备系统就是能在一大面积上制备成千的很小的、间隔很近的，每个都是精确地安放的焊料隆起的系统。
当将两表面按压在一起时，C4的焊料隆起应该被机械地很好地固定在它们的金属垫上，否则它们就可被撕扯开。应该知道，一复杂的装置，如计算机可以具有几十个芯片和成百上千个C4的焊料球连接点，只要有一个这种隆起失灵则会使整个装置无用。该C4隆起的连接要求仔细的设计。
形成焊料隆起的一种方法利用了溅射或真空沉积技术。在这种方法中，焊料金属在真空腔中被汽化。该金属蒸气会使该真空腔中的每件东西上覆盖一层该蒸发金属的薄膜。为了在基片上形成焊料隆起，可使该蒸气通过固定在该基片上的金属掩模中的孔。通过这些孔的焊料蒸汽就在该冷表面上凝结成一些焊料隆起。这种方法需要一高真空腔来容纳该基片、掩模、和闪蒸器。
制备焊料隆起的另一技术是电沉积，也叫电化学涂镀或电镀。这种方法也使用掩模并只在所选择的位置上形成焊料隆起，但该技术与该蒸发法是很不相同的。
电解形成C4焊料隆起过程的第一步是在打算形成隆起的该晶片上沉积一连续的金属薄膜的叠层(stack)。这就是所谓的“种子层”，它起着双重作用。首先，它在焊料隆起的电解沉积过程中提供了一电流的导电通路。第二，它保留在焊料隆起的下面，形成C4的球形限制冶金(ball limiting metallurgy)(BLM)的基础。因而，为了在该晶片的整个横向跨度上能进行均匀的电沉积，必须至少有一层是足够导电的。该底层必须很好地粘附在下面的半导体器件上以便钝化，而顶层必须与该焊料进行充分的相互作用以便形成可靠的连接。此外，该BLM可以包含一些阻挡层，以避免焊料与下面的器件组分发生有害的相互作用。最后，由混合堆叠(composite stack)所产生的应力应足够小，以便在各种热学和机械应力范围上维持该C4连接的可靠性。考虑到所有这些因素，种子层通常由一种以上的金属层组成，而且这些不同的层必须在处理过程中的某一时刻从C4之间被腐蚀掉，以便各互连点电绝缘。
在敷设种子层之后，第二步就是用光刻法形成一掩模。在该种子层上敷设一层光刻胶，并使它曝光。未曝光的光刻胶(如一负性光刻胶)那时就可被洗去以便将固化的光刻胶留下作掩模。该掩模具有一些孔列，焊料隆起就将沉积在这些孔所在的位置上。
第三步是将焊料电沉积(电镀)到上述掩模孔中。
在上述焊料隆起形成之后，就将固化的光刻胶的掩模除去。这时该基片就被连续的种子层和大量的焊料隆起所覆盖。然后，通过适当的湿浸蚀和/或电腐蚀工艺将该焊料隆起之间的种子层除去以便使它们电绝缘。
典型地用于C4焊料隆起的焊料为97wt％的Pb和3wt％的Sn。典型的种子层总是包括一TiW层、一形成过渡相的Cr/Cu层(phased Cr/Culayer)或Cr/Cu合金、和一Cu层。用来同时除去该Cr/Cu和Cu层的方法是电腐蚀方法，它包括一种含有甘油和硫酸钾的水溶液，就象在Datta等的美国专利5,486,282中所公开的一样，该公开已作为参考结合在本专利中。该甘油用作润湿剂，而硫酸钾的目的则是双重的。第一，该硫酸钾赋予该溶液电解导电率。第二，自由的硫酸根离子易于与高Pb的焊料隆起络合，形成一保护外壳，在电腐蚀过程中这外壳能防止焊料隆起被溶解。然后利用湿浸蚀方法对该TiW层进行腐蚀，该湿浸蚀方法包括含有过氧化氢、EDTA、和硫酸钾的含水腐蚀剂，就象在Datta等的美国专利5,462,638和Fanti等的美国专利6,015,505所公开的一样，上述公开已作为参考结合在本专利中。该焊料隆起上的“外壳”在紧接着的清洗过程中被除去。
更近的一些应用利用了一低熔点的焊料作C4的隆起以便能进行低温的芯片连接。这样的一种低熔点焊料可以是包括63wt％的Sn和37wt％的Pb的铅/锡焊料。
Cotte等的美国专利5,800,726提出了一种水溶液以便在存在有易熔焊料的情况下对各种金属，如TiW，的湿浸蚀，该专利内容已作为参考结合在本发明中。这种溶液包括磷酸钾、过氧化氢、EDTA、以及草酸。
本发明者们已认识到，现时的电腐蚀方法对于高Sn焊料隆起并非有效的。理由是Sn对于硫酸根离子并不是很活泼的，因而现行技术的电腐蚀溶液，如上述Datta等的美国专利5,486,282中所公开的那种，并不能在电腐蚀过程中在焊料隆起上形成保护外壳。不良的结果是从该焊料隆起浸出大量的Sn。此外，该溶解下来的Sn会自由地重新沉积在TiW上并与TiW络合，使得该TiW层对于传统的湿浸蚀来说是不可渗透的。
分层的焊料结构使问题更加复杂，例如，在这种分层结构中，低熔点的高Sn焊料隆起就被沉积在一高熔点的高Pb焊料隆起上。
这样，本发明者们就认识到，需要一种这样的腐蚀工艺，它要既能有效地电腐蚀金属而又不影响那些至少部分包含有高Pn的焊料的焊料隆起。
因此，本发明的目的在于对具有一些有待电腐蚀的金属和不想被腐蚀的高Sn的焊料隆起的基片进行电腐蚀。
本发明的另一目的在于对具有一些有待电腐蚀的金属和不想被腐蚀的包含有高Sn焊料隆起和高Pb焊料隆起的焊料分层结构的基片进行电腐蚀。
本发明的这些和其它的目的从下面的描述并结合附图来看将会变得更加明显。
发明概述
本发明的目的已由下述方法实现：在存在有一种或多种不想被腐蚀的金属的情况下，按照本发明的第一方面提供一种含水的电化学腐蚀剂，用来对一些金属进行腐蚀，该腐蚀剂包括：
甘油，其浓度为1.30-1.70M；
硫酸盐化合物，其硫酸根的离子浓度为0-0.5M；
磷酸盐化合物，其磷酸根的离子浓度为0.1-0.5M。
在一物件中存在有一种或多种不想被溶解的金属的情况下，按照本发明的第二方面，提供了一种方法，用来选择性地溶解一种或多种打算溶解的金属，该方法包括下述步骤：
用一种含水的腐蚀剂对想要溶解的金属进行电化学腐蚀，该含水腐蚀剂包括：甘油，其浓度为1.30-1.70M；硫酸盐化合物，其硫酸根离子浓度为0-0.5M；以及磷酸盐化合物，其磷酸根离子浓度为0.1-0.5M。
按照本发明的第三方面，提供了一种用来选择性地腐蚀一物件的方法，该方法包括下述步骤：
提供一物件，该物件具有一种或多种想要溶解的金属，同时还存在有一种或多种不想被溶解的金属；
用一种含水的腐蚀剂对想要溶解的金属进行电化学腐蚀，该含水腐蚀剂包括：甘油，其浓度为1.30-1.70M；硫酸盐化合物，其硫酸根离子浓度为0-0.5M；以及磷酸盐化合物，其磷酸根离子浓度为0.1-0.5M。
附图简介
被认为是本发明的一些新颖的特点和本发明的一些特征的要素都被详细地陈述在附录的权利要求书中。所有附图都仅是为了图示的目的，因而都未按比例画出。但是，通过参考后面的详述及结合这些附图，本发明本身就结构和操作方法来说都是可最好理解的，其中，
图1是一芯片的侧视图，它表示该种子层和第一种焊料分层结构，该结构仅包含有主要是Sn的焊料。
图2是一芯片的侧视图，它表示出该种子层和第二种焊料分层结构，该结构包含有高Sn的焊料和高Pb的焊料。
图3是在利用现行技术的腐蚀剂进行电腐蚀之后图2芯片的侧视图。
图4是为了除去该种子层的最后一层而进行湿侵蚀之后的图3芯片的侧视图。
图5是图4所示芯片的表面图示，它表示出该种子层的不完全腐蚀。
图6是在用本发明所述的腐蚀剂进行电腐蚀之后的图2芯片的侧视图。
图7是为了除去该种子层的最后一层而进行湿侵蚀之后的图6芯片的侧视图。
图8是图7所示芯片的表面图示，它表示出该种子层的完全腐蚀。
发明详述
详细参考附图，特别是参考图1，该图表示出第一种芯片10，它由半导体材料12、种子层14和焊料隆起24构成。如早先所指出的那样，该种子层14实际上是一多层结构。为了图示而非限制的目的，一种典型的层组合的第一层16为TiW合金(例如，10wt％的Ti和90wt％的W)，第二层18为形成过渡相的Cr/Cu(phased Cr/Cu)或Cr/Cu合金，第三层20为Cu。还可有，例如，一镍的阻挡层22。
在芯片10上的焊料隆起24主要包含Sn的焊料。这样的焊料可以由适度的Sn含量，如60wt％或更多的Sn和40wt％或更少的Pb构成，也可由高Sn含量，如95wt％或更多的Sn和保持平衡的Pb含量构成。而且，该焊料还可包括主要是含Sn的一些无Pb合金，如Sn/Ag、Sn/Cu、Sn/Ag/Cu、以及Sn/Bi合金，这里仅列举了几个。
现在参考图2，该图表示出第二种芯片30，它是由半导体材料12、种子层14、和焊料隆起32构成。种子层14可与图1所示的种子层相同，也可不同，这取决于具体应用。同样，第二种芯片30也可具有阻挡层22。第二种芯片30含有一些焊料隆起32。但是，在这种情形，焊料隆起32却包括由一较高熔化温度的焊料34和一较低熔化温度的焊料36组成的一焊料分层结构。图2所示的该焊料分层结构仅只是为了图示的目的，如果需要，还可有另外一些焊料层。
较高熔化温度的焊料34可以是高Pb的焊料，具有95-97wt％的Pb，余下的是Sn。较低熔化温度的焊料36可以是上面提及的任何中度的Sn含量、高Sn含量或无Pb的合金。
余下的讨论将集中在第二种芯片30上，但应明白本发明同样适用于第一种芯片10。
现在来参看图3，第二种芯片30已被包括甘油和硫酸钾的传统的含水腐蚀剂电腐蚀过了。这种腐蚀剂的组成为1.5M的甘油和0.35M的K2SO4(硫酸钾)。电池电压为14.0伏，工件与电极之间的间隔为3.0mm，脉冲保持时间与间隙之比为20％。
如从图3所能看见的那样，在电腐蚀过程中，较高熔化温度的焊料34已被一保护性外壳所保护起来，而较低熔化温度的焊料36却被腐蚀了，这就导致了的有害的Sn的损失和随之而来的焊料隆起32中成分的变化。而且，来自较低熔化温度焊料36的一些Sn 39已重新沉积在该种子层的第一层16上，而且甚至可与之络合。
紧接着，将第二种芯片30在传统的含水腐蚀剂中进行了湿浸蚀，所用腐蚀剂包括30wt％的过氧化氢、7.8g/1 K-EDTA以及1.1M的硫酸钾，其腐蚀周期为330秒。该腐蚀槽的温度设定为50℃。湿浸蚀后的结果图示在图4和图5中，图中可以看到第一层16已被基本除去，留下第二种芯片30的表面42大部分没有该第一层16。另一方面，Sn的沉积物39(如图3所示)妨碍了第一层16的某些区域的腐蚀，因而留下了一些没有被腐蚀掉的第一层16的一些区域40。
如图3至5所示芯片结构是不希望的，而且可能导致高的产率损失。如所知道的那样，在芯片处理的这个阶段的任何产率损失都是代价很高的。
现在来参看图6，第二种芯片30按照本发明被含水腐蚀剂所腐蚀。
本发明所用的该含水的电化学腐蚀剂的组成将包括：1.30-1.70M(最好为1.5M)的甘油(HOCH2(OH)CH2OH)，0-0.5M(最好0.35M)的硫酸根离子浓度和0.1-0.5M(最好为0.15M)磷酸根离子浓度。该含水腐蚀剂的pH值应为4-9(标称为5)，该电池电压应为13-17伏(标称为14.5)，电极间隔为3.0mm，以及占空比为10-30％(最好为20％)。
该硫酸根离子和磷酸根离子都可从任意相应的盐类产生。硫酸钾和磷酸钾都属于这些盐类，而硫酸钠或磷酸钠也可用于本发明的这些目的。
硫酸根和磷酸根离子的相对含量应根据存在的高Pb和高Sn焊料的量来调节。如果高Pb和高Sn焊料两者都存在，则为了保护这些焊料就必须存在硫酸根和磷酸根两种离子。如果不存在高Pb焊料，则就不需存在硫酸根离子。作为最小值来说，硫酸根离子和磷酸根离子必须提供一足够高的溶液电导率以便在合理的电压下进行电腐蚀。
在焊料隆起存在的情况下可被腐蚀的金属包括钛、钨、铬、铜、镍、以及它们的合金。在焊料隆起存在的情况下可被电腐蚀的金属包括各种金属叠层(metal stack)，包括Cu、Cr/Cu、Cu/Ni、和Cr/Cu/Ni等合金。
作为本发明的一种优选腐蚀剂的例子，用于第二种芯片30电腐蚀的腐蚀剂包含1.5M的甘油、0.35M的K2SO4(硫酸钾)、0.15M的K3PO4(磷酸钾)。用磷酸将pH值调到5.0。电池电压为14.0伏，电极间隔为3.0mm，以及占空比为20％。由硬壳35保护各个焊料隆起。第二和第三层18、20分别都被除去，而且没有残留物留在该第一层16上。
然后，将第二种芯片30放在传统的含水腐蚀剂中进行湿浸蚀，该腐蚀剂包括30wt％的过氧化氢、7.8g/l K-EDTA、和1.1M的硫酸钾，腐蚀周期为330秒。该腐蚀槽的温度被设定为50℃。结果被图示于图7和图8中，在图中可看到该第一层16已完全被除去，留下的第二种芯片30的表面42上没有任何的残留物。
在湿浸蚀后保护性外壳38仍保留在适当的地方，在湿浸蚀完成后再用甲磺酸将其除去。
已发现，本发明的使用大大地提高了电腐蚀过程的产率。
对于与本公开有关的技术领域的业内人士来说，显然可以对本发明进行一些超出此处所具体描述的那些实施例的其它改进，而并不偏离本发明的精神。因此，这些改进都被认为是在只受附录的 限制的本发明范围之内。

Claims (21)

1.一种含水的电化学腐蚀剂，用于在存在有一种或多种不打算腐蚀的金属的情况下对一些金属进行腐蚀，该腐蚀剂包括：
甘油，其浓度为1.30-1.70M；
硫酸盐化合物，其硫酸根的离子浓度为0-0.5M；
磷酸盐化合物，其磷酸根的离子浓度为0.1-0.5M。
2.按照权利要求1所述的电化学腐蚀剂，其特征在于：该腐蚀剂的pH值为4-9。
3.按照权利要求1所述的电化学腐蚀剂，其特征在于：该不打算腐蚀的一种或多种金属是从由铅、锡、以及它们的合金构成的组群中选出的。
4.按照权利要求1所述的电化学腐蚀剂，其特征在于：该不打算腐蚀的一种或多种金属是从由下列的一些焊料构成的组群中选出的：高铅/锡焊料，其铅含量的重量百分比大于95，其余为锡；中等比率的铅/锡焊料，其铅含量的重量百分比小于40，其余为锡；高锡/低铅焊料，其锡含量的重量百分比大于95，其余为铅；无铅焊料，其锡含量的重量百分比大于95；以及它们的组合。
5.按照权利要求1所述的电化学腐蚀剂，其特征在于：打算腐蚀的那些金属是从由铬、铜、镍、以及它们的合金构成的组群中选出的。
6.按照权利要求1所述的电化学腐蚀剂，其特征在于：该硫酸盐化合物的浓度为0.2-0.5M。
7.按照权利要求1所述的电化学腐蚀剂，其特征在于：该甘油的浓度大约为1.4M，该硫酸盐的浓度大约为0.35M，而该磷酸盐的浓度大约为0.15M。
8.在一物件中在存在有一种或多种不打算溶解的金属的情况下用来选择性地溶解一种或多种打算溶解的金属的方法，该方法包括下述步骤：
用一种含水的腐蚀剂对打算溶解的金属进行电化学腐蚀，该含水腐蚀剂包括：甘油，其浓度为1.30-1.70M；硫酸盐化合物，其硫酸根离子浓度为0-0.5M；以及磷酸盐化合物，其磷酸根离子浓度为0.1-0.5M。
9.按照权利要求8所述的方法，其特征在于：该腐蚀剂的pH值为4-9。
10.按照权利要求8所述的方法，其特征在于：该不打算腐蚀的一种或多种金属是从由铅、锡、以及它们的合金构成的组群中选出的。
11.按照权利要求8所述的方法，其特征在于：该不打算腐蚀的一种或多种金属是从由下列的一些焊料构成的组群中选出的：高铅/锡焊料，其铅含量的重量百分比大于95，其余为锡；中等比率的铅/锡焊料，其铅含量的重量百分比小于40，其余为锡；高锡/低铅焊料，其锡含量的重量百分比大于95，其余为铅；无铅焊料，其锡含量的重量百分比大于95；以及它们的组合。
12.按照权利要求8所述的方法，其特征在于：打算腐蚀的那些金属是从由铬、铜、镍、以及它们的合金构成的组群中选出的。
13.按照权利要求8所述的方法，其特征在于：该硫酸盐化合物的浓度为0.2-0.5M。
14.按照权利要求8所述的电化学腐蚀剂，其特征在于：该甘油的浓度大约为1.4M，该硫酸盐的浓度大约为0.35M，而磷酸盐的浓度大约为0.15M。
15.一种用来选择性地腐蚀一物件的方法，该方法包括下述步骤：
提供一物件，该物件具有一种或多种打算溶解的金属，同时还存在有一种或多种不打算溶解的金属；
用一种含水的腐蚀剂对打算溶解的金属进行电化学腐蚀，该含水腐蚀剂包括：甘油，其浓度为1.30-1.70M；硫酸盐化合物，其硫酸根离子浓度为0-0.5M；以及磷酸盐化合物，其磷酸根离子浓度为0.1-0.5M。
16.按照权利要求15所述的方法，其特征在于：该腐蚀剂的pH值为4-9。
17.按照权利要求15所述的方法，其特征在于：该不打算腐蚀的一种或多种金属是从由铅、锡、以及它们的合金构成的组群中选出的。
18.按照权利要求15所述的方法，其特征在于：该不打算腐蚀的一种或多种金属是从由下列的一些焊料构成的组群中选出的：高铅/锡焊料，其铅含量的重量百分比大于95，其余为锡；中等比率的铅/锡焊料，其铅含量的重量百分比小于40，其余为锡；高锡/低铅焊料，其锡含量的重量百分比大于95，其余为铅；无铅焊料，其锡含量的重量百分比大于95；以及它们的组合。
19.按照权利要求15所述的方法，其特征在于：打算腐蚀的那些金属是从由铬、铜、镍、以及它们的合金构成的组群中选出的。
20.按照权利要求15所述的方法，其特征在于：该硫酸盐化合物的浓度为0.2-0.5M。
21.按照权利要求15所述的电化学腐蚀剂，其特征在于：该甘油的浓度大约为1.4M，该硫酸盐的浓度大约为0.35M，而该磷酸盐的浓度大约为0.15M。
CNB011371978A 2000-10-26 2001-10-25 高锡焊料隆起的电化学腐蚀 Expired - Fee Related CN1184362C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/697333 2000-10-26
US09/697,333 US6468413B1 (en) 2000-10-26 2000-10-26 Electrochemical etch for high tin solder bumps

Publications (2)

Publication Number Publication Date
CN1354285A true CN1354285A (zh) 2002-06-19
CN1184362C CN1184362C (zh) 2005-01-12

Family

ID=24800725

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011371978A Expired - Fee Related CN1184362C (zh) 2000-10-26 2001-10-25 高锡焊料隆起的电化学腐蚀

Country Status (5)

Country Link
US (1) US6468413B1 (zh)
JP (1) JP3368271B2 (zh)
CN (1) CN1184362C (zh)
SG (1) SG94868A1 (zh)
TW (1) TW555886B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110310939A (zh) * 2018-03-27 2019-10-08 矽品精密工业股份有限公司 基板结构及其制法及导电凸块

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876052B1 (en) * 2000-05-12 2005-04-05 National Semiconductor Corporation Package-ready light-sensitive integrated circuit and method for its preparation
JP4293500B2 (ja) * 2001-05-07 2009-07-08 第一電子工業株式会社 電子部品の製造方法
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
US6900142B2 (en) * 2003-07-30 2005-05-31 International Business Machines Corporation Inhibition of tin oxide formation in lead free interconnect formation
US20060021974A1 (en) * 2004-01-29 2006-02-02 Applied Materials, Inc. Method and composition for polishing a substrate
US6995084B2 (en) * 2004-03-17 2006-02-07 International Business Machines Corporation Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
CN111621787B (zh) * 2020-04-27 2022-07-12 江苏富乐华半导体科技股份有限公司 一种蚀刻液体系及一种氮化铝基板的刻蚀方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3134054A1 (de) * 1981-08-28 1983-05-05 Hoechst Ag, 6230 Frankfurt Elektrochemisches entwicklungsverfahren fuer reproduktionsschichten
US5318677A (en) * 1991-02-13 1994-06-07 Future Automation, Inc. Process and solutions for removing resin bleed from electronic components
US5462638A (en) 1994-06-15 1995-10-31 International Business Machines Corporation Selective etching of TiW for C4 fabrication
US5486282A (en) 1994-11-30 1996-01-23 Ibm Corporation Electroetching process for seed layer removal in electrochemical fabrication of wafers
US5800726A (en) 1995-07-26 1998-09-01 International Business Machines Corporation Selective chemical etching in microelectronics fabrication
US6015505A (en) 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110310939A (zh) * 2018-03-27 2019-10-08 矽品精密工业股份有限公司 基板结构及其制法及导电凸块

Also Published As

Publication number Publication date
JP2002180299A (ja) 2002-06-26
US6468413B1 (en) 2002-10-22
TW555886B (en) 2003-10-01
CN1184362C (zh) 2005-01-12
JP3368271B2 (ja) 2003-01-20
SG94868A1 (en) 2003-03-18

Similar Documents

Publication Publication Date Title
CN1261979C (zh) 下层块金属的阻挡层盖
US5503286A (en) Electroplated solder terminal
CN1186801C (zh) 在电镀的控制熔塌芯片连接焊料突头存在下改进的钛钨合金腐蚀方法
US3761309A (en) Ctor components into housings method of producing soft solderable contacts for installing semicondu
US6689639B2 (en) Method of making semiconductor device
US4087314A (en) Bonding pedestals for semiconductor devices
US6750133B2 (en) Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US5904859A (en) Flip chip metallization
US20130105329A1 (en) Method to form solder deposits and non-melting bump structures on substrates
US20010032787A1 (en) Method to plate C4 to copper stud
US20090218230A1 (en) Method of producing electronic component
KR20130135042A (ko) 커넥터 자리 간격에 대한 설계 방식 및 결과의 구조물
CN1184362C (zh) 高锡焊料隆起的电化学腐蚀
US5800726A (en) Selective chemical etching in microelectronics fabrication
US7425278B2 (en) Process of etching a titanium/tungsten surface and etchant used therein
US20080008900A1 (en) Ball Limiting Metallurgy, Interconnection Structure Including the Same, and Method of Forming an Interconnection Structure
CN100508147C (zh) 电镀方法和接触凸起装置
US20080119056A1 (en) Method for improved copper layer etching of wafers with c4 connection structures
JP3407839B2 (ja) 半導体装置のはんだバンプ形成方法
JPS6112047A (ja) 半導体装置の製造方法
Chyan et al. Mechanistic Investigation and Prevention of Al Bond Pad Corrosion in Cu Wire-bonded Device Assembly
US6900142B2 (en) Inhibition of tin oxide formation in lead free interconnect formation
Liu Development of a Cost‐effective and Flexible Bumping Method for Flip‐chip Interconnections
CN1103119C (zh) 用于单掩膜c4焊料凸点制造的方法
CN116666334B (zh) 一种芯片封装结构及其制作方法、电子设备

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170308

Address after: American California

Patentee after: Ultratech Corporation

Address before: American New York

Patentee before: International Business Machines Corp.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050112

Termination date: 20171025