CN1340858A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1340858A
CN1340858A CN01125838A CN01125838A CN1340858A CN 1340858 A CN1340858 A CN 1340858A CN 01125838 A CN01125838 A CN 01125838A CN 01125838 A CN01125838 A CN 01125838A CN 1340858 A CN1340858 A CN 1340858A
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amplifier
unit amplifier
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power line
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CN1227733C (zh
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瀧川久美子
田中聪
香山聪
斋藤祐一
林範雄
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Hitachi Ltd
Hitachi Solutions Technology Ltd
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Hitachi ULSI Systems Co Ltd
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Abstract

为了减少双频带收发用半导体集成电路上内装的差动低噪音放大器中每个发射极引线焊接、封装的阻抗成分并提高增益,所以将差动放大器成对的放大器的接地脚作成彼此相邻。并且,将相同放大器的输入脚和接地脚作成彼此相邻。因此,使相邻的管脚信号成为反相,利用管脚间的变压器耦合,降低每个晶体管发射极阻抗。

Description

半导体器件
技术领域
本发明涉及一种主要用于无线通信的收发两用半导体器件。
发明背景
图5表示应用内装差动低噪音放大器的双频带无线收发用半导体集成电路(以下，称为收发信IC)的终端设备的构成例。
收发信IC501是组合双频带高频部分电路和频率变换电路，并内装于一个芯片上的集成电路。该IC与后级的基带IC515连接。基带IC对信号进行A/D、D/A变换，并且进行数字信号处理。收发信IC501的收发信部分由低频带差动低噪音放大器502a、低频带接收混频器503a、和高频带差动低噪音放大器502b、高频带接收混频器503b、低通滤波器504、可变增益放大器505、调制器507、以及调整偏差PLL508构成。并且，由高频合成器509和外带的本机振荡器510、驱动器511供给频率变换需要的高频本振信号。同样，由低频合成器512、本机振荡器513、驱动器514供给低频本振信号。通过将低噪音放大器作成差动结构，就不需要使用外带构件变压器进行的单差动变换。因此，可以减少外带构件的个数。
差动低噪音放大器由具有相同结构的两个单元放大器构成，输入相位反相的2个高频信号并进行差动放大。
内装差动低噪音放大器的收发信IC的一个例子，有Infinon公司发表于ISSCC2000，pp.144～145和451中的“A RF Transceiver forDigital Wireless Communication in a 25GHz Si Bipolar Technology”。按照论文是对DECT(Digital Enhanced CordlessTelecommunication)的收发信IC。接收系统的低噪音放大器为差动结构，但是信号线和地线、管脚配置都不清楚。并且，使用的封装为TSSOP38脚。
作为只使差动放大器IC化的代表例，有Philip(菲利普)公司的卫星电视接收机的IF频带增益控制放大器、TDA8011T(参照DATA SHEET，February，1995)。图7中示出管脚配置和电路框图。电路为差动结构，由封装管脚IFI1和IFI2输入，而从IFO1和IFO2输出。接地脚为1脚。作为另一个例子，有NEC(日电气)公司的1.6GHz频段差动型宽带放大器、μPC2726T。图8中示出管脚配置和电路图。就是从in1发in2输入，从out1和out2示出的集成电路。
但是，各个差动放大器的单元放大器中具有接地脚的差动放大器，除上述公司以外再也找不到其他IC厂商。
发明内容
本发明的目的在于改善低噪音放大器等差动结构的放大器增益。
以下，叙述造成图6中高频放大器增益降低的因素。图6是表示将IC装入封装时的放大器互导Gm的等效电路。晶体管601是放大器本身的晶体管。高频信号从602的基极输入。并且，通过给予适当的偏压使集电极电流ic流动。晶体管601的发射极上加上由焊线和管脚引起的阻抗Ze。由于该阻抗，如图6中的式601所示，整个放大器的Gm比晶体管601具有的互导gm要低。因为如果需要高增益的放大器，就进一步允许增加管脚，而且并联连接Ze。因此，可能降低焊线和管脚的电感成分。
                                           表1
表1表示具有2条与单元放大器电源线连接的引线脚(以下称为接地脚)时的封装脚配置、这时的等效电路、及电感成分。表的上部是相邻配置图1a中记载的第1单元放大器101的电感情况。用具体电路说明以后在实施例叙述，而放大器的输入脚IN1和接地脚G1、G2都是第1单元放大器101的管脚。IN2、G3、G4是与单元放大器101成对的第2单元放大器106的管脚。L表示由焊线和管脚引起的电感。因为IC管脚间距极窄，管脚之间存在变压器偶合，并将其以互感M表示。对于这样的管脚配置，相邻接地脚的电压是相同的。因而，由表可知，即使规定2脚接地，电感成分也不可能为一半。一般地说，与单脚比较约为70％。
接着，叙述单元放大器接地为1脚结构的情况。图1b示出其电路。这就是图1a的单元放大器101和106的接地脚只有G1和G3。在图1b中，第1单元放大器101的晶体管102基极上输入正电压时增加集电极电流，并在负载电阻105上降压。因此，集电极电压减少，输入信号于输出信号为反相关系。第2单元放大器106也同样，但是输入信号反相，因而101与106的电路工作变成反相。
                                                  表2
Figure A0112583800081
表2中表示单元放大器的接地脚为一条时的封装管脚配置和此时的晶体管发射极阻抗。表的上部是相邻图1b中记载的第1单元放大器101的接地脚G1和第2单元放大器106的输入脚IN2的情况。这时，管脚互相变成同相，因此，晶体管的发射极阻抗增大，整个放大器的Gm减少并使增益降低。
按照本发明的一个方面，为了提高增益，在有2条连接单元放大器电源线的引线脚(以下，称为接地脚)的差动放大器中，第1单元放大器的接地脚作成与第2单元放大器的接地脚分别一对一邻接的配置。表1的下部是本发明一个实施例的管脚配置例。这时，因差动信号使相邻管脚电压成为反相。由表中的等效电路可知，总电感变成焊线和管脚电感的一半以下。
按照本发明的另一个方面，为了提高增益，单元放大器的接地脚为1条管脚时，将接地脚作成与输入线连接的引线脚(以下，称为输入脚)互相邻接配置。
表2下部是本发明一个实施例的管脚配置例。从比较表的上下两行的阻抗可知，相同放大器的输入脚若与接地脚相邻，由于信号为反相，因而每个晶体管发射极阻抗都小。
附图说明
图1a和图1b是本发明实施例的电路图。
图2表示封装的管脚间的耦合状态图。
图3是本发明一个实施例的双频带收发信IC封装的组装例。
图4是本发明一个实施例的差动放大器IC封装的组装例。
图5是双频带无线收发信用半导体集成电路的结构。
图6表示放大器互导的等效电路。
图7是菲利普公司的TDA8011T管脚配置。
图8是NEC公司的μPC2726T管脚配置。
实施例的说明
以下，图1a和图1b表示本发明实施例的电路图。各图的100是应用于图5的收发信IC501的电路。具体地说，图1a的100相当于图5的高频带低噪音放大器502b，图1b的100相当于图5的低频带低噪音放大器502a。
图1a中，第1单元放大器101由晶体管102、偏压电阻103、和负载电阻105构成。并且，具有给放大器101加偏压的偏压电流供给电路104。封装管脚是高频信号输入脚IN1和从发射极来的2条接地脚G1、G2。与放大器101成对的第2单元放大器106也是同样结构，由晶体管107、偏压电阻108和负载电阻110构成。并且在与104相同的电路结构中也设有偏压电流供给电路109。管脚也同样有输入脚IN2、接地脚G3、G4。电源和接地脚是放大器的电源Vcc与偏压电路的电源BVcc、及偏置电路的接地BGND。单元放大器的接地脚即使一条差动放大器，除管脚数减少外，电路结构都相同。
接着，以下表示放大器的工作。首先，从天线输入高频信号。带通滤波器112去除频带外不要信号，变换成差动信号。低噪音放大器的匹配电路113、114采用阻抗匹配，经由管脚IN1、IN2向IC内部的差动低噪音放大器输送差动信号。偏压电路104、109对温度、电流电源变动生成稳定的偏压电流，并决定晶体管102、107的工作点。偏压电流量对2个电路也相同。偏置电阻103、108把上述偏压电流变换成电压。因此，向晶体管102、107供给适当的偏置电压，流过直流集电极电流决定晶体管的工作点。因此，各个晶体管进行差动信号的放大工作。放大后的高频信号由负载电阻105、110转换为电压，并送向后级的接收混合器115。
在这样构成的差动低噪音放大器中，进行示于表1下部的管脚配置。就是，第1单元放大器101的接地脚作成与第2单元放大器106的接地脚分别一对一相邻的配置。因此，总电感变成焊线和管脚电感的一半以下。其结果，如式601所示，电路的互感Gm上升，增益提高。表3
Figure A0112583800101
表3中的No.1和No.2表示表1所示接地脚配置的电路特性分析结果。表3的No.3是No.2的变形例。表3的No.2和No.3为本发明
实施例的管脚配置例。
接着，说明图1b。电路除接地脚变成一个管脚以外都与图1a相同，因而省略工作的说明。对这这种电路，则进行表2下部示出的管脚配置。就是，将接地脚作成与输入脚互相邻接的配置。因此，放大器的每个晶体管发射极阻抗减少，其结果，改善了电路的互导并提高增益。表4
Figure A0112583800111
表4的No.2是本发明一个实施例的管脚配置。
表3、4中示出的电路分析，使用了高频模拟HSPICE。对分析的放大器，采用了0.35μm工艺的双极晶体管。并且，在电源电压2.8V下向晶体管102、107流入6ma直流电流进行工作。图2表示封装一部分的管脚间的耦合状态。201表示封装的一部分。202表示封装的管脚。K为决定互导量的耦合系数。互导规定从某一个管脚到三个最先管脚的作用，按照其距离使耦合系数变化为0.4、0.27、0.2、0.13。耦合系数假定相当于QFP(Quadrature Flat Package：正方形扁平封装)56脚的。表3中，根据本实施例，表示增益提高1.5dB～1.7dB。对表4也同样提高增益1.1dB。
为了降低电感成分，理想的是放大器布局在从放大器晶体管的发射极管脚最顶端到焊盘的距离为最短的位置处设置低噪音放大器的电路。图3表示其一例。图3是以图5中叙述过的双频带收发信IC为例。301是应用本发明的收发信IC芯片。302是密封收发信IC的QFP56脚。303是封装芯片的粘合面，304是封装的支承材料。305是应用本发明的高频带差动低噪音放大器502b布局的场所。并且，315是对低频带差动低噪音放大器502a进行布局的场所。
306、310是图1A的晶体管102接地脚；307、311是晶体管107的接地脚；308、309分别是差动低噪音放大器101和106的输入脚。312是高频带低噪音放大器502b的电源脚。
对低频带低噪音放大器502a也同样，317是图1B的晶体管102接地脚；320是晶体管107的接地脚；318、319分别是差动低噪音放大器101和106的输入脚。316是低频带低噪音放大器502a的电源脚。321是偏压电路的电源脚；322是偏压电路的接地脚。偏压电路的管脚为低频低噪音放大器和高频低噪音放大器共用。323是从芯片上的各焊盘焊到上述所示的引线脚的焊线。
如图3所示，放大器被配置于芯片端面的中央附近并进行压焊。如此，焊盘与管脚间的焊线就会缩短。在本实施例中，由于假定双频带，所以应用本发明的放大器的管脚从中央到下端进行分配。但是，接地脚306和307分配给中央部分的管脚。因此，电感成分比起把放大器配置到芯片角落来要降低。
至此，已叙述了具有放大器的LSI，但是本发明也能应用于仅由放大器构成的IC。图4中示出这时的例子。401是本发明一个实施例的差动放大器IC芯片。402是密封差动放大器IC的封装TSSOP12脚。403是封装芯片的粘合面；404是封装支承材料。405、409是晶体管102的接地脚；406、410是晶体管107的接地脚；407、408是差动放大器101和106的输入脚。411是偏压电路的电源脚；412是偏压电路的接地脚；413、414是差动放大器的输出脚，415是差动放大器的电源脚。416是从芯片上各焊盘焊到上述示出的引线脚的焊线。
如图那样对封装中央配置线对称的管脚，则从放大器晶体管的发射极管脚顶端到焊盘的距离就变成最短。并且，使低噪音差动放大器成为也包括封装电学影响完全对称的电路。因而，可以预期IC差动性特性更好。
虽然图3、4依照表3的No.2中示出的管脚配置，但是依照表3No.3中示出的管脚配置也可以。
另外，实施例把低噪音放大器作为例子进行说明，但是本发明是关系到放大器的接地脚配置。因此，也可以应用于如图1A所示的差动结构通用型放大器。
根据本发明的实施例，对于差动放大器，在具有2个单元放大器的差动放大器中，将第1单元放大器的接地脚作成分别与第2单元放大器的接地脚一对一邻接的配置。因此，使每个晶体管的发射极电感变成为单个接地脚的一半以下。其结果，可使每个晶体管发射极降低阻抗，提高放大器增益。并且，当单元放大器具有一条接地脚时，可将接地脚与输入脚互相邻接配置。
并且，当应用于象收发信IC这样的大规模IC时，通过把低噪音放大器的电路设置于从放大器晶体管的发射极脚顶端到焊盘的距离变成最短位置的布局和使之组合，可以实现更低电感。
而且，对只有差动放大器的IC，通过加上本发明以下的二点，就可以作成提高增益，也包括封装影响的对称差动放大器。第一点，把低噪音放大器的电路设置于从放大器晶体管的发射极脚顶端到焊盘的距离变成最短的位置，第二点，对于封装作成对称的管脚配置。

Claims (15)

1、一种半导体器件，具有半导体电路芯片、与该半导体电路芯片连接的多个引线脚、及密封该半导体电路芯片的封装，上述半导体电路芯片上形成2个单元放大器，该2个单元放大器形成1个差动放大器；
该2个单元放大器的第1单元放大器的第1电源线与上述多条引线脚的至少2条连接；
该2个单元放大器的第2单元放大器的第1电源线与上述多条引线脚的至少2条连接；以及
与上述第1单元放大器的第1电源线连接的各个引线脚作成为与上述第2单元放大器的第1电源线连接的各个引线脚一对一邻接配置。
2、一种半导体器件，具有具有差动放大器的半导体电路芯片、与该半导体电路芯片连接的多条引线脚、及密封上述半导体电路芯片的封装；
上述差动放大器具有成对的2个单元放大器，各单元放大器的第1电源线与上述引线脚的1条连接；以及
与上述2个单元放大器的第1电源线连接的管脚是与单元放大器输入线连接的引线脚互相邻接配置。
3、根据权利要求1或2所述的半导体器件，其特征是离上述封装的一边中央线对称地配置有与上述2个单元放大器的第1电源线连接的管脚和输入脚。
4、根据权利要求1到3任一项所述的半导体器件，其特征是上述2个单元放大器配置在从连接于该2个单元放大器的第1电源线的焊盘到突出于上述封装外部的管脚顶端的距离变成最短的芯片上位置。
5、根据权利要求1到4任一项所述的半导体器件，其特征是上述2个单元放大器的各单元放大器具有与上述第1电源线连接的晶体管、第2电源线、及负载；以及
上述负载连接于上述晶体管与上述第2电源线之间。
6、根据权利要求5所述的半导体器件，其特征是上述2个单元放大器的上述第2电源线连接在共用的1条引线脚上。
7、一种无线收发信用的半导体器件，
具有设置于将天线来的接收信号和本机振荡器来的信号进行混频的接收混频器与上述天线之间的差动低噪音放大器，和与该差动低噪音放大器连接的多条引线脚；
该差动低噪音放大器具有输入互相相位反相信号的2个单元放大器；以及
上述2个单元放大器的第1电源线与互相不同的引线脚连接。
8、根据权利要求7上述的无线收发用的半导体器件，其特征是与上述2个单元放大器的第1电源线连接的引线脚互相邻接。
9、根据权利要求7上述的无线收发用的半导体器件，其特征是与上述2个单元放大器的第1电源线连接的引线脚和与单元放大器的输入线连接的引线脚互相邻接。
10、根据权利要求7上述的无线收发用的半导体器件，其特征是上述2个单元放大器的第1电源线分别与多条引线脚连接。
11、根据权利要求10上述的半导体器件，其特征是与上述2个单元放大器的一方单元放大器的第1电源线连接的多条引线脚分别作成与另一方单元放大器的第1电源线连接的多条引线脚一对一邻接配置。
12、根据权利要求7到11任一项所述的半导体器件，其特征是离上述封装的一边中央线对称地配置有与上述2个单元放大器的第1电源线连接的管脚和输入脚。
13、根据权利要求7到12任一项所述的半导体器件，其特征是上述2个单元放大器配置在从连接于该2个单元放大器的第1电源线的焊盘到突出于上述封装外部的管脚顶端的距离变成最短的芯片上的位置。
14、根据权利要求7到13任一项所述的半导体器件，其特征是上述2个单元放大器的各单元放大器具有与上述第1电源线连接的晶体管、第2电源线和负载；以及
上述负载连接于上述晶体管与上述第2电源线之间。
15、根据权利要求14所述的半导体器件，其特征是上述2个单元放大器的上述第2电源线连接在共用的1条引线脚上。
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