CN1333944A - 栅极偏置结构 - Google Patents

栅极偏置结构 Download PDF

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Publication number
CN1333944A
CN1333944A CN99815824A CN99815824A CN1333944A CN 1333944 A CN1333944 A CN 1333944A CN 99815824 A CN99815824 A CN 99815824A CN 99815824 A CN99815824 A CN 99815824A CN 1333944 A CN1333944 A CN 1333944A
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transistor
grid
ldmos transistor
biasing
power
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CN1196252C (zh
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P·艾利松
N·阿菲肯斯塔姆
J·约翰松
H·舍登
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Ke Rui
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Telefonaktiebolaget LM Ericsson AB
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14Modifications for compensating variations of physical values, e.g. of temperature
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/18Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

为了消除功率晶体管(1)的静态电流的温度依赖性,借助于和功率晶体管在同一个硅芯片上的偏置晶体管的输出电压控制功率晶体管的栅极偏压,并且使偏置晶体管的栅极和漏极互连,并由外部电路对其提供恒定电流(IB)。

Description

栅极偏置结构
技术领域
本发明一般涉及LDMOS(横向扩散的金属氧化物半导体)晶体管,尤其涉及用于进行静止电流的温度补偿的RF功率LDMOS场效应晶体管的栅极偏置结构。
发明背景
图1A说明对RF功率LDMOS场效应晶体管1的栅极G加一偏置栅极电压VG,从而产生所需的晶体管1的静态电流IDQ的常规方式。RF信号通过端子2被提供给栅极G。
为了使晶体管1的栅极G偏置,固定的电阻R1被连接在栅极G和源极S之间,源极一般和地相连,并且可变电阻R2被连接在栅极G和正电压的端子之间。借助于电阻R2,把栅极电压VG调节到一个产生所需的通过晶体管1的静态电流IDQ的值。
静态电流IDQ的值一般被这样选择,使得对于输出功率特性产生一个平的增益。离开所选的IDQ的任何偏移都将使晶体管的线性性能变差。
对于一个给定的栅极电压VG,静态电流IDQ和温度有关。因而,温度改变将引起晶体管1的性能的变差。
晶体管的静态电流的温度系数是栅极偏压的函数。正常使用的相对低的栅极偏移电压VG产生正的温度系数,即静态电流IDQ随温度而增加。
用于减少静态电流IDQ随温度而改变的通常的方法是引入和电阻R1串联的分立的二极管D1,如图1B所示。在二极管两端的电压降随温度的增加而减少,因而部分地消除RF晶体管的静态电流对温度的依赖性。
然而,使用二极管作为温度补偿有两个明显的缺点。首先,二极管的温度特性不精确地跟踪RF LDMOS晶体管的温度特性。第二,在分立的二极管和晶体管之间,不能实现好的热耦合,因而,两个元件的温度是不同的。
发明内容
本发明的目的在于消除功率晶体管的静态电流的温度依赖性。
这可以这样来实现:借助于和功率晶体管在同一个硅芯片上的偏置晶体管的输出电压控制功率晶体管的栅极偏压,并且使偏置晶体管的栅极和漏极互连,并由外部电路对其提供恒定电流。
因为偏置晶体管的栅极和漏极相互连接,所以偏置晶体管的栅极电压将自动地调节以便维持强制的漏极电流。由于偏置晶体管的固有的温度依赖性,栅极偏压将随温度增加而减少。因而,功率晶体管的栅极偏压将随温度增加而减少,从而得到恒定的静态电流IDQ。
本发明也可以用于栅极偏压较高,因而具有负的静态电流温度系数的情况。
附图简述
下面结合附图更详细地说明本发明,其中图2和图3分别说明按照本发明的栅极偏置结构的第一和第二实施例。
详细描述
在图2和图3中,和图1A,1B相同的电路元件用相同的标号表示。
在图2中,说明了用于RF功率LDMOS晶体管1的按照本发明的第一栅极偏置结构,其中的晶体管和图1A,1B所示的相同。
如图1A,1B那样,RF信号通过图2的端子2提供给功率晶体管1的栅极G。
按照本发明的栅极偏置结构包括偏置LDMOS场效应晶体管3,其具有互连的栅极G3和漏极D3,所述互连的栅极G3和漏极D3通过电感L和功率晶体管的栅极G相连,并且其源极S3和功率晶体管1的源极S相连。
按照本发明,偏置晶体管3的互连的栅极G3和漏极D3被提供给恒定的偏置直流电流。
在图2中,这个恒定的偏流IB由外部电路(未示出)通过RF信号输入端2和输入的RF信号一道被提供。电感L用于隔离输入的RF信号和偏置晶体管3。
来自偏置晶体管3的输出电压用于控制功率晶体管1的栅极偏压VG。
来自偏置晶体管3的输出电压将随温度的增加而减少,这是因为输入的偏流IB是固定的。因而,功率晶体管1的栅极偏压VG也随温度的增加而减少,从而保持静态电流IDQ恒定。
因而,将消除功率晶体管1的静态电流IDQ对温度的依赖性。
电流值比IDQ/IB是在功率晶体管1和偏置晶体管3之间的尺寸差的函数。
按照本发明的一个实施例,偏置晶体管3和功率晶体管1位于同一个硅片(未示出)上,从而使温度跟踪最佳,并且偏置晶体管3比功率晶体管1小得多,例如小100倍以上。
应当指出,所述电流比不精确地等于晶体管尺寸的比,这是因为偏置晶体管3的漏极对源极的电压比功率晶体管的该电压比低得多。
图2中的用于隔离偏置晶体管3和RF信号的电感L可以和晶体管2、3集成在一个芯片上,但是也可以是位于芯片外部的分立元件。
图3说明按照本发明的栅极偏置结构的第二实施例。
图3的实施例几乎和图2的实施例相同,其中偏置晶体管3具有互连的栅极G3和漏极D3,它们通过RF信号隔离装置和功率LDMOS晶体管1的栅极G相连,所述隔离装置在本实施例中是高阻抗元件Z,可以由电阻或者电感实现。为了便于和晶体管集成,可以选择电阻。
不过,在图3的实施例中,偏置晶体管3的互连的栅极G3和漏极D3不通过功率晶体管1的RF信号输入端2被供给恒定的偏流IB。而是互连的栅极G3和漏极D3直接由外部电流源(未示出)提供恒定的偏流IB。
由上述可见,显然,功率晶体管的静态电流的温度依赖性可以被消除,其中借助于和功率晶体管在同一个硅芯片上的偏置晶体管的输出电压控制功率晶体管的栅极偏压,并且使偏置晶体管的栅极和漏极互连,并由外部电路对其提供恒定电流。

Claims (5)

1.一种用于RF功率LDMOS晶体管(1)的栅极偏置结构,用于温度补偿其静态电流(IDQ),其特征在于,偏置LDMOS晶体管(3)具有互连的栅极(G3)和漏极(D3),并通过RF隔离元件(L,R)使所述互连的栅极和漏极和功率LDMOS晶体管(1)的栅极(G)相连,并使其源极(S3)和功率LDMOS晶体管(1)的源极(S)相连,偏置LDMOS晶体管(3)的互连的栅极和漏极适用于被供给恒定偏流(IB),借以使静态电流(IDQ)和温度的变化无关。
2.如权利要求1所述的结构,其中功率LDMOS晶体管位于一个硅片上,其特征在于,偏置LDMOS晶体管(3)和功率LDMOS晶体管(1)位于同一个硅片上,并且偏置LDMOS晶体管(3)比功率LDMOS晶体管(1)小。
3.如权利要求2所述的结构,其特征在于,偏置LDMOS晶体管(3)比功率LDMOS晶体管(1)小100倍以上。
4.如权利要求1-3任何一个所述的结构,其特征在于,偏置LDMOS晶体管(3)的互连的栅极和漏极适用于通过所述RF隔离装置被供给所述恒定的偏流(IB),并且所述RF隔离装置是电感(L)。
5.如权利要求1-3任何一个所述的结构,其特征在于,偏置LDMOS晶体管(3)的互连的栅极和漏极适用于直接地被供给所述恒定的偏流(IB),并且所述RF隔离装置是具有高阻值的电阻(R)。
CNB998158240A 1999-01-25 1999-12-30 栅极偏置结构 Expired - Lifetime CN1196252C (zh)

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EP (1) EP1153475B1 (zh)
JP (1) JP2002535907A (zh)
KR (1) KR100580748B1 (zh)
CN (1) CN1196252C (zh)
AU (1) AU2334900A (zh)
CA (1) CA2359679A1 (zh)
DE (1) DE69934828T2 (zh)
SE (1) SE516012C2 (zh)
TW (1) TW427026B (zh)
WO (1) WO2000044089A1 (zh)

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CN100397282C (zh) * 2002-04-30 2008-06-25 快捷半导体有限公司 用于有过程差异补偿的有源偏置电路的电流断开电路

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KR100580748B1 (ko) 2006-05-15
EP1153475B1 (en) 2007-01-10
CA2359679A1 (en) 2000-07-27
SE9900210L (sv) 2000-07-26
EP1153475A1 (en) 2001-11-14
TW427026B (en) 2001-03-21
SE516012C2 (sv) 2001-11-05
CN1196252C (zh) 2005-04-06
WO2000044089A1 (en) 2000-07-27
US6288596B1 (en) 2001-09-11
DE69934828T2 (de) 2007-08-16
JP2002535907A (ja) 2002-10-22
AU2334900A (en) 2000-08-07
SE9900210D0 (sv) 1999-01-25
DE69934828D1 (de) 2007-02-22
KR20010108087A (ko) 2001-12-07

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