CN1316861C - Multi-layer circuit board and mfg. method - Google Patents
Multi-layer circuit board and mfg. method Download PDFInfo
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- CN1316861C CN1316861C CNB2004100307162A CN200410030716A CN1316861C CN 1316861 C CN1316861 C CN 1316861C CN B2004100307162 A CNB2004100307162 A CN B2004100307162A CN 200410030716 A CN200410030716 A CN 200410030716A CN 1316861 C CN1316861 C CN 1316861C
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Abstract
The present invention relates to a multilayer circuit board and a manufacturing method thereof, which mainly provides a plurality of circuit board units with patterning circuit layers. An insulating layer is formed on the surface of the circuit board units; then patterning process is carried out so as to form a plurality of openings on the insulating layer or to thin the insulating layer to expose the circuit layers needing jointing in the circuit board unit; finally, processes of surface activation and jointing are carried out to the circuit board units in a vacuum state so that the circuit layers exposed at the openings of the insulating layer are electrically connected mutually to form the multilayer circuit board. The present invention simplifies process steps, shortens process time and reduces cost. The multilayer circuit board and the manufacturing method thereof of the present invention can enhance process fineness rate and wiring flexibility. In the situation of normal temperature, the process of pressing the multilayer circuit board can be carried out to avoid generating improper thermal stress and warpage. The multilayer circuit board is light and thin, and is suitable for a small electronic component.
Description
Technical field
The invention relates to a kind of multilayer circuit board and method for making thereof, particularly about a kind of multilayer circuit board that semiconductor chip carrying and encapsulation are provided and preparation method thereof.
Background technology
Flourish along with electronic industry, electronic product also develops towards multi-functional, high performance direction gradually.For satisfying the package requirements of semiconductor package part height integrated (Integration) and microminiaturized (Miniaturization), the circuit board (Circuit board) that provides a plurality of main passive components and circuit to carry to connect, also develop into multi-layer sheet (Multi-layer board) by doubling plate gradually, under limited space, interconnection technique (Interlayer connection) by interlayer enlarges available circuit area on the circuit board, thereby cooperates the demand of highdensity integrated circuit (Integrated circuit).
The manufacture method of tradition multilayer circuit board generally is by pressing method (Laminating press) and Layer increasing method (Build-up) dual mode.
The existing processing procedure that utilizes the pressing mode to make multilayer circuit board mainly is, preparation is as Copper Foil and the made a plurality of circuit boards of insulating substrate, this circuit board is formed with upper and lower circuit layer and conductive through hole, between these circuit boards, press from both sides and establish by fiber or thermosetting resin etc. (as epoxy resin, phenolic resins etc.) the preimpregnation material of making (Prepreg) is as adhesion coating (Adhesive layer), through lamination (Laminating) and hot pressing (Heat press) step, to hand over mutually stacked circuit board to be pressed into multi-layer sheet, afterwards, use drilling technique (Drilling) again, be drilled with a plurality of through holes that run through, and run through plating conductive metal layer on the hole wall surface of through hole at this, make respectively can electrically connect mutually by this through hole between this circuit board, to finish the making of multilayer circuit board.
Shown in Figure 1A to Fig. 1 F, in Japanese technical journal (JMS), be that another utilizes the pressing mode to form the manufacturing method thereof of multilayer circuit board.At first, the thermoplastic insulation's plate 12 (shown in Figure 1A) that provides a plurality of surfaces to have Copper Foil 11, and utilize patterning process on the surface of this Copper Foil 11, form the circuit layer 13 (shown in Figure 1B) of patterning, then, a side that does not have patterned circuit layer 13 in this thermoplastic insulation's plate 12 forms a plurality of openings 14, expose outside the partially patterned circuit layer 13 (shown in Fig. 1 C) that need be electrically conducted, filling electric conducting material in the opening 14 of this thermoplastic insulation's plate 12 again, as (shown in Fig. 1 D) such as tin cream or silver paste 15, then, a plurality of thermoplastic insulation's plates 12 that are filled with tin cream or silver paste 15 are at high temperature carried out pressing (shown in Fig. 1 E), while dissolves by opening 14 interior tin cream or the silver paste 15 that high temperature action will be filled in this thermoplastic insulation's plate 12, so that being electrically conducted and the joint (shown in Fig. 1 F) of each thermoplastic insulation's plate 12 of 12 adjacent circuit layers 13 of this thermoplastic insulation's plate to be provided, form multilayer circuit board.
But it is existing with in the pressing manufactured multilayer circuit board processing procedure, because of wherein being formed with a plurality of conductive through holes that run through this multilayer circuit board, cause the configuration flexibility of this circuit board to diminish, though can utilize in insulation board electric conducting material such as filling tin cream or silver paste so that the electrical joint of adjacent circuit interlayer to be provided, but need additionally provide these electric conducting materials, cause the increase of process complexity and cost, moreover, anyway, this pressure programming is at high temperature to carry out, yet thermal coefficient of expansion (CTE) is different each other between this circuit board and insulating layer material, therefore will produce thermal stress and warpage issues in the pressing process, has a strong impact on its processing procedure acceptance rate.
Be to make multiple-plate method shown in Fig. 2 A to Fig. 2 E to increase a layer mode (Build-up).Shown in Fig. 2 A, at first, preparation core substrate 21, this core substrate 21 is by the resin sandwich layer 211 with predetermined thickness and is formed at these sandwich layer 211 lip-deep circuit layers 212 and constitutes, simultaneously, in this resin sandwich layer 211, be formed with a plurality of plating vias 213, electrically connect the circuit layer 212 on these resin sandwich layer 211 surfaces whereby.Shown in Fig. 2 B, this core substrate 21 is implemented to increase a layer processing procedure, to lay insulating barrier 22, offer a plurality of blind holes 23 that are communicated to this circuit layer 212 on this insulating barrier 22 on these core substrate 21 surfaces.Shown in Fig. 2 C, these insulating barrier 22 exposed surfaces (comprising the blind hole hole wall) form metal conductive film 24 in modes such as electroless plating or sputters, and on this metal conductive film 24, form patterning plating resistance layer 25, make this plating resistance layer 25 be formed with a plurality of opening 250 to expose outside the partially conductive film that will form patterned circuit layer.Shown in Fig. 2 D, utilize plating mode in this plating resistance layer opening, to form patterned circuit layer 26 and conductive blind hole 23a, and this circuit layer 26 can be electrically conducted to this circuit layer 212 by this conductive blind hole 23a, the etching partially conductive film 24 that removes this plating resistance layer 25 and covered then is to form layer reinforced structure 20a.Shown in Fig. 2 E, similarly, on this first layer reinforced structure 20a outermost surface, also use same procedure to repeat to form the second layer reinforced structure 20b, progressively to increase a layer formation multilayer circuit board 20.
Yet in above-mentioned processing procedure, formation increase layer circuit must be from the inside to the outside successively storehouse just can finish, in increasing floor processing procedure if there is a certain layer line road to go wrong, the discarded of integral multi-layered circuit board will be caused, have a strong impact on its processing procedure acceptance rate, therefore, by existing fabrication steps that layer mode make multilayer circuit board not only flow process complexity, the manufacturing cost height of increasing, and the investment of its process apparatus is expensive especially, and the processing procedure time (Cycle time) is tediously long and be unfavorable for a large amount of productions.
Therefore, how effectively solve above-mentioned existing pressing and increase the existing problems of layer technology, a kind of processing procedure, cost descends and acceptance rate improves multilayer circuit plate structure and manufacture method thereof simplified is provided, become present urgency problem to be solved.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of configuration that can carry out each circuit board unit simultaneously, rejoins to form the multilayer circuit board and the method for making thereof of multilayer circuit plate structure.
Another object of the present invention is to provide a kind of each circuit board unit is detected after, rejoining forms the multilayer circuit plate structure, improves the multilayer circuit board and the method for making thereof of processing procedure acceptance rate.
A further object of the present invention is to provide a kind of multilayer circuit plate structure and method for making thereof of simplifying processing procedure, saving cost and improving acceptance rate.
Another purpose of the present invention is to provide a kind of multilayer circuit board and method for making thereof that improves the wiring flexibility.
Another object of the present invention is to provide a kind of and can under the normal temperature situation, carry out multilayer circuit board pressing processing procedure, avoid in the processing procedure multilayer circuit board and the method for making thereof that produce because of improper thermal stress and warpage issues.
It is a kind of frivolous and be applicable to multilayer circuit board and method for making thereof in the miniature electric assembly that another purpose of the present invention is to provide.
For reaching above-mentioned and other purpose, method for making multi-layer circuit board of the present invention comprises: a plurality of circuit board units with patterned circuit layer are provided; Form patterned insulation layer on these circuit board unit surfaces, make this insulating barrier form a plurality of openings, expose outside the circuit layer that will engage in this circuit board unit; And the surface active processing procedure that under vacuum state, carries out these circuit board units, the circuit layer that this circuit board unit respectively will be engaged electrically connects mutually, forms multilayer circuit board.
Method for making multi-layer circuit board of the present invention also can comprise: a plurality of circuit board units with patterned circuit layer are provided; Form insulating barrier on these circuit board unit surfaces, and this insulating barrier of thinning, expose outside the circuit layer that will engage in this circuit board unit; And the surface active and the connection process that under vacuum state, carry out these circuit board units, the circuit layer that this circuit board unit respectively need be engaged electrically connects mutually, forms multilayer circuit board.
In addition, for further improving the engaging force between these circuit board units, can be before the circuit board unit surface activates processing procedure, to the metal surface and the surface of insulating layer planarization of these circuit board units, and carry out clean program and remove its surperficial oxide layer, improve follow-up surface active process quality.In addition, after respectively this circuit board unit is finished joint, can toast, remove aqueous vapor and increase its bond strength.
Above-mentioned method for making prepared multilayer circuit board comprises according to the present invention: a plurality of circuit board units, respectively this circuit board unit interbody spacer has insulating barrier, and this insulating barrier is formed with opening, contact mat for adjacent circuit plate cell surface corresponding circuits layer is electrically conducted mutually, wherein, the surface that engages between these circuit board units is through the surface active processing procedure with effective joint together.
The multilayer circuit board that above-mentioned method for making makes according to the present invention also comprises: a plurality of circuit board units, respectively be separated with insulating barrier between this circuit board unit, and this insulating barrier through thinning to expose outside the contact mat of adjacent circuit plate cell surface corresponding circuits layer, be electrically conducted mutually by these contact mats for these circuit board units, wherein, the surface that engages between these circuit board units is through the surface active processing procedure with effective joint together.
In sum, multilayer circuit board of the present invention and method for making thereof simultaneously the combined circuit plate pressure programming and increase the advantage of layer processing procedure, at first carry out the configuration processing procedure of a plurality of circuit board units, improve the flexibility of wiring, and can be in advance this circuit board unit be respectively detected, to improve the successive process acceptance rate, effectively avoid the existing waste product problem that produces in layer processing procedure that increases, simultaneously, carrying out respectively this circuit board unit when engaging, be by electricity slurry (Plasma) under vacuum environment, reactive ion etching (Reactive ionic etching, RIE) or ionic metal electricity slurry (Ion metal plasma, IMP) mode such as processing procedure activates processing procedure on the surface of this circuit board unit, make the surface that needs between this circuit board unit to engage present the atom and the molecular structure of nano-scale, so that directly at the joint that carries out under the normal temperature vacuum between these circuit board units, effectively avoid in the existing pressure programming various storeroom thermal coefficient of expansions (CTE) different the thermal stress that produces and warpage issues and electric conducting material problem such as WU cream additionally is provided, have again, the joint that the present invention can carry out a plurality of circuit board units simultaneously has the circuit board of multilayer circuit layer with rapid formation, effectively save fabrication steps and cost, in addition, because of this circuit board unit can be pre-formed the patterned electricity line structure, and when engaging, directly utilize and be formed at its surperficial circuit layer and be electrically conducted mutually, therefore, need not additionally to form again conductive through hole, so can effectively improve its configuration flexibility.Moreover by the thickness of insulating layer between this circuit board unit of thinning in advance, the multilayer circuit board that follow-up joint will be finished has more frivolous thickness, to be applicable to small-sized electronic building brick.
Description of drawings
Figure 1A to Fig. 1 F has now to utilize the pressing mode to form the processing procedure schematic diagram of multilayer circuit board;
Fig. 2 A to Fig. 2 E is that existing the utilization increases the processing procedure schematic diagram that layer mode forms multilayer circuit board;
Fig. 3 A to Fig. 3 E is the generalized section of the embodiment 1 of method for making multi-layer circuit board of the present invention;
Fig. 4 A to Fig. 4 C is the generalized section of the embodiment 1 of circuit board unit;
Fig. 5 A and Fig. 5 B are the generalized sections that once engages a plurality of circuit board units among the embodiment 1 of method for making multi-layer circuit board of the present invention;
Fig. 6 A to Fig. 6 E is the generalized section of the embodiment 2 of method for making multi-layer circuit board of the present invention; And
Fig. 7 A and Fig. 7 B are the generalized sections that once engages a plurality of circuit board units among the embodiment 2 of method for making multi-layer circuit board of the present invention.
Embodiment
Embodiment 1
Fig. 3 A to Fig. 3 E is the generalized section of the embodiment 1 of method for making multi-layer circuit board of the present invention.
As shown in Figure 3A, at first, provide a plurality of circuit board units 31.The form of these circuit board units 31 can for example be any in individual layer, bilayer and the multilayer circuit board institute cohort group, it mainly comprises insulating barrier 310 and the patterned circuit layer 311 that is formed on this insulating barrier, and this patterned circuit layer 311 can electrically connect by a plurality of holes that electrically conduct that are formed in this insulating barrier 310.Wherein, the form of these circuit board units 31 is shown in Fig. 4 A, and it is circuit board unit 31 schematic diagrames with conductive through hole 312a, and this conductive through hole 312a that is used to electrically connect circuit layer 311 is filled with electric conducting material; Or shown in Fig. 4 B, it is another circuit board unit 31 schematic diagrames with conductive blind hole 312b, the opening of this conductive blind hole 312b extends in the insulating barrier 310, but do not penetrate the circuit layer 311 of insulating barrier one side, and can be filled with electric conducting material in the opening of this conductive blind hole 312b or not have packing material; Or shown in Fig. 4 C, it is to have plating via (Plated through hole, PTH) circuit board unit 31 schematic diagrames of 312c, it is behind insulating barrier 310 perforate hole walls and surface formation conductive metal layer, fill up the residual clearance of perforate again with conduction or non-conductive packing material, to guarantee to electroplate the reliability of via 312c.These circuit board units 31 of above-mentioned accompanying drawing only are used to illustrate applicable circuit board unit kind, and the electric connection mode of this circuit layer 311 is non-exceeds with above-mentioned, it is the simple and easy replacement of processing procedure, but not be used to limit application category of the present invention, the making of this circuit board unit 31 is prior aries in addition, so no longer explanation.
Shown in Fig. 3 B, be formed with insulating barrier 32 on these circuit board unit 31 surfaces, carry out patterning process so that this insulating barrier 32 forms a plurality of openings 320, expose outside the contact mat 311a part (shown in Fig. 3 C) of the circuit layer 311 that need engage.This insulating barrier 32 can for example be epoxy resin (Epoxyresin), polyimides (Polyimide), cyanate (Cyanate Ester), glass fibre (Glass fiber), bismaleimide-triazine resin (BT, BismaleimideTriazine) or blending epoxy and glass fibre materials such as (FR5) constitute, and this insulating barrier 32 is formed at least one side of this circuit board unit 31, then can utilize for example perforate technology to form a plurality of openings 320 in this insulating barrier 32.Then, can the planarization processing procedure such as for example polish to the surface (comprising circuit layer and surface of insulating layer) of these circuit board units 31, and can under suitable environment, (in vacuum environment, inert gas environment or chemical solution) carry out clean program, remove its surperficial oxide layer, follow-up surface active process quality is provided.
Shown in Fig. 3 D, these circuit board units 31 are placed under the vacuum state, by electricity slurry (Plasma), reactive ion etching (Reactive ionic etching, RIE) or ionic metal electricity slurry (Ion metal plasma, IMP) mode such as processing procedure activates processing procedure, the surface that 31 needs of this circuit board unit are engaged presents the atom and the molecular structure of nano-scale, so that directly under the normal temperature vacuum, engage, making needs the contact mat 311a part of the circuit layer 311 that engages to electrically connect mutually in this circuit board unit 31 respectively, form multilayer circuit board 30 (shown in Fig. 3 E), the follow-up vacuum activation processing procedure that also can utilize on this multilayer circuit board 30 is to continue bonded circuitry plate unit 31.
In addition, also a plurality of circuit board units 31 can be carried out the normal temperature vacuum engagement simultaneously, replacement successively increases layer technology and once is bonded into multilayer circuit board 30 structures, shortens the production time whereby and can simplify making flow process (shown in Fig. 5 A and Fig. 5 B).For further improving the engaging force between these circuit board units, can after finishing joint, 31 of circuit board units toast processing procedure, and remove aqueous vapor and increase its bond strength.
See also Fig. 3 E or Fig. 5 B, therefore, the multilayer circuit board 30 that makes according to above-mentioned method for making comprises a plurality of circuit board units 31, respectively 31 of this circuit board units are separated with insulating barrier 32, and this insulating barrier 32 is formed with opening, contact mat 311a for adjacent circuit plate unit 31 surperficial corresponding circuits layers 311 is electrically conducted mutually, makes the surface of 31 joints of these circuit board units pass through the surface active processing procedure in advance, effectively is bonded together for these circuit board units 31.
Embodiment 2
It shown in Fig. 6 A to Fig. 6 E the generalized section of the embodiment 2 of method for making multi-layer circuit board of the present invention.
As shown in Figure 6A, at first, provide a plurality of circuit board units 31.The form of these circuit board units 31 can be any in individual layer, bilayer and the multilayer circuit board institute cohort group, it mainly includes insulating barrier 310 and the patterned circuit layer 311 that is formed on this insulating barrier, and this patterned circuit layer 311 can electrically connect by a plurality of holes that electrically conduct that are formed in this insulating barrier 310.Wherein, the form of these circuit board units 31 can be the circuit board unit 31 shown in previous Fig. 4 A to Fig. 4 C, and these circuit board units 31 only are used to illustrate applicable circuit board unit kind, and unrestricted application category of the present invention, the making of this circuit board unit 31 all is a prior art in addition, so no longer explanation.
Shown in Fig. 6 B, form insulating barrier 32 on these circuit board unit 31 surfaces, and carry out the thinning processing procedure, manifest circuit layer 311 upper surfaces of this circuit board unit 31, it can utilize technology removal partial insulating layer 32 such as grinding, manifests the contact mat 311a part (shown in Fig. 6 C) of the circuit layer 311 that need engage at least.This insulating barrier 32 can for example be that epoxy resin (Epoxyresin), polyimides (Polyimide), cyanate (Cyanate Ester), glass fibre (Glassfiber), bismaleimide-triazine resin (BT, Bismaleimide Triazine) or blending epoxy and glass fibre materials such as (FR5) constitute.Then, can the planarization processing procedure such as for example polish to the surface (comprising circuit layer and surface of insulating layer) of these circuit board units 31, and can under suitable environment, (in vacuum environment, inert gas environment or chemical solution) carry out clean program to remove its surperficial oxide layer, improve follow-up surface active process quality.
Shown in Fig. 6 D, these circuit board units 31 are placed under the vacuum state, by electricity slurry (Plasma), reactive ion etching (Reactive ionic etching, RIE) or ionic metal electricity slurry (Ion metal plasma, IMP) mode such as processing procedure activates processing procedure, the surface that 31 needs of this circuit board unit are engaged presents the atom and the molecular structure of nano-scale, can directly under the normal temperature vacuum, engage, the contact mat 311a part of the circuit layer 311 that will engage in this circuit board unit 31 is respectively electrically connected mutually, form multilayer circuit board 30 (shown in Fig. 6 E), the follow-up vacuum activation processing procedure that also can utilize on this multilayer circuit board 30 is to continue bonded circuitry plate unit 31.
In addition, also the circuit board unit 31 that can simultaneously a plurality of surface insulation layers 32 have been finished thinning carries out the normal temperature vacuum engagement, replacement successively increases layer technology and once is bonded into multilayer circuit board 30, shortens the production time whereby and can simplify making flow process (shown in Fig. 7 A and Fig. 7 B).For further improving the engaging force between these circuit board units, can after finishing joint, 31 of circuit board units toast processing procedure, and remove aqueous vapor and increase its bond strength.
See also Fig. 6 E or Fig. 7 B, therefore, the multilayer circuit board 30 that makes according to above-mentioned method for making comprises a plurality of circuit board units 31, respectively 31 of this circuit board units are separated with insulating barrier 32, and this insulating barrier 32 exposes outside the contact mat 311a of adjacent circuit plate unit 31 surperficial corresponding circuits layers 311 through thinning, and these circuit layers 311 are electrically conducted mutually, the surface active processing procedure is passed through on the surface of 31 joints of these circuit board units in advance, effectively be bonded together for these circuit board units 31.
Because, multilayer circuit board of the present invention and method for making thereof simultaneously the combined circuit plate pressure programming and increase the advantage of layer processing procedure, at first, carry out the configuration processing procedure of a plurality of circuit board units, and can be in advance this circuit board unit be respectively carried out every test, to improve the successive process acceptance rate, effectively avoid the existing waste product problem that produces in layer processing procedure that increases, simultaneously, carrying out respectively this circuit board unit when engaging, be by electricity slurry (Plasma) under vacuum environment, reactive ion etching (Reactive ionic etching, RIE) or ionic metal electricity slurry (Ion metal plasma, IMP) mode such as processing procedure, surface at this circuit board unit activates processing procedure, make the surface that will engage between this circuit board unit present the atom and the molecular structure of nano-scale, can be follow-up directly at the joint that carries out under the normal temperature vacuum between these circuit board units, effectively avoid in the existing pressure programming, various storeroom thermal coefficient of expansions (CTE) different the thermal stress that produces and warpage issues and electric conducting material problem such as WU cream additionally is provided, moreover, the present invention can carry out the joint of a plurality of circuit board units simultaneously, the circuit board that has the multilayer circuit layer with rapid formation, effectively save fabrication steps and cost, in addition, because of this circuit board unit can be pre-formed the patterned electricity line structure, and when engaging, directly utilize and be formed at its surperficial circuit layer and be electrically conducted mutually, therefore, need not additionally to form again conductive through hole, so can effectively improve its configuration flexibility.Moreover, also can be by the thickness of insulating layer between this circuit board unit of thinning in advance, the multilayer circuit board that follow-up joint will be finished has more frivolous thickness, to be applicable to small-sized electronic building brick.
Claims (17)
1. a method for making multi-layer circuit board is characterized in that, this method for making comprises:
A plurality of circuit board units with patterned circuit layer are provided;
On these circuit board units, form insulating barrier, and the circuit layer that needs in this circuit board unit electrically to engage is exposed outside this insulating barrier; And
These circuit board units are placed under the vacuum state, carry out the surface active processing procedure and engage.
2. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, this insulating barrier makes this insulating barrier form a plurality of openings by patterning process, and exposing outside needs the circuit layer that electrically engages in this circuit board unit.
3. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, this insulating barrier is by the thinning processing procedure, and exposing outside needs the circuit layer that electrically engages in this circuit board unit.
4. method for making multi-layer circuit board as claimed in claim 3 is characterized in that, this insulating barrier borrows grinding technique to remove partial insulating layer, exposes outside the circuit layer that need electrically engage in this circuit board unit.
5. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, before this circuit board unit surface activates processing procedure, and circuit layer surface and the surface of insulating layer planarization that these circuit board units are exposed earlier.
6. method for making multi-layer circuit board as claimed in claim 5 is characterized in that, this circuit board unit of finishing planarization is carried out clean program, removes its surperficial oxide layer.
7. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, this method for making is toasted after also being included in and finishing joint between this circuit board unit.
8. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, being bonded under the normal temperature vacuum between this circuit board unit carried out.
9. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, these circuit board units are any in individual layer, bilayer and the multilayer circuit board institute cohort group.
10. method for making multi-layer circuit board as claimed in claim 1 is characterized in that, the joint of these circuit board units adopts gradation and once finishes a kind of in the joint.
11. method for making multi-layer circuit board as claimed in claim 1, it is characterized in that, this activation processing procedure is undertaken by a kind of mode in electricity slurry, reactive ion etching and the ionic metal plasma manufacture, makes the surface that needs between this circuit board unit to engage be the atom and the molecular structure of nano-scale.
12. multilayer circuit board, it is characterized in that, this circuit board comprises a plurality of circuit board units, be separated with insulating barrier between respectively between this circuit board unit, and respectively this insulating barrier is formed with opening, contact mat for adjacent circuit plate cell surface corresponding circuits layer is electrically conducted mutually, and wherein, the surface that engages between these circuit board units through the surface active processing procedure with effective joint together.
13. multilayer circuit board as claimed in claim 12 is characterized in that, these circuit board units are any in individual layer, bilayer and the multilayer circuit board institute cohort group.
14. multilayer circuit board as claimed in claim 12, it is characterized in that, the surface active of this circuit board unit is undertaken by a kind of mode in electricity slurry, reactive ion etching and the ionic metal plasma manufacture, makes the surface that needs between this circuit board unit to engage be the atom and the molecular structure of nano-scale.
15. multilayer circuit board, it is characterized in that, this circuit board comprises a plurality of circuit board units, respectively be separated with insulating barrier between this circuit board unit, and this insulating barrier exposes outside the contact mat of adjacent circuit plate cell surface corresponding circuits layer through thinning, is electrically conducted mutually by these contact mats for these circuit board units, wherein, the surface that engages between these circuit board units through the surface active processing procedure with effective joint together.
16. multilayer circuit board as claimed in claim 15 is characterized in that, these circuit board units are any in individual layer, bilayer and the multilayer circuit board institute cohort group.
17. multilayer circuit board as claimed in claim 15, it is characterized in that, the surface active of this circuit board unit is undertaken by a kind of mode in electricity slurry, reactive ion etching and the ionic metal plasma manufacture, makes the surface that needs between this circuit board unit to engage be the atom and the molecular structure of nano-scale.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100307162A CN1316861C (en) | 2004-03-31 | 2004-03-31 | Multi-layer circuit board and mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100307162A CN1316861C (en) | 2004-03-31 | 2004-03-31 | Multi-layer circuit board and mfg. method |
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| CN1678167A CN1678167A (en) | 2005-10-05 |
| CN1316861C true CN1316861C (en) | 2007-05-16 |
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| CNB2004100307162A Expired - Fee Related CN1316861C (en) | 2004-03-31 | 2004-03-31 | Multi-layer circuit board and mfg. method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414595B (en) * | 2007-10-18 | 2012-08-08 | 欣兴电子股份有限公司 | Package substrate and manufacturing method thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008028376A (en) * | 2006-06-20 | 2008-02-07 | Sanyo Electric Co Ltd | Circuit board, semiconductor module and method of manufacturing circuit board |
| US8546698B2 (en) * | 2009-10-30 | 2013-10-01 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
| CN103208428B (en) * | 2012-01-12 | 2016-01-20 | 欣兴电子股份有限公司 | Base plate for packaging and method for making thereof |
| JP5941735B2 (en) * | 2012-04-10 | 2016-06-29 | 新光電気工業株式会社 | Wiring board manufacturing method and wiring board |
| CN112118682A (en) * | 2019-06-21 | 2020-12-22 | 培英半导体有限公司 | Method for forming copper layer on circuit board and circuit board with sputtered copper layer |
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| CN1269695A (en) * | 1999-04-01 | 2000-10-11 | 日本胜利株式会社 | Printed circuit board and producing method thereof |
| CN1384701A (en) * | 2001-05-07 | 2002-12-11 | 索尼公司 | Multi-layered printed circuit board and its making process |
| JP2003347733A (en) * | 2002-05-28 | 2003-12-05 | Yamanashi Matsushita Electric Works Ltd | Printed circuit board and method for its manufacturing |
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| JPH01131883A (en) * | 1987-11-17 | 1989-05-24 | Matsushita Refrig Co Ltd | Vegetable storage vessel for refrigerator |
| US5830563A (en) * | 1995-11-29 | 1998-11-03 | Nec Corporation | Interconnection structures and method of making same |
| CN1269695A (en) * | 1999-04-01 | 2000-10-11 | 日本胜利株式会社 | Printed circuit board and producing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1678167A (en) | 2005-10-05 |
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