CN1316590C - 用于在具有帽盖层的半导体互连结构上沉积金属层的方法 - Google Patents

用于在具有帽盖层的半导体互连结构上沉积金属层的方法 Download PDF

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CN1316590C
CN1316590C CNB2003801023725A CN200380102372A CN1316590C CN 1316590 C CN1316590 C CN 1316590C CN B2003801023725 A CNB2003801023725 A CN B2003801023725A CN 200380102372 A CN200380102372 A CN 200380102372A CN 1316590 C CN1316590 C CN 1316590C
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sputter etching
cap layer
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拉里·克莱温格
蒂莫西·达尔顿
马克·霍因克斯
斯蒂芬斯·达尔多
考施科·库玛
小道格拉斯·拉图利普
徐顺天
安德鲁·西蒙
王允愈
杨智超
杨海宁
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Abstract

公开了一种在用于半导体晶片的互连结构上沉积金属层的方法。在该方法中，金属导体(14)被帽盖层(16)和介质层(18)覆盖。对介质层图案化以露出帽盖层。然后对帽盖层溅射蚀刻以去除帽盖层并露出金属导体(14)。在溅射蚀刻过程中，帽盖层被重新沉积(22)到图案的侧壁上。最后，至少一层被沉积到图案中并覆盖重新沉积的帽盖层。

Description

用于在具有帽盖层的半导体 互连结构上沉积金属层的方法
相关申请
本申请涉及与本申请同一日提交、名称为“A Method forDepositing a Metal Layer on a Semiconductor InterconnectStructure”的美国专利申请10/318,605。
技术领域
本发明涉及半导体处理，更具体地涉及包含使用铜冶金(coppermetallurgy)的先进互连结构的半导体晶片的处理。
背景技术
使用铜冶金的先进互连结构表现出与功能特性相关的许多技术优点。这些优点中最重要的是实现在热循环下稳定的低接触电阻，以及在电迁移和应力迁移下的良好可靠性。
电迁移是在诸如铜的导体中离子响应电流通过的运动，并且可以最终导致导体的开路失效。
已经发展了各种现有技术的方法以防止或限制电迁移，特别是在铜金属线和互连中，因此，Hsiao等人的美国专利6,191,029公开了一种用于制造金属互连的方法，包括在沟槽中沉积阻挡金属层、沉积诸如铜的导电金属以填充沟槽、蚀刻掉一部分铜从而在沟槽中形成空腔，采用顶部阻挡层以及随后的介质材料填充空腔，其公开内容以引用方式结合在本文中。在铜上方的共形顶部阻挡层提高了抗电迁移性。
Chen的美国专利6,200,890公开了一种用于制造金属互连的方法，包括在形成铜导线之后蚀刻掉一部分介质层，使得铜导线从介质层的表面突出，然后在突出的铜导线上方形成顶部阻挡层，以防止电迁移和漏电流，其公开内容以引用方式结合在本文中。
Nogami等人的美国专利6,214,731公开了一种用于制造金属互连的工艺，包括在沟槽中沉积阻挡金属层，采用硅烷处理阻挡金属层以形成硅层，并且在硅层上面沉积铜以填充沟槽，从而铜和硅反应以形成硅化铜层，其公开内容以引用方式结合在本文中。硅化铜层改善了界面缺陷密度并提高了抗电迁移性。
尽管存在各种现有技术的方法以处理电迁移的已知问题，但现有技术看起来没有注意到传统上采用的金属层沉积步骤对于电迁移问题的影响。对于有机介质膜的应用，对这些挑战的漠视已经加剧了。因此，在有机介质中的互连结构如沟槽和通路中观察到的侧壁和底切剖面表现出其中和其自身的空前困难，这些困难在于在金属填充之前实现对所述沟槽和通路的高度完整的衬里和籽层覆盖度。另一个与有机介质膜相关的问题是所谓的与时间有关的介质分解(TDDB)，其中例如铜穿过不完整的侧壁层，污染(poison)介质材料。因此，对制造金属互连特别是铜互连的方法仍有需要，所述互连具有提高的抗电迁移性、减少了应力迁移并避免TDDB。
在其它方面中，目前已知的金属阻挡方案包括对图案化介质的氩溅射清洁。不利的是，所有本发明人已知的对电迁移和TDDB问题的解决方案都包括沉积金属层或连续的金属层，而没有考虑在连续的金属层沉积之间的溅射步骤。实际上，由于与短接屏蔽(shorting of theshielding)有关的考虑，沉积工具销售方特别推荐的是反对在金属层上的氩溅射。
发明内容
根据本发明，提供了一种在半导体晶片的互连结构上沉积金属层的方法，该方法包括以下步骤：
(a)提供包括金属导体的互连结构，所述金属导体由帽盖层和介质层覆盖；
(b)图案化介质层，以形成露出金属导体上方的帽盖层的开口；
(c)在所述开口的侧壁和底部上沉积衬里层；
(d)溅射蚀刻衬里层和帽盖层，以露出金属导体并且在开口的侧壁上至少部分地重新沉积衬里层和帽盖层；以及
(e)在开口的侧壁和底部上沉积至少一层金属层，并覆盖重新沉积的衬里层和帽盖层。
附图说明
本发明的特征被认为是新颖的，并且本发明的要素特征具体地在权利要求书中提出。附图仅用于示例性的目的而没有按比例绘出。然而，本发明自身作为结构和操作方法可以通过参考以下结合附图的详细描述而被最好地理解，其中：
图1A至1E是说明根据本发明的工艺的第一实施方式用于沉积金属层半导体晶片的截面侧视图。
图2A至2E是说明根据本发明的工艺的第二实施方式用于沉积金属层的半导体晶片的截面侧视图。
具体实施方式
更详细地参照附图，特别是参照图1A至1E，说明根据本发明的工艺的第一实施方式。首先参照图1A，示出了半导体晶片10的两个层面。第一层面包括层间介质(ILD)层12、金属导线14和帽盖层16。为了清楚的目的，没有示出下面的硅。在处理半导体晶片10的下一层面时，帽盖层16保护金属导线14不受氧化、湿度和污染的影响。此外，帽盖层16还用于防止导线14不必要地扩散到ILD18中。在下一层面，采用传统的技术，ILD18被沉积在帽盖层16上。
对于ILD12、18，可以使用任何介质材料。然而对目前的亚微米高密度集成的电路的需求要求ILD12、18优选地由有机介质层构成，更优选地由低k有机介质层构成，例如具有通常定义为大约3.0或更低的低介电常数的有机介质材料。所述低k有机介质材料的一个优选的例子是SiLK(聚(亚芳香醚)，可从Dow Chemical购得)。ILD12、18的成分不限于有机低k介质。而是可以由对于本领域的技术人员已知为有用的任何低k介质组成。帽盖层16可以由任何合适的帽盖材料制成，如氮化硅、碳化硅、碳氧化硅、氢化的碳化硅、二氧化硅、有机硅酸盐玻璃以及其它的低k介质。金属导线14可以包括铜、钨或铝。如果金属导线14是第一金属层面，则钨是优选的，同时在随后的层面中铜是优选的。
然后，参照图1B，优选使用传统的光刻和蚀刻技术(例如反应离子蚀刻(RIE))，在ILD18上和穿过ILD18图案化出电路图案20。例如，电路图案包括用于形成到金属导线14的金属导电互连的互连结构，如沟槽20a和通路20b。所示的互连结构是双镶嵌结构，但这种特定的结构对本发明不是必需的。取决于所制造的多层面半导体集成电路的预定设计需要，电路图案可以包括任何所需的线(沟槽结构)、通路(互连)以及诸如焊盘和器件(如FET)的其它结构的图案，这些结构通常设计在所述的半导体晶片中。超大规模集成(VISI)技术可能包括五个或六个(或者可能更多)层面的集成和互连电路元件的图案，这些电路元件具有各自的亚微米尺寸特征。
同样在图1B中示出了电路图案20现在具有露出的帽盖层16。在半导体器件中使用铜线时，金属线必须受到保护，从而在处理ILD18时不受氧化、湿度和其它环境污染的影响。这对于铜线更是如此。因此，需要保护性的帽盖层16。在图案化ILD18时，帽盖层16也可以用作蚀刻停止层。
在现有技术的处理方法中，可以通过反应离子蚀刻或类似的工艺去除帽盖层16，晶片移出蚀刻室然后传送到沉积室。在这样的传送步骤中，金属导线14将受大气的影响，从而暴露于氧化和湿度，以及可能的污染。在传送到沉积室之后，金属导线将被轻微地蚀刻以去除任何氧化或污染。
根据本发明，使用溅射蚀刻去除金属导线14上方的帽盖层16。尽管为了示例和非限制的目的而示出氩，但可以将任何纯气体如Ar、He、Ne、Xe、N2、H2、NH3、N2H2或其混合物用于溅射蚀刻工艺。如果需要，金属导线14也可被溅射蚀刻，结果致使进行如图1C所示的回蚀刻(etch back)金属导线14。回蚀刻金属导线是可选的步骤。本发明人已经发现当帽盖层16被溅射蚀刻时，部分帽盖层16重新沉积22到电路图案20(尤其是通路20b)的侧壁上，如图1C所示。所述的重新沉积在电路图案20(尤其是通路20b)附近提供了一些额外的材料(当Cu是通路/沟槽金属时，作为额外的Cu扩散阻挡材料尤其有用)，并且减轻了之后可能产生的电迁移和TDDB问题。
溅射蚀刻是一种其中晶片被固定在真空室中的两个电偏置的电极之间、随后向真空室内送入气体以产生轰击晶片表面的等离子体的工艺。离子化的颗粒导致对晶片表面的蚀刻。在溅射蚀刻时使用Ar气，本发明人已经发现氩溅射蚀刻的优选操作条件如下：气流20 sccm氩，温度20℃，顶部电极的偏置400KHz和750W，台偏置13.56MHz和400W，处理压力大约0.6mTorr。
现在参照图1D，在晶片仍在沉积室的时候，在电路开口20中沉积衬里层或多层。优选地，按传统方法沉积(例如通过化学气相沉积(CVD)、等离子体气相沉积(PVD)或其它工艺)TaN、Ta、Ti、Ti(Si)N或W的第一层24，之后是第二按传统方法沉积的TaN、Ta、Ti、Ti(Si)N、W或Cu层26。金属导线14现在被密封在内，并可以按需要移动至其它的室。如果铜将是用于金属导线14的材料，那么可以在第二层26的顶部上沉积铜籽层(未示出)。在优选的实施方式中，第一层24是TaN，第二层26是Ta，随后是铜籽层。
然后，按传统方法沉积填充冶金(fill metallurgy)28，随后是诸如化学机械抛光等的平面化工艺，以导致形成如图1F所示的结构。如果填充冶金28是铜，则从沉积室移出晶片，并按传统方法镀覆铜填充冶金28。如果填充冶金28是W或Al，则可以在同一沉积室中沉积W或Al，或者，在传统的实践中，更多的是移动到专门设置用以处理W或Al填充冶金28的室中。
现在参照图2A至2E，描述根据本发明的工艺的第二实施方式。图2A与前述的图1A相同，包括可以用于各层的材料。类似地，图2B与图1B相同，除了还没有发生溅射蚀刻。
现在参照图2C，按传统方法沉积TaN、Ta、Ti、Ti(Si)N或W的第一层24。现在使半导体晶片10’受到溅射蚀刻。操作参数与较早时讨论的相同。在本发明的该实施方式中，金属层24和帽盖层16同时被溅射蚀刻，以获得如图2D所示的结构。再一次，如果需要，可以继续溅射蚀刻通过帽盖层16，结果致使进行回蚀刻金属导线14。首先是金属层24、然后是帽盖层16被重新沉积30到通路20b的侧壁上。如果金属导线14也被溅射蚀刻，则金属导线14被重新沉积30到重新沉积的帽盖层上。
作为沉积工艺的正常结果，第一金属层24在ILD18的顶部上和在沟槽20a中的水平部分通常比第一金属层24在通路20b底部处的水平部分厚很多。因此，在溅射蚀刻之后，在ILD18的顶部上和在沟槽20a中的第一金属层24的水平部分被留下，尽管在一定程度上被减薄。
之后，如图2E所示，按传统方法沉积TaN、Ta、Ti、Ti(Si)N、W或Cu的第二金属层26。然后，从沉积室移出晶片，随后沉积填充冶金28，优选为镀铜。如果铜被用作填充冶金，则通常沉积前面的铜籽层。然后，通过化学机械抛光或其它类似的工艺平面化半导体晶片10’，以获得图2E所示的结构。
本领域的技术人员显然可知，对于本公开内容，在本文中具体描述的那些实施方式之外可以不背离本发明的精神而对本发明进行其它修改。因此，这样的修改也认为在本发明的范围之内，如同仅由权利要求书限定的那样。

Claims (13)

1.一种用于在半导体晶片的互连结构上沉积金属层的方法，该方法包括以下步骤：
(a)提供包括金属导体的互连结构，所述金属导体由帽盖层和介质层覆盖；
(b)图案化介质层，以形成露出金属导体上方的帽盖层的开口；
(c)在所述开口的侧壁和底部上沉积衬里层；
(d)溅射蚀刻衬里层和帽盖层，以露出金属导体并且在开口的侧壁上至少部分地重新沉积衬里层和帽盖层；以及
(e)在开口的侧壁和底部上沉积至少一层金属层，并覆盖重新沉积的衬里层和帽盖层。
2.根据权利要求1的方法，其中所述帽盖层选择自由氮化硅、碳化硅、碳氧化硅、氢化碳化硅、二氧化硅和有机硅酸盐玻璃构成的组。
3.根据权利要求1的方法，其中所述帽盖层的厚度薄于介质层。
4.根据权利要求1的方法，其中至少一层金属层选自由TaN、Ta、Ti、Ti(Si)N和W构成的组。
5.根据权利要求4的方法，其中所述金属层的厚度为1nm至50nm。
6.根据权利要求1的方法，其中所述衬里层选自TaN、Ta、Ti、Ti(Si)N和W构成的组，所述金属层选自TaN、Ta、Ti、Ti(Si)N、W和Cu构成的组。
7.根据权利要求6的方法，其中所述衬里层是TaN，所述至少一层金属层是Ta。
8.根据权利要求1的方法，进一步包括步骤：
(f)采用铜填充所述开口的步骤。
9.根据权利要求1的方法，其中所述开口是通路或沟槽。
10.根据权利要求1的方法，其中所述金属导体选自由铜、钨和铝构成的组。
11.根据权利要求1的方法，其中用于溅射蚀刻的气体选自由Ar、He、Ne、Xe、N2、H2、NH3、N2H2及其混合物构成的组。
12.根据权利要求1的方法，其中在所述溅射蚀刻的步骤中，在至少部分地溅射蚀刻金属导体之后停止溅射蚀刻。
13.根据权利要求1的方法，其中在溅射蚀刻的步骤中，溅射蚀刻停止在金属导体的顶部表面上。
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