CN1314114C - 适于传输高频信号的电子器件载体 - Google Patents

适于传输高频信号的电子器件载体 Download PDF

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CN1314114C
CN1314114C CNB028201981A CN02820198A CN1314114C CN 1314114 C CN1314114 C CN 1314114C CN B028201981 A CNB028201981 A CN B028201981A CN 02820198 A CN02820198 A CN 02820198A CN 1314114 C CN1314114 C CN 1314114C
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electronic device
conductive layer
signal
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chip
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戴夫·阿尔科
罗纳德·诺瓦克
弗朗西丝科·普雷达
斯蒂法诺·S·奥格乔尼
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Abstract

一种适于传输高频信号的电子器件载体(110)，包括具有彼此绝缘的多个导电层(240a到240g)的电路衬底，按照从其中形成多个信号轨迹(200)的导电层的第一层(240a)的顺序安排所述导电层，每一个信号轨迹结束于接触区域(205)，用于传输高频信号；和可与参考电压或接地连接的参考结构(215a，215b，230)，用于屏蔽所述信号轨迹。该参考结构包括在与该第一导电层相邻的导电层的第二层(240b)中形成的至少一个参考轨迹(230)，和在不同于第一和第二导电层的导电层之一(240d)中形成的至少一个另外的参考轨迹，通过插入与任何信号、参考电压或接地轨迹不相连的浮动导电轨迹，将至少除了对应于相关接触区域的正交投影的区域以外的每一信号轨迹的一部分在平面图中叠加到对应参考轨迹上，和将与相关于每一信号轨迹的接触区域的正交投影对应的区域的至少一部分在平面图中叠加到对应的其它参考轨迹上。

Description

适于传输高频信号的电子器件载体
技术领域
本发明涉及电子器件互连的领域，并具体涉及适于传输高频信号的电子器件载体。
背景技术
以半导体材料的芯片中集成的电路实现一些种类的电子元件。该芯片典型安装在载体上，从而保护芯片免受机械应力，并然后封装在包装中。该芯片载体包括具有导电轨迹(tracks)的绝缘衬底；每一轨迹与该芯片的对应端联结，并以接触焊盘结束，典型用于连接到印刷电路板。同样，印刷电路板一般包括在绝缘材料中形成的几个导电层，适于在几个电子器件之间或电子器件和连接器之间传输信号。
当器件的开关速度高于1GHz时钟速率时，需要不再将电子信号传输认为是轨迹上简单的点到点传输，而认为是电路迹线(circuit trace)上的电流支持的电磁波的传播。这样的电子器件载体(芯片载体和印刷电路板)上的迹线，也称为传输线，代表包括至少两个具有特殊特性(传输线宽度之间的关系、传输线之间的距离、传输线和参考面之间的电介质厚度)的导电路径的系统。这些传输线包括近距离形成、并与参考电压或接地连接的导电信号轨迹或迹线和另一轨迹和/或导电面，用于保护信号轨迹不受电磁干扰。波沿着信号轨迹和下面的参考电压或接地平面定义的传输线传播，形成信号电流的完整环路。当芯片工作在高频，例如大于1GHz时，电子器件载体的感应可能严重影响电子系统整体的性能。
具体说，传输线中的任何不连续(转换)，例如结构、材料特性和设计特征的任何改变，都产生反射波。而且，该系统包括寄生结构(电容、电感和电阻)，用作所传输信号的低通滤波器。结果，沿着该传输线传播的电磁波的完整性得不到保护。
在低压(逻辑值0)和高压(逻辑值1)之间切换的传输信号产生方波。由于传输线中的所有不连续，该波经受降级并一般被接收为伪正弦波。通过所谓“眼图”可呈现传输波的质量，该眼图将所接收信号的值绘制为控制该电子器件的时钟信号的相位的函数。传输线中的上述不连续性减小了眼图的开口；所以，很难理解是否实际发生了开关转换或信号基线的移动是否由于背景噪声。
在利用电源电压的降低电平(低至1.2V)工作的现代电子系统中，这些缺点特别明显。在这种情况下，具有很低的容限来区别逻辑值0(0V)和逻辑值1(1.2V)。
而且，电子器件小型化的持续趋势需要降低芯片载体和印刷电路板导电轨迹的尺寸。然而，传输线的阻抗必须保持在优化电子器件的性能的期望值上(典型为50Ω)。所以，有必要在导电轨迹和接地平面之间使用很细的电介层(由于该阻抗与轨迹宽度成反比，并与电介层厚度成正比)。导电轨迹和接地平面之间的短距离增加了对应寄生电容的值；结果，严重降低了传输线的带宽。
所以，随着电子器件载体，即芯片载体或印刷电路板的传输质量的降级，可使得电子器件工作在远低于该芯片提供的工作频率的频率上。
发明内容
因此，本发明的主要目的是提供一种电子器件载体以补救上述现有技术的缺点。
本发明的一个目的是提供一种适于传输高频信号的可靠电子器件载体。
本发明的另一个目的是提供一种适于传输高频信号的电子器件载体，用于匹配其上连接的电子器件和电子系统的系数膨胀。
本发明的另一个目的是提供一种适于传输高频信号的平坦电子器件载体。
本发明的另一个目的是提供一种适于传输高频信号的电子器件载体，用于改善焊盘共面性，从而提供焊盘和电子器件I/O之间的可靠接触。
本发明的另一个目的是提供一种适于传输高频信号的电子器件载体，用于提供其不同介电材料层之间的可靠粘贴。
通过一种适于传输高频信号的电子器件载体而达到了这些和其他相关目的的实现，该电子器件载体包括具有彼此绝缘的多个导电层的电路衬底，按照从其中形成多个信号轨迹的导电层的第一层的顺序安排所述导电层，每一个信号轨迹结束于接触区域，用于传输高频信号；和可与参考电压或接地连接的参考结构，用于屏蔽所述信号轨迹，
其特征在于：
该参考结构包括在与该第一导电层相邻的导电层的第二层中形成的至少一个参考轨迹，和在不同于第一和第二导电层的导电层之一中形成的至少一个另外的参考轨迹，通过插入与任何信号、参考电压或接地轨迹不相连的浮动导电轨迹，将至少除了对应于相关接触区域的正交投影的区域以外的每一信号轨迹的一部分在平面图中叠加到对应参考轨迹上，和将与相关于每一信号轨迹的接触区域的正交投影对应的区域的至少一部分在平面图中叠加到对应的其它参考轨迹上。
通过附图和详细说明，本领域普通技术人员将更加清楚本发明的其他优点。意欲将任何其他优点合并到这里。
附图说明
图1示出了能使用根据本发明的芯片载体的电子模块的剖面图。
图2包括图2a、2b和2c，描绘了根据本发明的具体芯片载体。图2a和2b分别图示了平面图和剖面图，而图2c是特定导电层的平面图。
图3包括图3a和3b，分别是公知电子器件和包括根据本发明的芯片载体的电子器件中的信号的眼图。
图4包括图4a和4b，示出了频域中的相同信号。
具体实施方式
为了说明的目的，以下描述基于焊球网格阵列(Ball Grid Array-BGA)封装，其中用控制折叠芯片连接(Controlled Collapse Chip Connection)(IBM C4技术)执行芯片到芯片载体的互连，广泛称为倒装芯片连接(Flip-Chip Attach---FCA)。该技术提供了高I/O密度、均匀的芯片功率分布、高冷却能力和高可靠性。
具体参考图1，描绘了BGA类型的电子模块100。该电子模块100包括半导体材料的芯片105，其中集成了在高频工作的电源电路，例如时钟速率5GHz。由低压电源，例如1.2V，供电的芯片105被安装在层叠(laminate)芯片载体110上，所述层叠芯片载体110包括依靠例如聚四氟乙烯(PTFE)的介电材料而彼此绝缘的例如由铜制成的几个导电层。由C4球(ball)115执行芯片105到芯片载体110互连，而由BGA球120完成芯片载体110到印刷电路板(未示出)的互连。芯片载体110粘贴到包括芯片105的腔的刚性元件125和任选的例如电容器130的其他电子元件。刚性元件125最好包括例如由铜制成的金属板，它增加整体电子模块100的硬度，并提供别的路径以驱散芯片105产生的热能。芯片105和刚性元件125由例如铜制成的盖子135覆盖，该盖子135也用作驱散芯片105产生的热能和为芯片105提供机械保护的散热器。层140包括将芯片载体110、芯片105、刚性元件125和盖子135固定到一起的例如环氧胶的胶水。胶水也补偿芯片载体110、芯片105、刚性元件125和盖子135的热膨胀的不同系数。
同样考虑该电子器件是否BGA类型、该芯片是否包含(数字)电源电路、其是否工作在不同频率或不同电源等。
现在考虑图示了芯片载体110的部分平面图的图2a，其中示出了附图标记为200的轨迹，以焊盘205结束，该焊盘205可能经过直通孔(through via)与互连球210相连，用于传输高频信号。分别标为215a和215b的一对共面轨迹安排在信号轨迹200周围，并可形成在图示的相同导电层中。共面轨迹215a和215b以互连球225的焊盘220结束，该互连球225链接到在另一导电层中形成的轨迹230，和在印刷电路板(未表示)中形成的参考电压或接地轨迹。轨迹230部分叠加到轨迹200和共面轨迹215a和215b。
轨迹200上传输的高频信号产生沿着由信号轨迹200、共面轨迹215a和215b以及轨迹230限定的传输线传播的电磁波。
现在参考图2b所示的沿线A-A的剖面，芯片载体110通过绝缘膜235和235’而分别与芯片105(未表示)和印刷电路板(未表示)绝缘。绝缘膜235和235’包括其中形成例如焊盘205的焊盘的开口。芯片载体110包括通过例如PTFE的介电材料245而彼此绝缘的几个导电层240a到240g(讨论中的该例中有7个)。导电层240a到240g提供芯片105和在其上焊接电子模块100的印刷电路板(未表示)之间的电连接。一般来说，导电层240a到240g中轨迹的设计被优化，从而降低信号和传输延迟之间的串扰。结果，导电层240b、240d和240f经常用于形成参考电压或接地轨迹，导电层240c和240e用于传输(高频)信号，而导电层240a和240g用于将球焊盘连接到内部导电层240b到240f，并从而用于形成(高频)信号轨迹或参考电压或接地轨迹。
因而，作为图示，信号轨迹200以及共面轨迹215a和215b形成在第一导电层240a中(从芯片载体110的较低面开始)，并且轨迹230形成在第二导电层240b中(与第一导电层相邻)。
转接孔(via-hole)250将导电层240d中形成的参考电压或接地平面连接到轨迹230以及共面轨迹215a和215b，并然后连接到互连球225。
在导电层240d中形成的参考电压或接地平面、轨迹230以及共面轨迹215a和215b定义了参考结构，该参考结构控制与信号轨迹200关联的传输线的阻抗，并屏蔽信号轨迹200不受电磁干扰。
导电层的接近产生寄生电容。具体说，在互连球210和225之间以及在互连球210和导电层240b中形成的轨迹之间形成寄生电容。
本发明人已发现了已知电子器件的性能降级主要是由于与互连球210关联的传输线中的不连续。该传输线实际上经过方向的急剧变化，从沿着信号轨迹200的水平方向到前往互连球210的垂直方向。具体说，在互连球210和导电层240b中形成的轨迹之间形成的寄生电容如果与互连球210和225之间形成的寄生电容相比，则具有相对高的电容。结果，这些电容器在高频担当低通滤波器，并因此降低传输带宽。通过根据与例如焊盘205的焊盘对应的接触区域的正交投影而实现导电层240b和240c中的开口，即通过排除任何信号或参考电压轨迹，可降低在互连球210和导电层240b中形成的轨迹之间形成的寄生电容。然而，这些开口可导致制造缺陷，例如由于当考虑介电层厚度，例如35μm时，不能忽视封装结构的导电层厚度，例如12μm，而导致的芯片载体110的平坦。补充通过去除导电层240b中的导电材料而创建的大区域，例如直径600到800μm，以保持整个封装表面区域的平坦，是如何困难变得很明显。另一个制造缺陷是扩展的介电材料到介电材料的界面，它对于这样大的区域是很关键的粘贴界面。因此，本发明在前述方法的相反方向进行，它存在于实现环形开口，例如255，其中由导电材料制成的例如260的中心浮动盘，如图2b和2c所示不与任何信号、参考电压或接地平面相连。
形状265代表不必形成信号、参考电压或接地平面从而降低上述低通滤波效果的位置。通过重叠具有与导电层240a垂直的公共轴线的圆锥和圆柱部分而形成形状265。由其中分别形成信号和参考电压或接地轨迹的第一和第二导电层240a和240b而划定第一圆柱部分的界限。由其中分别形成参考电压或接地轨迹和信号的第二和第三导电层240b和240c而划定该圆锥部分的界限。由其中形成信号轨迹的第三导电层240c和其中还形成参考电压或接地轨迹的最近的导电层240d而划定第二圆柱部分的界限。如图所示，圆锥部分的较小直径对应于第一圆柱部分的直径，而第二圆柱部分的直径对应于圆锥部分的较大直径。通过接触与焊盘205对应的区域而确定第一圆柱部分的直径，其值至少等于与焊盘205对应的该接触区域的正交投影。如图所示，圆锥部分角包含在30°和60°之间，并最好等于45°。由导电材料制成的浮动盘260形成在导电层240b中，以创建图2b和2c所示的参考面230和浮动盘260之间的由绝缘材料制成的环孔255。在优选实施例中，环孔255的剖面集中在与焊盘205对应的接触区域的正交投影上。浮动盘260不与任何信号、参考电压或接地轨迹相连。例如考虑与焊盘205对应的接触区域具有等于600μm的直径，然而该开口的直径必须至少等于600μm，较大的直径可改善信号屏蔽。发明人已注意到，在这样的情况下，开口直径等于800μm而浮动盘直径等于600μm是提供有效信号屏蔽的数值，同时优化上述专用表面区域和物理参数，例如整个封装表面区域的平坦和介电材料与介电材料的粘贴。
同样考虑芯片载体是否具有不同的结构，例如在共面轨迹之间安排的两个不同的信号轨迹，芯片载体是否包括不同数目的导电层，在其中形成信号轨迹的第一层的顶部是否还提供接地平面，接地平面和电源平面是否包括两个或多个截然不同的轨迹的每一个，接触区域是否有不同尺寸等。
更一般地，本发明提供了一种用于传输高频信号的电子器件载体，包括具有彼此绝缘的多个导电层的电路(circuitised)衬底；按照从其中形成多个信号轨迹的导电层的第一层的顺序安排导电层，每一个信号轨迹结束于用于传输高频信号的接触区域。该电子器件载体还包括可与参考电压或地连接的参考结构，用于屏蔽所述信号轨迹；该参考结构具有在与该第一导电层相邻的导电层的第二层中形成的至少一个参考轨迹和在不同于第一和第二导电层的导电层之一中形成的至少一个别的参考轨迹；通过插入与任何信号、参考电压或接地轨迹不相连的浮动导电轨迹，将至少除了对应于相关接触区域即焊盘的正交投影的区域以外的每一信号轨迹的一部分在平面图中叠加到对应参考轨迹上，和将与相关于每一信号轨迹的接触区域即焊盘的正交投影对应的区域的至少一部分在平面图中叠加到对应的其它参考轨迹上。
所设计的方案大大降低了在信号轨迹和互连球区域中的参考面之间形成的寄生电容的电容(与它们的距离成反比)。
本发明的方案保持沿着该传输线传播的电磁波的好的完整性。该电子器件载体的提出的设计尽可能小地影响芯片的性能，使得整个电子系统能在与该芯片提供的工作频率非常靠近的频率上工作。
而且，即使信号轨迹的尺寸(也即信号轨迹和相邻参考面之间的介电层的宽度)降低，根据本发明的方案仍将传输线的带宽保持为令人满意的值。所以，该结构可能生产非常小尺寸的电子系统，但同时具有高性能。
考虑制造和机械方面，本发明的技术方案适于传输高频信号的平坦电子器件载体，并且由于用电子器件载体多层结构中的层之间的改善的粘贴来最小化相邻介电材料层的接触区域，其允许匹配其上连接的电子器件载体、电子器件和电子系统之间的系数膨胀。
具体参考图3a，其中绘出了公知电子模块的眼图，单一参考面与信号轨迹相邻，也与各互连球重叠。该图示出了从传输线路接收、作为时钟信号的相位的函数的信号s(t)的值(V)；由于传输线路中的不连续，该眼图完全闭合。相反，图3b中示出的包含本发明的芯片载体的电子模块的眼图打开很大，使得易于从由于背景噪声的信号基线的移动辨别信号的实际开关转换。结果，即使具有电源电压的降低的电平，该电子模块仍可工作在高频。
换言之，在公知电子模块中，由在焊盘和下面的参考面之间形成的寄生电容定义的低通滤波器具有很低的截止频率；所以，如图4a所示，几乎不传输信号s(f)(以频域表示)的第一谐波f0。另一方面，如图4b所示，本发明的技术方案将传输线路的带宽增加至该信号的第三谐波3f0。
尽管已参考从芯片载体到印刷电路板传输高频信号的芯片载体而描述了本发明，但本发明可有效应用到芯片载体中，以降低与C4焊盘或用于引线接合连接的焊盘接近的传输线路中的不连续的影响。
由于信号、参考电压和接地轨迹之间的介电层厚度与轨迹宽度的比率经常足够大，所以在印刷电路板中起作用的寄生电容一般是可忽略的。因此，即使可无缺陷地实现，但除非考虑成本，一般不需要在印刷电路板中实现本发明。然而，由于小型化趋势，芯片载体的上述低通滤波器效果可能出现在印刷电路板中，例如基于特氟纶(Teflon)的印刷电路板。在这种情况下，通过在印刷电路板中本身中实现本发明，可降低寄生电容的影响。
自然地，为了满足本地和特殊需求，本领域普通技术人员可在以下权利要求限定的本发明的保护范围内对上述技术方案进行许多修改和替换。

Claims (15)

1.一种适于传输高频信号的电子器件载体(110)，包括具有彼此绝缘的多个导电层(240a到240g)的电路衬底，按照从其中形成多个信号轨迹(200)的导电层的第一层(240a)的顺序安排所述导电层，每一个信号轨迹结束于接触区域(205)，用于传输高频信号；和可与参考电压或接地连接的参考结构(215a，215b，230)，用于屏蔽所述信号轨迹，
其特征在于：
该参考结构包括在与该第一导电层相邻的导电层的第二层(240b)中形成的至少一个参考轨迹(230)，和在不同于第一和第二导电层的导电层之一(240d)中形成的至少一个另外的参考轨迹，通过插入与任何信号、参考电压或接地轨迹不相连的浮动导电轨迹，将至少除了对应于相关接触区域的正交投影的区域以外的每一信号轨迹的一部分在平面图中叠加到对应参考轨迹上，和将与相关于每一信号轨迹的接触区域的正交投影对应的区域的至少一部分在平面图中叠加到对应的其它参考轨迹上。
2.根据权利要求1的电子器件载体(110)，其中在该第二导电层(240b)和其中形成所述另外的参考轨迹的所述一个导电层(240d)之间安排导电层的至少一个中间层(240c)，在该至少一个中间导电层中形成多个轨迹，所述轨迹在平面图中安排于阴影区域外部，其中通过将与第二导电层(240b)相邻的导电层的第三层(240c)与从该至少一个参考轨迹(230)的轮廓向该第三导电层延伸的表面相交，并与该至少一个参考轨迹形成在30°和60°之间范围内的角度，而限定所述阴影区域。
3.根据权利要求2的电子器件载体(110)，其中所述角度为45°。
4.根据权利要求1到3的任何一个的电子器件载体(110)，其中该参考结构(215a，215b，230)还包括在该第一导电层(240a)中形成的多个成对的共面轨迹(215a，215b)，每一信号轨迹(200)安排于对应的共面轨迹对之间。
5.根据权利要求4的电子器件载体(110)，还包括多个转接孔(250)，每一转接孔将共面轨迹(215a)连接到对应参考轨迹(230)和对应的另外参考轨迹。
6.根据权利要求1到3的任何一个的电子器件载体，其中所述电子器件是芯片(105)。
7.根据权利要求4的电子器件载体，其中所述电子器件是芯片(105)。
8.根据权利要求5的电子器件载体，其中所述电子器件是芯片(105)。
9.根据权利要求6的电子器件载体(110)，还包括多个互连球(210，225)，每一个安排于对应接触区域(205，220)上。
10.根据权利要求1到3的任何一个的电子器件载体，包含印刷电路板。
11.根据权利要求4的任何一个的电子器件载体，包含印刷电路板。
12.根据权利要求5的任何一个的电子器件载体，包含印刷电路板。
13.一种高频电子器件(100)，包括根据权利要求1的电子器件载体(110)；具有多个端子的半导体材料的芯片(105)，该芯片安装于该载体上；和用于将该芯片的每一端子与该对应信号轨迹电连接的部件。
14.根据权利要求13的电子器件(100)，其中该芯片(105)的端子通过互连球(115)与该对应信号轨迹相连。
15.根据权利要求13的电子器件(100)，其中该芯片(105)的端子引线接合到该对应信号轨迹。
CNB028201981A 2001-11-13 2002-10-25 适于传输高频信号的电子器件载体 Expired - Fee Related CN1314114C (zh)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3580803B2 (ja) * 2002-08-09 2004-10-27 沖電気工業株式会社 半導体装置
JP2004214657A (ja) 2003-01-07 2004-07-29 Internatl Business Mach Corp <Ibm> プリント回路板製造用水溶性保護ペースト
JP4957013B2 (ja) * 2006-02-24 2012-06-20 凸版印刷株式会社 半導体素子搭載用基板
US20070200234A1 (en) * 2006-02-28 2007-08-30 Texas Instruments Incorporated Flip-Chip Device Having Underfill in Controlled Gap
US20080093726A1 (en) * 2006-10-23 2008-04-24 Francesco Preda Continuously Referencing Signals over Multiple Layers in Laminate Packages
EP2493273A4 (en) * 2009-10-23 2013-10-16 Fujikura Ltd MOUNTING SUPPORT AND ASSEMBLY PROCESS FOR ONE DEVICE
US8325459B2 (en) * 2009-12-08 2012-12-04 International Business Machines Corporation Channel performance of electrical lines
US8890302B2 (en) 2012-06-29 2014-11-18 Intel Corporation Hybrid package transmission line circuits
US9373600B2 (en) * 2014-01-27 2016-06-21 Semiconductor Components Industries, Llc Package substrate structure for enhanced signal transmission and method
GB2552983B (en) * 2016-08-17 2021-04-07 Ge Aviat Systems Ltd Method and apparatus for detecting an electrical fault in a printed circuit board
KR20200100967A (ko) * 2019-02-19 2020-08-27 주식회사 엘지화학 Ic 칩 및 이를 이용한 회로 시스템
KR20200145589A (ko) 2019-06-22 2020-12-30 김민태 살균 기능을 더한 렌즈 세척기
WO2023286475A1 (ja) * 2021-07-13 2023-01-19 株式会社村田製作所 回路基板及び電子部品

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260773A (ja) * 1985-09-09 1987-03-17 Howa Mach Ltd ボビン下降搬送装置
US5336855A (en) * 1991-01-07 1994-08-09 U.S. Philips Corporation Multilayer printed circuit board, in particular, for high-frequency operation
US5691568A (en) * 1996-05-31 1997-11-25 Lsi Logic Corporation Wire bondable package design with maxium electrical performance and minimum number of layers
EP0834922A2 (en) * 1993-03-24 1998-04-08 Intergraph Corporation Improved multi-layer packaging
US5907265A (en) * 1996-09-13 1999-05-25 Matsushita Electric Industrial Co., Ltd. High-frequency circuit board trace crossing and electronic component therefor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260773A (ja) * 1993-03-03 1994-09-16 Oki Electric Ind Co Ltd 高速信号伝送用回路基板のパッド部の構造
JPH118445A (ja) * 1997-06-18 1999-01-12 Toyota Motor Corp 回路基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260773A (ja) * 1985-09-09 1987-03-17 Howa Mach Ltd ボビン下降搬送装置
US5336855A (en) * 1991-01-07 1994-08-09 U.S. Philips Corporation Multilayer printed circuit board, in particular, for high-frequency operation
EP0834922A2 (en) * 1993-03-24 1998-04-08 Intergraph Corporation Improved multi-layer packaging
US5691568A (en) * 1996-05-31 1997-11-25 Lsi Logic Corporation Wire bondable package design with maxium electrical performance and minimum number of layers
US5907265A (en) * 1996-09-13 1999-05-25 Matsushita Electric Industrial Co., Ltd. High-frequency circuit board trace crossing and electronic component therefor

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