CN1314098C - 半导体器件中的高频信号隔离 - Google Patents

半导体器件中的高频信号隔离 Download PDF

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CN1314098C
CN1314098C CNB028241436A CN02824143A CN1314098C CN 1314098 C CN1314098 C CN 1314098C CN B028241436 A CNB028241436 A CN B028241436A CN 02824143 A CN02824143 A CN 02824143A CN 1314098 C CN1314098 C CN 1314098C
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杨笃
苏曼·K.·班纳吉
雷纳·托玛
艾伦·杜瓦利特
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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Abstract

一种半导体器件(20)包括由一个埋置的n型阱(25)和一个n型阱环(24)在一个衬底(21)中形成的一个被隔离的p型阱(22)。该n型阱环(24)从所述半导体器件(20)的一个表面延伸到所述埋置的n型阱(25)。所述被隔离的p型阱(22)包括多个从所述半导体器件(20)的所述表面延伸到所述被隔离的p型阱(22)中并与所述埋置的n型阱(25)接触的n型阱栓(27)。所述多个n型阱栓(27)降低n型阱电阻，从而针对高频信号提供更好的噪声隔离。

Description

半导体器件中的高频信号隔离
技术领域
本发明总体上涉及半导体器件，尤其涉及半导体器件中的高频信号隔离。
背景技术
为了降低集成电路设计的成本，希望在单个集成电路上包括尽可能多的功能。例如，在低成本无线通信系统中，希望在作为数字逻辑电路的同一个集成电路上包括射频电路。但是，数字逻辑电路产生的噪声会被注入敏感的RF电路模块比如锁相环(PLL)和低噪放大器电路中。从概念上，理想的法拉第笼可屏蔽外部电磁干扰，提供有效的信号隔离。在集成电路中，掺杂(注入)形成的阱(implanted well)用来降低噪声效应并提供信号隔离。在用p型衬底进行的CMOS双阱工艺中，n型阱和p型衬底之间的pn结对PMOS提供了某种程度的信号隔离。NMOS的信号隔离是这样实现的：用深n+掺杂(注入)(deep n+implant，DNW)和n型阱一道形成被隔离的p型阱(IPW)穴(pocket)，这有时候被称为三阱工艺。用来在集成电路中近似形成法拉第笼的掺杂阱降低了噪声效应。但是，掺杂阱的使用在高RF频率不能提供充分的信号隔离。
图1图示了现有技术的半导体器件10的顶视图，图2图示了图1的现有技术半导体器件10的剖面图。半导体器件10具有一个p型衬底18。深n型阱掺杂体16与一个n型阱环15一道形成被隔离的p型阱穴12。在被隔离的p型阱12的表面掺杂有多个p+型连阱(well tie)14。电子线路被建造在被隔离的p型阱的表面中(未图示)。被隔离的p型阱12用来将在阱中实现的电路与在该阱外部实现的电路隔离开。但是，深n型阱掺杂体16具有比较高的电阻，这对于射频频段的信号隔离是不利的。
附图说明
图1图示了现有技术的半导体器件的顶视图；
图2图示了图1的现有技术半导体器件的剖面图；
图3是本发明的半导体器件的顶视图；
图4是图3所示半导体器件的剖面图。
具体实施方式
总体来说，本发明提供一种半导体器件20，其具有一个衬底21、一个埋置的n型阱25和一个n型阱环24。所述n型阱环24从所述半导体器件20的表面延伸到所述埋置的n型阱25。所述n型阱环24和埋置的n型阱25形成一个被隔离的p型阱22。该被隔离的p型阱22包括多个从表面伸入被隔离的p型阱22中并接触所述埋置的n型阱25的n型阱栓27。所述多个n型阱栓27降低了n型阱电阻，以针对高频信号提供更好的隔离。
图3图示了本发明的半导体器件20的一部分的顶视图。图4图示了图3所示的半导体器件沿着4-4线的剖面图。现在参考图3和图4，半导体器件20包括一个衬底21、深n型阱25、复合阱环23以及复合连阱(composite well tie)34和44。深n型阱25和n型阱环24形成一个被隔离的p型阱22。复合阱环23包括n型阱环24、阱间(inter-well)STI(浅沟槽隔离，Shallow Trench Isolation)26、阱内STI30、n+有源区(激活区，active)29和p+有源区28。复合连阱34包括n型阱栓27、p+有源区36、阱间STI38、n+有源区40以及阱内STI42。类似于复合连阱34的多个复合连阱在整个被隔离的p型阱22上分布。但是，为了说明的目的，在图3和图4中只图示了一个另外的复合连阱44。
首先在衬底21中掺杂形成深n型阱25。然后，在深n阱25上方掺杂形成n阱环24从而构成被隔离的p型阱22。在n型阱24和被隔离的p型阱22上形成阱间STI26、阱内STI30、n+有源区29和p+有源区28。复合连阱34和44与复合n阱环23用相同的掩模同时形成。n型阱栓27与n型阱环24同时形成。N型阱栓27的掺杂浓度的范围约为1e17原子每立方厘米到1e19原子每立方厘米，所述埋置的n型阱25的掺杂浓度的范围约为1e17到5e19原子每立方厘米。然后在n型阱栓27上方形成p+有源区36、阱间STI38、n+有源区40以及阱内STI42。所述p+有源区36构成围绕所述n型阱栓的保护环，用以消除对工艺敏感的泄漏，使得复合n型连阱更加稳定可靠。
由于欧姆并联电阻定理，被隔离的p型阱中有更多的n型连阱将形成更低的电阻。但是，增加的n型连阱降低电阻的代价是集成电路的表面积增加。在图示的实施例中，复合n型连阱相互间等间距设置，距离小于约50微米。n型连阱间距的降低，从而n型连阱数目的增加，形成更好的信号隔离效果。所述多个n型阱栓34中的每一个的长度的范围约为0.5微米到1.0微米，宽度的范围约为0.5微米到1.0微米。在其它的实施例中，所述复合n型连阱的间隔可以进一步大于50微米，并且可以非均匀设置，以适应电路布局或者其它考虑。另外，n型阱栓可以具有不同的长度和宽度。例如，在一个实施例中，n型阱栓可以为形成一个条的矩形。
复合连阱34和44用来与深n型阱25接触，通过提供穿过被隔离的p型阱22的多个并行的导电路径，降低埋置的n型阱的深n型阱电阻。同样，复合连阱34和44可以用与n型阱环24相同的掩模在被隔离的p型阱22的内部掺杂形成。在掺杂形成p型阱后，形成n+有源区(激活区，activeregion)40和p+有源区36，以形成与所述阱的欧姆接触。在图示的实施例中，复合阱环23和复合连阱34和44具有类似的结构，以实现优化的信号隔离。随着频率的增加，集总阱电阻决定信号隔离量。
集总阱电阻可以由下式表示：
Rw＝Rnw*Rpw/(Rnw+Rpw)，
其中Rnw为深n型阱电阻，Rpw是被隔离p型阱电阻。在高频时，集总阱电阻用作旁路电阻。使Rw最小化会改善高达约10GHz的频率的噪声隔离。
尽管上面结合具体实施例对本发明进行了描述，本领域的普通技术人员会很容易作出一些变化和改进。因此，本发明包括落在所附权利要求范围内的所有这样的变化和修改。

Claims (5)

1.一种半导体器件，包括：
p型衬底；
在该p型衬底中的被隔离的p型阱，该被隔离的p型阱由n型阱环和埋置的n型阱限定而成，其中，n型阱环和埋置的n型阱将该被隔离的p型阱与所述p型衬底电隔离开；
多个在所述被隔离的p型阱中的复合连阱，每一个复合连阱包括：
延伸到所述被隔离的p型阱中的p型部分；和
延伸穿过所述被隔离的p型阱的深度并与所述埋置的n型阱接触的n型部分，所述p型部分和所述n型部分形成穿过所述被隔离的p型阱的并行导电路径。
2.如权利要求1所述的半导体器件，其中，每一个复合连阱还包括：
在所述p型部分和n型部分之间的隔离部分，其中，所述n型部分与所述p型部分被电隔离。
3.如权利要求2所述的半导体器件，其中，每一个复合连阱还包括：
围绕所述p型部分的阱内浅沟槽隔离部分。
4.如权利要求1所述的半导体器件，其中，所述n型阱环包括沟槽隔离部分和p+保护环。
5.一种半导体器件，包括：
由n型阱环和埋置的n型阱限定的被隔离的p型阱，其中，所述n型阱环沿着所述被隔离的p型阱的深度延伸并与所述埋置的n型阱电接触；
所述被隔离的p型阱中的多个p型连阱；和
所述被隔离的p型阱中的多个n型阱栓，其中，所述多个n型阱栓在整个所述被隔离的p型阱中间隔分布，并与所述埋置的n型阱电接触，并且其中，所述多个p型连阱中的每一个在所述多个n型阱栓中的相应阱栓的周围形成保护环。
CNB028241436A 2001-11-02 2002-10-10 半导体器件中的高频信号隔离 Expired - Fee Related CN1314098C (zh)

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US10/003,535 US6563181B1 (en) 2001-11-02 2001-11-02 High frequency signal isolation in a semiconductor device

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WO2003041161A3 (en) 2003-11-13
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