CN1610966A - 半导体器件中的高频信号隔离 - Google Patents

半导体器件中的高频信号隔离 Download PDF

Info

Publication number
CN1610966A
CN1610966A CNA028241436A CN02824143A CN1610966A CN 1610966 A CN1610966 A CN 1610966A CN A028241436 A CNA028241436 A CN A028241436A CN 02824143 A CN02824143 A CN 02824143A CN 1610966 A CN1610966 A CN 1610966A
Authority
CN
China
Prior art keywords
well
type
isolated
semiconductor device
type well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA028241436A
Other languages
English (en)
Other versions
CN1314098C (zh
Inventor
杨笃
苏曼·K.·班纳吉
雷纳·托玛
艾伦·杜瓦利特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1610966A publication Critical patent/CN1610966A/zh
Application granted granted Critical
Publication of CN1314098C publication Critical patent/CN1314098C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一种半导体器件(20)包括由一个埋置的n型阱(25)和一个n型阱环(24)在一个衬底(21)中形成的一个被隔离的p型阱(22)。该n型阱环(24)从所述半导体器件(20)的一个表面延伸到所述埋置的n型阱(25)。所述被隔离的p型阱(22)包括多个从所述半导体器件(20)的所述表面延伸到所述被隔离的p型阱(22)中并与所述埋置的n型阱(25)接触的n型阱栓(27)。所述多个n型阱栓(27)降低n型阱电阻，从而针对高频信号提供更好的噪声隔离。

Description

半导体器件中的高频信号隔离
技术领域
本发明总体上涉及半导体器件，尤其涉及半导体器件中的高频信号隔离。
背景技术
为了降低集成电路设计的成本，希望在单个集成电路上包括尽可能多的功能。例如，在低成本无线通信系统中，希望在作为数字逻辑电路的同一个集成电路上包括射频电路。但是，数字逻辑电路产生的噪声会被注入敏感的RF电路模块比如锁相环(PLL)和低噪放大器电路中。从概念上，理想的法拉第笼可屏蔽外部电磁干扰，提供有效的信号隔离。在集成电路中，掺杂(注入)形成的阱(implanted well)用来降低噪声效应并提供信号隔离。在用p型衬底进行的CMOS双阱工艺中，n型阱和p型衬底之间的pn结对PMOS提供了某种程度的信号隔离。NMOS的信号隔离是这样实现的：用深n+掺杂(注入)(deep n+implant，DNW)和n型阱一道形成被隔离的p型阱(IPW)穴(pocket)，这有时候被称为三阱工艺。用来在集成电路中近似形成法拉第笼的掺杂阱降低了噪声效应。但是，掺杂阱的使用在高RF频率不能提供充分的信号隔离。
图1图示了现有技术的半导体器件10的顶视图，图2图示了图1的现有技术半导体器件10的剖面图。半导体器件10具有一个p型衬底。深n型阱掺杂体16与一个n型阱环15一道形成被隔离的p型阱穴12。在被隔离的p型阱12的表面掺杂有多个p+型连阱(well tie)14。电子线路被建造在被隔离的p型阱的表面中(未图示)。被隔离的p型阱12用来将在阱中实现的电路与在该阱外部实现的电路隔离开。但是，深n型阱掺杂体16具有比较高的电阻，这对于射频频段的信号隔离是不利的。
附图说明
图1图示了现有技术的半导体器件的顶视图；
图2图示了图1的现有技术半导体器件的剖面图；
图3是本发明的半导体器件的顶视图；
图4是图3所示半导体器件的剖面图。
具体实施方式
总体来说，本发明提供一种半导体器件20，其具有一个衬底21、一个埋置的n型阱25和一个n型阱环24。所述n型阱环24从所述半导体器件20的表面延伸到所述埋置的n型阱25。所述n型阱环24和埋置的n型阱25形成一个被隔离的p型阱22。该被隔离的p型阱22包括多个从表面伸入被隔离的p型阱22中并接触所述埋置的n型阱25的n型阱栓27。所述多个n型阱栓27降低了n型阱电阻，以针对高频信号提供更好的隔离。
图3图示了本发明的半导体器件20的一部分的顶视图。图4图示了图3所示的半导体器件沿着4-4线的剖面图。现在参考图3和图4，半导体器件20包括一个衬底21、深n型阱25、复合阱环23以及复合连阱(composite well tie)34和44。深n型阱25和n型阱环24形成一个被隔离的p型阱22。复合阱环23包括n型阱环24、阱间(inter-well)STI(浅沟槽隔离，Shallow Trench Isolation)26、阱内STI30、n+有源区(激活区，active)29和p+有源区28。复合连阱34包括n型阱栓27、p+有源区36、阱间STI38、n+有源区40以及阱内STI42。类似于复合连阱34的多个复合连阱在整个被隔离的p型阱22上分布。但是，为了说明的目的，在图3和图4中只图示了一个另外的复合连阱44。
首先在衬底21中掺杂形成深n型阱25。然后，在深n阱25上方掺杂形成n阱环24从而构成被隔离的p型阱22。在n型阱24和被隔离的p型阱22上形成阱间STI26、阱内STI30、n+有源区29和p+有源区28。复合连阱34和44与复合n阱环23用相同的掩模同时形成。n型阱栓27与n型阱环24同时形成。N型阱栓27的掺杂浓度的范围约为1e17原子每立方厘米到1e19原子每立方厘米，所述埋置的n型阱25的掺杂浓度的范围约为1e17到5e19原子每立方厘米。然后在n型阱栓27上方形成p+有源区36、阱间STI38、n+有源区40以及阱内STI42。所述p+有源区36构成围绕所述n型阱栓的保护环，用以消除对工艺敏感的泄漏，使得复合n型连阱更加有鲁棒性。
由于欧姆并联电阻定理，被隔离的p型阱中有更多的n型连阱将形成更低的电阻。但是，增加的n型连阱降低电阻的代价是集成电路的表面积增加。在图示的实施例中，复合n型连阱相互间等间距设置，距离小于约50微米。n型连阱间距的降低，从而n型连阱数目的增加，形成更好的信号隔离效果。所述多个n型阱栓34中的每一个的长度的范围约为0.5微米到1.0微米，宽度的范围约为0.5微米到1.0微米。在其它的实施例中，所述复合n型连阱的间隔可以进一步大于50微米，并且可以非均匀设置，以适应电路布局或者其它考虑。另外，n型阱栓可以具有不同的长度和宽度。例如，在一个实施例中，n型阱栓可以为形成一个条的矩形。
复合连阱34和44用来与深n型阱25接触，通过提供穿过被隔离的p型阱22的多个并行的导电路径，降低埋置的n型阱的深n型阱电阻。同样，复合连阱34和44可以用与n型阱环24相同的掩模在被隔离的p型阱22的内部掺杂形成。在掺杂形成p型阱后，形成n+有源区(激活区，activeregion)40和p+有源区36，以形成与所述阱的欧姆接触。在图示的实施例中，复合阱环23和复合连阱34和44具有类似的结构，以实现优化的信号隔离。随着频率的增加，集总阱电阻决定信号隔离量。
集总阱电阻可以由下式表示：
Rw＝Rnw*Rpw/(Rnw+Rpw)，
其中Rnw为深n型阱电阻，Rpw是被隔离p型阱电阻。在高频时，集总阱电阻用作旁路电阻。使Rw最小化会改善高达约10GHz的频率的噪声隔离。
尽管上面结合具体实施例对本发明进行了描述，本领域的普通技术人员会很容易作出一些变化和改进。因此，本发明包括落在所附权利要求范围内的所有这样的变化和修改。

Claims (10)

1.一种半导体器件，包括：
一个衬底；
一个在该衬底中的埋置的n型阱；以及
一个从该半导体器件的表面延伸到所述埋置的n型阱并与该埋置的n型阱接触的n型阱环，
其中，
该n型阱环和所述埋置的n型阱形成一个被隔离的p型阱，该被隔离的p型阱包括：
多个从所述表面延伸到所述被隔离的p型阱中并与所述埋置的n型阱接触的n型阱栓。
2.如权利要求1所述的半导体器件，其中，所述被隔离的p型阱包括：
多个复合连阱，每一个复合连阱包括一个n+有源区，所述n+有源区形成于所述多个n型阱栓中的每一个的顶部上，与所示多个n型阱栓电接触。
3.如权利要求2所述的半导体器件，还包括一个环绕所述多个n型阱栓中的每一个的顶部的p+保护环。
4.一种半导体器件，包括：
一个p型衬底；
一个在该p型衬底中的被隔离的p型阱，该被隔离的p型阱由一个n型阱环和一个埋置的n型阱限定而成，其中，n型阱环和埋置的n型阱将该被隔离的p型阱与所述p型衬底电隔离开；
多个在所述被隔离的p型阱中的复合连阱，每一个复合连阱包括：
一个延伸到所述被隔离的p型阱中的p型部分；和
一个延伸穿过所述被隔离的p型阱的深度并与所述埋置的n型阱接触的n型部分。
5.如权利要求4所述的半导体器件，其中，每一个复合连阱还包括：
在所述p型部分和n型部分之间的一个隔离部分，其中，所述n型部分与所述p型部分被电隔离。
6.如权利要求5所述的半导体器件，其中，每一个复合连阱还包括：
一个围绕所述p型部分的阱内浅沟槽隔离部分。
7.如权利要求4所述的半导体器件，其中，至少部分所述多个复合连阱共用一个n型部分，该n型部分从一个复合连阱延伸到所述部分复合连阱中的另一个复合连阱。
8.如权利要求4所述的半导体器件，其中，所述被隔离的p型阱还包括一个有源器件，该有源器件具有一个体电极(bulk electrode)，该体电极连接到所述多个复合连阱中的至少一个的所述p型部分。
9.如权利要求4所述的半导体器件，其中，所述n型阱环包括一个沟槽隔离部分和一个p+保护环。
10.一种半导体器件，包括：
由一个n型阱环和一个埋置的n型阱限定的一个被隔离的p型阱，其中，所述n型阱环沿着所述被隔离的p型阱的深度延伸并与所述埋置的n型阱电接触；
所述被隔离的p型阱中的多个p型连阱；和
多个n型阱栓，其中，所述多个n型阱栓中的每一个按照预定的间隔在相应的p型连阱内，并延伸穿过所述被隔离的p型阱的深度，与所述埋置的n型阱电接触。
CNB028241436A 2001-11-02 2002-10-10 半导体器件中的高频信号隔离 Expired - Fee Related CN1314098C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/003,535 US6563181B1 (en) 2001-11-02 2001-11-02 High frequency signal isolation in a semiconductor device
US10/003,535 2001-11-02

Publications (2)

Publication Number Publication Date
CN1610966A true CN1610966A (zh) 2005-04-27
CN1314098C CN1314098C (zh) 2007-05-02

Family

ID=21706319

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028241436A Expired - Fee Related CN1314098C (zh) 2001-11-02 2002-10-10 半导体器件中的高频信号隔离

Country Status (7)

Country Link
US (1) US6563181B1 (zh)
EP (1) EP1497858B1 (zh)
JP (1) JP4579539B2 (zh)
KR (1) KR100909346B1 (zh)
CN (1) CN1314098C (zh)
TW (1) TW561550B (zh)
WO (1) WO2003041161A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635298A (zh) * 2009-06-10 2010-01-27 北京中星微电子有限公司 平面工艺的三维集成电路
CN104332409A (zh) * 2014-11-05 2015-02-04 北京大学 基于深n阱工艺隔离隧穿场效应晶体管的制备方法

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6710424B2 (en) 2001-09-21 2004-03-23 Airip RF chipset architecture
US20030234438A1 (en) * 2002-06-24 2003-12-25 Motorola, Inc. Integrated circuit structure for mixed-signal RF applications and circuits
US7834421B2 (en) * 2002-08-14 2010-11-16 Advanced Analogic Technologies, Inc. Isolated diode
US7667268B2 (en) 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
US7825488B2 (en) * 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US8513087B2 (en) * 2002-08-14 2013-08-20 Advanced Analogic Technologies, Incorporated Processes for forming isolation structures for integrated circuit devices
US7956391B2 (en) * 2002-08-14 2011-06-07 Advanced Analogic Technologies, Inc. Isolated junction field-effect transistor
US8089129B2 (en) * 2002-08-14 2012-01-03 Advanced Analogic Technologies, Inc. Isolated CMOS transistors
US6744112B2 (en) * 2002-10-01 2004-06-01 International Business Machines Corporation Multiple chip guard rings for integrated circuit and chip guard ring interconnect
US6891207B2 (en) * 2003-01-09 2005-05-10 International Business Machines Corporation Electrostatic discharge protection networks for triple well semiconductor devices
US7429891B2 (en) * 2003-02-14 2008-09-30 Broadcom Corporation Method and system for low noise amplifier (LNA) gain adjustment through narrowband received signal strength indicator (NRSSI)
US7851860B2 (en) * 2004-03-26 2010-12-14 Honeywell International Inc. Techniques to reduce substrate cross talk on mixed signal and RF circuit design
US7138686B1 (en) 2005-05-31 2006-11-21 Freescale Semiconductor, Inc. Integrated circuit with improved signal noise isolation and method for improving signal noise isolation
US7608913B2 (en) 2006-02-23 2009-10-27 Freescale Semiconductor, Inc. Noise isolation between circuit blocks in an integrated circuit chip
US7881679B1 (en) * 2007-03-14 2011-02-01 Rf Micro Devices, Inc. Method and apparatus for integrating power amplifiers with phase locked loop in a single chip transceiver
US8138570B2 (en) * 2007-03-28 2012-03-20 Advanced Analogic Technologies, Inc. Isolated junction field-effect transistor
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US8227902B2 (en) * 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US8546953B2 (en) 2011-12-13 2013-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
US8921978B2 (en) * 2012-01-10 2014-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices
CN110880502B (zh) * 2018-09-05 2022-10-14 无锡华润上华科技有限公司 半导体结构及电机驱动装置
JP7176676B2 (ja) * 2018-11-16 2022-11-22 ミネベアミツミ株式会社 検出装置
KR20220167549A (ko) 2021-06-14 2022-12-21 삼성전자주식회사 웰 영역을 포함하는 반도체 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56120141A (en) * 1980-02-27 1981-09-21 Toshiba Corp Semiconductor device
JPS62177959A (ja) * 1986-01-31 1987-08-04 Nec Corp 半導体装置
JPH0353561A (ja) * 1989-07-21 1991-03-07 Fujitsu Ltd 半導体集積回路装置
US5027183A (en) * 1990-04-20 1991-06-25 International Business Machines Isolated semiconductor macro circuit
JPH04147668A (ja) * 1990-10-11 1992-05-21 Hitachi Ltd 半導体集積回路装置とその製造方法
JP2976912B2 (ja) * 1997-01-13 1999-11-10 日本電気株式会社 半導体記憶装置
JP2000021972A (ja) * 1998-07-03 2000-01-21 Fujitsu Ltd 半導体装置
US6349067B1 (en) * 2001-01-30 2002-02-19 International Business Machines Corporation System and method for preventing noise cross contamination between embedded DRAM and system chip

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635298A (zh) * 2009-06-10 2010-01-27 北京中星微电子有限公司 平面工艺的三维集成电路
WO2010142240A1 (zh) * 2009-06-10 2010-12-16 北京中星微电子有限公司 平面工艺的三维集成电路
CN101635298B (zh) * 2009-06-10 2014-12-31 北京中星微电子有限公司 平面工艺的三维集成电路
CN104332409A (zh) * 2014-11-05 2015-02-04 北京大学 基于深n阱工艺隔离隧穿场效应晶体管的制备方法
CN104332409B (zh) * 2014-11-05 2017-09-19 北京大学 基于深n阱工艺隔离隧穿场效应晶体管的制备方法

Also Published As

Publication number Publication date
WO2003041161A2 (en) 2003-05-15
TW561550B (en) 2003-11-11
KR20040053273A (ko) 2004-06-23
US20030085432A1 (en) 2003-05-08
US6563181B1 (en) 2003-05-13
WO2003041161A3 (en) 2003-11-13
KR100909346B1 (ko) 2009-07-24
JP2005536867A (ja) 2005-12-02
EP1497858B1 (en) 2011-09-28
CN1314098C (zh) 2007-05-02
EP1497858A2 (en) 2005-01-19
JP4579539B2 (ja) 2010-11-10

Similar Documents

Publication Publication Date Title
CN1610966A (zh) 半导体器件中的高频信号隔离
JP2005536867A5 (zh)
US8513782B2 (en) Shielding device
US7511346B2 (en) Design of high-frequency substrate noise isolation in BiCMOS technology
US8049284B2 (en) Bipolar device compatible with CMOS process technology
US20100102414A1 (en) Semiconductor device
TW200427059A (en) Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
US9048110B2 (en) Noise isolation between circuit blocks in an integrated circuit chip
JP2003133434A (ja) 半導体集積回路
US6740953B2 (en) High frequency integrated devices
US20060125014A1 (en) Diode with low junction capacitance
CN113937098A (zh) 用于快速充电管理系统的静电防护芯片及其制备方法
US7902013B1 (en) Method of forming a semiconductor die with reduced RF attenuation
JP2006313861A (ja) 半導体装置
EP4053889A1 (en) Isolated wells for improved noise performance
US20050045992A1 (en) Bipolar/thin film SOI CMOS structure and method of making same
KR100707594B1 (ko) 반도체 소자의 싸이리스터형 격리 구조
KR100281106B1 (ko) 이에스디보호회로및그제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: FISICAL SEMICONDUCTOR INC.

Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP.

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: FREESCALE SEMICONDUCTOR, Inc.

Address before: Texas in the United States

Patentee before: FreeScale Semiconductor

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CP01 Change in the name or title of a patent holder
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070502

Termination date: 20181010

CF01 Termination of patent right due to non-payment of annual fee