CN1302538C - Cmos阱结构及其形成方法 - Google Patents

Cmos阱结构及其形成方法 Download PDF

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CN1302538C
CN1302538C CNB2004100923709A CN200410092370A CN1302538C CN 1302538 C CN1302538 C CN 1302538C CN B2004100923709 A CNB2004100923709 A CN B2004100923709A CN 200410092370 A CN200410092370 A CN 200410092370A CN 1302538 C CN1302538 C CN 1302538C
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CN1667816A (zh
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拉吉夫·V.·约施
许履尘
特伦斯·B·胡克
沃纳·劳斯
维尔弗雷德·E.·赫恩斯
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

一种用于形成CMOS阱结构的方法，包括：在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱中的每一个形成在第一掩模的各开口中。在第一导电类型的阱的每一个上形成盖，并去除第一掩模。在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件。形成多个第二导电类型的阱，多个第二导电类型的阱的每一个形成在各个第一导电类型的阱之间。在第一导电类型的阱和第二导电类型的阱之间形成多个浅沟槽隔离。通过第一选择性外延生长工艺形成多个第一导电类型的阱，通过第二选择性外延生长工艺形成多个第二导电类型的阱。

Description

CMOS阱结构及其形成方法
技术领域
本发明涉及半导体器件，尤其涉及集成的半导体器件，例如互补金属氧化物半导体(CMOS)器件。
背景技术
在集成在同一芯片上的CMOS例如NMOS和PMOS中，在硅衬底上需要至少一个阱。例如，当采用P型衬底时，NMOS可以制造在衬底上，而PMOS必须制造在衬底中的n阱上。作为选择，当采用n型衬底时，PMOS可以制造在衬底上，而NMOS必须制造在衬底中的P-阱上。此外，为了避免与锁存(latch-up)有关的问题，通常采用双阱方式。无论最初衬底的类型如何，双阱方式包括在p阱上形成NMOS和在n阱上形成PMOS。双阱的掺杂剂浓度应是合适的，因而不会出现锁存的情况。
为了使两个阱完全与起始衬底隔离(isolate)，通常采用一个额外的阱。这被称作“三阱”结构。在这种情况下，例如，当n阱形成在n型衬底中时，如果n阱的底部和周围没有被p-掺杂材料密封，就不能与n阱隔离并对其实施与衬垫不同的偏压。一种常见的例子是在p-掺杂硅衬底上形成具有NMOS转移(transfer)栅极的DRAM阵列。在没有采用三阱结构的情况下，不能采用与地线不同的电压对DRAM阵列进行偏压。通常将负偏压oVbbo施加到内埋阱，这样能够保留电荷保持力。三阱结构还希望放置模拟器件，这种模拟器件要么产生高电平的噪音，要么需要非常安静的环境，三阱结构还可以应用于需要单独体偏压的器件或电路。
随着CMOS技术深入扩展到亚微米并进入到纳米的要求，对阱的形成提出了巨大的挑战。随着器件逐渐变小，对阱-阱和器件-阱尺寸的基本要求也相应地按比例变化。然而，应用于晶体管的相同比例因数不可以应用于由离子注入形成的常规阱中。与利用离子注入形成阱有关的一个问题是阱邻近效应，其中在阱的边缘处的掺杂轮廓在横穿阱的宽度上是不均匀的。这种现象是由于高能量的离子散射和高剂量离子注入造成的。结果，接近于阱的边缘设置的器件具有与远离阱边缘设置的器件不同的阈值电压Vt。对于这一问题的一种简单的解决方案是使器件远离阱的边缘。然而，这种方法不适用于6-T SRAM阵列，因为在这种阵列中存储元件必须密集组装。具体而言，使器件远离阱的边缘明显浪费了芯片空间，如果所得到的阈值电压对于SRAM元件不可接受，那么附加的掩模必须加入到工艺中以适当地集中阈值电压，造成额外成本和复杂性。
发明内容
本发明的目的是使阱可按比例缩放，这样就可以根据技术要求缩放阱-阱和器件-阱的尺寸。
本发明的另一目的是通过采用深和浅沟槽隔离的方式对不同导电类型的阱进行完全地隔离。
本发明的再一目的是采用完全自对准的、低温外延生长工艺在整块衬底上形成多个单独的阱结构。
根据本发明形成CMOS阱结构的方法包括在衬底上形成第一掩模，该第一掩模具有多个开口。在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱中的每一个形成在第一掩模的各开口中。在第一导电类型的阱的每一个上形成盖，并去除第一掩模。在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件。形成多个第二导电类型的阱，多个第二导电类型的阱的每一个形成在各个第一导电类型的阱之间。在第一导电类型的阱和第二导电类型的阱之间形成多个浅沟槽隔离。在多个第一导电类型的阱的每一个的内部形成至少一个第二导电类型的MOS器件，在多个第二导电类型的阱的每一个的内部形成至少一个第一导电类型的MOS器件。
在本发明的至少一个实施例中，通过第一选择性外延生长工艺形成多个第一导电类型的阱，通过第二选择性外延生长工艺形成多个第二导电类型的阱。
本发明的至少一个实施例包括：在衬底上形成多个第一导电类型的阱之前，将在第一掩模中多个开口之间的衬底刻蚀到预定深度。在形成侧壁间隔件的步骤之前，在衬底中形成多个第一导电类型的注入区，多个第一导电类型的注入区的每一个形成在衬底的各露出表面中。通过第一选择外延生长工艺形成多个第一导电类型的阱，在第一导电类型的注入区的露出表面上通过第二选择性外延生长工艺形成多个第二导电类型的阱。
本发明还提供了一种CMOS阱结构，通过下述方法形成，该方法包括：在衬底上形成第一掩模，该第一掩模具有多个开口；在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱的每一个分别形成在第一掩模的各开口中；在第一导电类型的阱的每一个上形成盖；去除第一掩模；在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件；以及形成多个第二导电类型的阱，该多个第二导电类型的阱形成在各个第一导电类型的阱之间。
本发明还提供了一种用于形成CMOS阱结构的方法，包括：在衬底上形成第一掩模，该第一掩模具有多个开口；对在第一掩模中的多个开口之间的衬底进行刻蚀，并刻蚀至预定深度；在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱的每一个分别形成在第一掩模的各开口中；在第一导电类型的阱的每一个上形成盖；去除第一掩模；在衬底中形成多个第一导电类型的注入区，多个第一导电类型的注入区的每一个分别形成在衬底的各露出表面中；在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件；以及形成多个第二导电类型的阱，该多个第二导电类型的阱形成在各个第一导电类型的阱之间。
通过结合附图阅读对本发明优选实施方式的详细描述，本发明的这些和其它目的和特点将更为明显。
附图说明
下面参照附图详细描述本发明的优选实施方式，其中：
图1-11是表示根据本发明的实施方式形成CMOS结构的方法的各步骤的横截面图；
图12-24是表示根据本发明的另一实施方式形成CMOS结构的方法的各步骤的横截面图；以及
图25是根据本发明的实施例的CMOS结构的横截面图。
具体实施方式
在本发明的各典型实施例中，在整块硅晶片中形成竖直侧壁的阱。采用连续低温选择性外延工艺形成竖直侧壁的单阱、双阱和三阱结构，从而消除由于离子散射造成的邻近效应。在不存在邻近效应的情况下，能够在所有通向阱边界的路径上的器件之间保持最小距离。本发明的各典型实施例采用深和浅沟槽隔离。利用侧壁间隔件技术在阱的边界处形成间隔件型薄竖直深沟槽，而采用浅沟槽不仅隔开阱内的器件，而且去除由选择性外延引起的在阱边界处的缺陷。
图1-11是表示根据本发明的典型实施例形成CMOS结构的方法的各步骤的横截面图。本实施例形成CMOS双阱结构。如图1所示，在p型衬底15上形成n-阱掩模10。n-阱掩模10具有多个露出p-型衬底15的上表面的开口12。通过在p-型衬底15上淀积掩模层并对掩模层进行构图，形成掩模10。掩模10可由任何适当的材料制成，例如多晶硅、二氧化硅(SiO2)或氮化硅(SiN)。第一掩模优选形成为约50nm至约500nm的厚度。
如图2所示，在n-阱掩模10的开口12内的p-型衬底15上形成n-阱区域16。通过n-型选择性外延生长工艺形成n-阱区域16。采用具有约1×1017/cm3至约1×1020/cm3的浓度的n-型掺杂剂原位掺杂n-阱区域16。n-阱区域16优选在掩模10上方形成有特定量的过生长f以避免形成拐角面(corner faceting)。
如图3所示，对n-阱区域16的上表面进行平整化，并去除外延过生长材料。可采用任何适当的抛光工艺进行这一步骤，例如化学机械抛光工艺(CMP)。
如图4所示，使n-阱区域16的上部凹进至预定深度b。在此步骤中，对n-阱区域16进行刻蚀工艺，例如湿法刻蚀工艺。
如图5所示，用盖21覆盖n-阱区域16。盖21可由任何适当的工艺形成，例如，化学汽相淀积(CVD)或热氧化。盖21可由例如二氧化硅制成。第一掩模10例如通过氮化物湿法刻蚀的方式去除，以获得图6所示的结构。
如图7所示，在n-阱区域16的竖直侧壁上形成间隔件28。该间隔件28可通过CVD工艺形成，其中，氮化物淀积成约为5-30nm的范围内的厚度。间隔件28密封n-阱区域16的侧壁，以避免向外扩散或交叉污染。
如图8所示，在n阱区域16之间的衬底15上形成p-阱区域30。采用在约1×1017/cm3至约1×1020/cm3的范围内的原位掺杂浓度、通过p-型选择性外延生长工艺形成p-阱区域30。p-阱区域30优选在盖21上形成有特定量的过生长h以避免形成拐角面。
如图9所示，对p-阱区域30的上表面进行平整化，并去除外延过生长材料。可采用任何适当的抛光工艺进行这一步骤，例如化学机械抛光工艺(CMP)。
如图10所示，用盖31覆盖p-阱区域30。可通过任何适当的工艺形成盖31，例如化学汽相淀积(CVD)或热氧化。盖31例如可由二氧化硅制成。
如图11所示，为了隔开器件并形成阱边界，形成浅沟槽隔离(STI)32。采用本领域技术人员熟知的标准浅沟槽工艺步骤形成STI32。STI 32使在n-阱区域16中的器件区34与在p-阱区域30中的器件区36隔离开。
在本发明的各种典型实施例中，可在器件区34和36中形成不同类型的半导体器件。在本发明的至少一个实施例中，利用本领域技术人员熟知的标准CMOS工艺步骤在n-阱器件区16中形成pMOS器件40、在p-阱器件区36中形成nMOS器件42。各MOS器件40和42包括栅电介质44、栅导体46、在栅导体46的顶部上形成的选择性硬掩模48以及至少在栅导体46的侧壁上形成的间隔件50。在pMOS器件40的n-阱器件区16中形成p+结点52，在nMOS器件42的p-阱器件区36中形成n+结点54。
图12-24是表示根据本发明的另一典型实施例形成CMOS结构的方法的各步骤的横截面图。本发明的本实施例形成CMOS三阱结构。如图12所示，在p-型衬底15上形成n-阱掩模10。n-阱掩模10具有多个露出p-型衬底15上表面的开口12。通过在p-型衬底15上淀积掩模层并对该掩模层构图，形成掩模10。掩模10可由任何适当的材料制成，例如，光刻胶、多晶硅、二氧化硅(SiO2)或氮化硅(SiN)。
如图13所示，对由n-阱掩模10中的开12露出的p-型衬底15部分进行刻蚀，从而在p-型衬底15中形成具有深度d的开口20。深度d优选在约20nm至约500nm的范围内。优选采用Cl2基RIE(反应性离子刻蚀)工艺对p-型衬底15进行各向异性刻蚀。为了避免损害衬底15，在刻蚀工艺中采用低功率等离子体，接着进行退火或清洗步骤。
如图14所示，在p-型衬底15中的开口20上形成n-阱区域16。通过n-型选择性外延生长工艺形成n-阱区域16。n-阱区域16优选在掩模10上形成有特定量的过生长f以避免形成拐角面。
如图15所示，对n-阱区域16的上表面进行平整化，并去除外延过生长材料。可采用任何适当的抛光工艺进行这一步骤，例如化学机械抛光工艺(CMP)。
如图16所示，将n-阱区域16的上部去除至预定深度b。在此步骤中，对n-阱区域16进行刻蚀工艺，例如，湿法刻蚀工艺。
如图17所示，用盖21覆盖n-阱区域16。通过任何适当的工艺例如化学汽相淀积(CVD)或热氧化形成盖21。盖21可由例如二氧化硅制成。第一掩模10例如通过氮化物湿法刻蚀的方式去除，从而获得图18所示的结构。
如图19所示，在n-阱区域16之间的衬底15中形成n+注入区26。通过任何现有技术形成n+注入区26，例如离子注入。表面注入掺杂浓度优选在约1×1019/cm3至约1×1021/cm3的范围内。在退火之后，最后埋入的n+注入区26具有约20nm至约600nm的厚度。
如图20所示，在n-阱区域16的竖直侧壁上形成间隔件28。可通过CVD工艺形成间隔件28，其中，将氮化物淀积至约为5-30nm的范围内的厚度。间隔件28密封n-阱区域16的侧壁以避免向外扩散或交叉污染。
如图21所示，在n-阱区域16之间的衬底15上形成p-阱区域30。采用在约1×1017/cm3至约1×1020/cm3的范围内的掺杂浓度、通过p-型选择性外延生长工艺形成p-阱区域30。p-阱区域30优选在盖21上形成有特定量的过生长以避免形成拐角面。
如图22所示，对p-阱区域30的上表面进行平整化，并去除外延过生长材料。可采用任何适当的抛光工艺进行这一步骤，例如化学机械抛光工艺(CMP)。
如图23所示，用盖31覆盖p-阱区域30。可通过任何适当的工艺形成盖31，例如化学汽相淀积(CVD)或热氧化。盖31例如可由二氧化硅制成。
如图24所示，为了隔开器件并形成阱边界，形成浅沟槽隔离(STI)32。采用本领域技术人员熟知的标准浅沟槽工艺步骤形成STI32。STI 32使在n-阱区域16中的器件区34与在p-阱区域30中的器件区36分开。
在本发明的各种典型实施例中，可在器件区34和36中形成不同类型的半导体器件。在本发明的至少一个实施例中，利用本领域技术人员熟知的标准CMOS工艺步骤在n-阱器件区16中形成pMOS器件40、在p-阱器件区36中形成nMOS器件42。各MOS器件40和42包括栅电介质44、栅导体46、在栅导体46的顶部上形成的选择性硬掩模48以及至少在栅导体46的侧壁上形成的间隔件50。在pMOS器件40的n-阱器件区16中形成p+结点52，在nMOS器件42的p-阱器件区36中形成n+结点54。
在本发明的另一实施例中，多个第一导电类型的阱中至少一个是虚拟(dummy)第一导电阱，所述虚拟第一导电阱终接至少一个第二导电类型的阱。例如，图25是根据本发明实施例的CMOS结构的横截面图。在此实施例中，在p-阱区域30的边缘处形成虚拟n-阱区域16A，以隔开p-阱区域30。在另一实施例中，在n-阱区域的边缘处形成虚拟p-阱区域(未示出)以隔开n-阱区域。
虽然在此参照附图描述了优选实施方式，但是应理解本发明及方法不限于那些具体实施例，在不脱离本发明的范围和实质的条件下，相关领域的技术人员可以对其进行各种修改和其他改变。所有的这种变化和修改都涵盖在由附加权利要求限定的本发明的范围内。

Claims (34)

1.一种用于形成CMOS阱结构的方法，包括：
在衬底上形成第一掩模，该第一掩模具有多个开口；
在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱的每一个分别形成在第一掩模的各开口中；
在第一导电类型的阱的每一个上形成盖；
去除第一掩模；
在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件；以及
形成多个第二导电类型的阱，该多个第二导电类型的阱形成在各个第一导电类型的阱之间。
2.根据权利要求1的方法，进一步包括：
在第一导电类型的阱和第二导电类型的阱之间形成多个浅沟槽隔离，以便隔离第一导电类型的阱和第二导电类型的阱；
在多个第一导电类型的阱的每一个的内部形成至少一个第二导电类型的MOS器件；和
在多个第二导电类型的阱的每一个的内部形成至少一个第一导电类型的MOS器件。
3.根据权利要求1的方法，其中通过第一选择性外延生长工艺形成多个第一导电类型的阱，通过第二选择性外延生长工艺形成多个第二导电类型的阱。
4.根据权利要求1的方法，其中第一掩模是低温化学汽相淀积的氮化物。
5.根据权利要求1的方法，其中第一掩模的厚度在50nm至500nm的范围内。
6.根据权利要求3的方法，其中形成多个第一导电类型的阱的步骤包括形成用第一导电掺杂剂原位掺杂的第一外延层。
7.根据权利要求6的方法，其中第一导电掺杂剂的掺杂浓度在1×1017/cm3至1×1020/cm3的范围内。
8.根据权利要求6的方法，进一步包括：
将第一外延层形成至比第一掩模的厚度更大的厚度以避免形成外延面；和
将第一外延层深刻蚀至比第一掩模的厚度更小的厚度。
9.根据权利要求3的方法，其中形成多个第二导电类型的阱的步骤包括形成用第二导电掺杂剂原位掺杂的第二外延层。
10.根据权利要求9的方法，其中第二导电掺杂剂的掺杂浓度在1×1017/cm3至1×1020/cm3的范围内。
11.根据权利要求9的方法，进一步包括：
将第二外延层形成至比第一导电类型的阱的厚度更大的厚度以避免形成拐角面；和
对第二外延层进行平整化。
12.根据权利要求1的方法，其中形成盖的步骤包括热氧化。
13.根据权利要求1的方法，其中形成侧壁间隔件的步骤包括化学汽相淀积。
14.根据权利要求1的方法，其中侧壁间隔件由氮化物制成。
15.根据权利要求1的方法，其中侧壁间隔件的厚度在5nm至30nm的范围内。
16.根据权利要求1的方法，其中第一导电类型是n-型，第二导电类型是p-型。
17.根据权利要求1的方法，进一步包括：
在衬底上形成多个第一导电类型的阱之前，对在第一掩模中的多个开口之间的衬底进行刻蚀，并刻蚀至预定深度。
18.根据权利要求17的方法，进一步包括：
在形成侧壁间隔件的步骤之前在衬底中形成多个第一导电类型的注入区，多个第一导电类型的注入区中的每一个分别形成在衬底的各露出表面中。
19.根据权利要求18的方法，其中，通过第一选择性外延生长工艺形成多个第一导电类型的阱，并在第一导电类型的注入区的露出表面上通过第二选择性外延生长工艺形成多个第二导电类型的阱。
20.根据权利要求17的方法，其中预定深度在20nm至500nm的范围内。
21.根据权利要求18的方法，其中第一导电类型的注入区的掺杂浓度在1×1019/cm3至1×1021/cm3的范围内。
22.根据权利要求18的方法，其中多个第一导电类型的注入区形成在衬底中，达到20nm至600nm的深度。
23.根据权利要求19的方法，其中多个第一导电类型的阱的至少一个是虚拟第一导电阱，所述虚拟第一导电阱终接至少一个第二导电类型的阱。
24.根据权利要求19的方法，其中多个第二导电类型的阱的至少一个是虚拟第二导电阱，所述虚拟第二导电阱终接至少一个第一导电类型的阱。
25.根据权利要求19的方法，其中第一导电类型是n-型，第二导电类型是p-型。
26.一种CMOS阱结构，通过下述方法形成，该方法包括：
在衬底上形成第一掩模，该第一掩模具有多个开口；
在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱的每一个分别形成在第一掩模的各开口中；
在第一导电类型的阱的每一个上形成盖；
去除第一掩模；
在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件；以及
形成多个第二导电类型的阱，该多个第二导电类型的阱形成在各个第一导电类型的阱之间。
27.根据权利要求26的CMOS阱结构，其中该方法进一步包括：
在第一导电类型的阱和第二导电类型的阱之间形成多个浅沟槽隔离，以便隔离第一导电类型的阱和第二导电类型的阱；
在多个第一导电类型的阱的每一个的内部形成至少一个第二导电类型的MOS器件；和
在多个第二导电类型的阱的每一个的内部形成至少一个第一导电类型的MOS器件。
28.根据权利要求26的CMOS阱结构，其中通过第一选择性外延生长工艺形成多个第一导电类型的阱，通过第二选择性外延生长工艺形成多个第二导电类型的阱。
29.根据权利要求26的CMOS阱结构，其中在衬底上形成多个第一导电类型的阱之前，对在第一掩模中的多个开口之间的衬底进行刻蚀，并刻蚀至预定深度。
30.根据权利要求29的CMOS阱结构，其中在形成侧壁间隔件的步骤之前在衬底中形成多个第一注入区，多个第一导电类型的注入区中的每一个分别形成在衬底的各露出表面中。
31.根据权利要求30的CMOS阱结构，其中，通过第一选择性外延生长工艺形成多个第一导电类型的阱，并在第一导电类型的注入区的露出表面上通过第二选择性外延生长工艺形成多个第二导电类型的阱。
32.根据权利要求26的CMOS阱结构，其中第一导电类型是n型，第二导电类型是p型。
33.一种用于形成CMOS阱结构的方法，包括：
在衬底上形成第一掩模，该第一掩模具有多个开口；
对在第一掩模中的多个开口之间的衬底进行刻蚀，并刻蚀至预定深度；
在衬底上形成多个第一导电类型的阱，多个第一导电类型的阱的每一个分别形成在第一掩模的各开口中；
在第一导电类型的阱的每一个上形成盖；
去除第一掩模；
在衬底中形成多个第一导电类型的注入区，多个第一导电类型的注入区的每一个分别形成在衬底的各露出表面中；
在第一导电类型的阱的每一个的侧壁上形成侧壁间隔件；以及
形成多个第二导电类型的阱，该多个第二导电类型的阱形成在各个第一导电类型的阱之间。
34.根据权利要求33的方法，其中通过第一选择性外延生长工艺形成多个第一导电类型的阱，并在第一导电类型的注入区的露出表面上通过第二选择性外延生长工艺形成多个第二导电类型的阱。
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