CN1295879C - 在可重构逻辑中宽多路复用器的实现 - Google Patents

在可重构逻辑中宽多路复用器的实现 Download PDF

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Publication number
CN1295879C
CN1295879C CNB038061848A CN03806184A CN1295879C CN 1295879 C CN1295879 C CN 1295879C CN B038061848 A CNB038061848 A CN B038061848A CN 03806184 A CN03806184 A CN 03806184A CN 1295879 C CN1295879 C CN 1295879C
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China
Prior art keywords
output
signal
input
signals
multiplexer
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Expired - Fee Related
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CNB038061848A
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English (en)
Chinese (zh)
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CN1643793A (zh
Inventor
K·莱坦－诺瓦克
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
CNB038061848A 2002-03-18 2003-03-17 在可重构逻辑中宽多路复用器的实现 Expired - Fee Related CN1295879C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076049.2 2002-03-18
EP02076049 2002-03-18

Publications (2)

Publication Number Publication Date
CN1643793A CN1643793A (zh) 2005-07-20
CN1295879C true CN1295879C (zh) 2007-01-17

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ID=27838094

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CNB038061848A Expired - Fee Related CN1295879C (zh) 2002-03-18 2003-03-17 在可重构逻辑中宽多路复用器的实现

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US (1) US8082284B2 (enExample)
EP (1) EP1488523B1 (enExample)
JP (1) JP4260026B2 (enExample)
CN (1) CN1295879C (enExample)
AT (1) ATE458310T1 (enExample)
AU (1) AU2003209576A1 (enExample)
DE (1) DE60331296D1 (enExample)
WO (1) WO2003079550A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004045527B4 (de) 2003-10-08 2009-12-03 Siemens Ag Konfigurierbare Logikschaltungsanordnung
CN102147720B (zh) * 2011-03-18 2014-04-09 深圳市国微电子有限公司 用查找表实现多输入逻辑项之间的运算的装置及方法
US9450585B2 (en) * 2011-04-20 2016-09-20 Microchip Technology Incorporated Selecting four signals from sixteen inputs
JPWO2014163099A1 (ja) * 2013-04-02 2017-02-16 太陽誘電株式会社 再構成可能な論理デバイス
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
JP6653126B2 (ja) * 2015-04-28 2020-02-26 太陽誘電株式会社 再構成可能な半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118300A (en) * 1998-11-24 2000-09-12 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US5233539A (en) * 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
JP3127654B2 (ja) * 1993-03-12 2001-01-29 株式会社デンソー 乗除算器
JPH06276086A (ja) * 1993-03-18 1994-09-30 Fuji Xerox Co Ltd フィールドプログラマブルゲートアレイ
US5426379A (en) * 1994-07-29 1995-06-20 Xilinx, Inc. Field programmable gate array with built-in bitstream data expansion
US5442306A (en) 1994-09-09 1995-08-15 At&T Corp. Field programmable gate array using look-up tables, multiplexers and decoders
JPH09181598A (ja) 1995-12-18 1997-07-11 At & T Corp フィールドプログラマブルゲートアレイ
US6154049A (en) * 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
JP2003526129A (ja) * 1997-12-17 2003-09-02 エリクセントリミティド プログラマブル・アレイにおける乗算器の実現
GB9727414D0 (en) * 1997-12-29 1998-02-25 Imperial College Logic circuit
JP3123977B2 (ja) * 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック
JP3269526B2 (ja) 1999-02-09 2002-03-25 日本電気株式会社 プログラマブルロジックｌｓｉ
US6556042B1 (en) * 2002-02-20 2003-04-29 Xilinx, Inc. FPGA with improved structure for implementing large multiplexers
US6816562B2 (en) * 2003-01-07 2004-11-09 Mathstar, Inc. Silicon object array with unidirectional segmented bus architecture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118300A (en) * 1998-11-24 2000-09-12 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables

Also Published As

Publication number Publication date
JP4260026B2 (ja) 2009-04-30
DE60331296D1 (de) 2010-04-01
AU2003209576A1 (en) 2003-09-29
EP1488523B1 (en) 2010-02-17
EP1488523A2 (en) 2004-12-22
JP2005521288A (ja) 2005-07-14
WO2003079550A3 (en) 2004-03-04
ATE458310T1 (de) 2010-03-15
US20050232297A1 (en) 2005-10-20
US8082284B2 (en) 2011-12-20
WO2003079550A2 (en) 2003-09-25
CN1643793A (zh) 2005-07-20

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Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20070817

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Address after: Holland Ian Deho Finn

Patentee after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Patentee before: Koninklijke Philips Electronics N.V.

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Granted publication date: 20070117

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CF01 Termination of patent right due to non-payment of annual fee