CN1267090A - 带有每位线栓柱四个节点和两级字线布局的6 1/4 f2DRAM单元结构 - Google Patents
带有每位线栓柱四个节点和两级字线布局的6 1/4 f2DRAM单元结构 Download PDFInfo
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Abstract
公开了一种四柱型单元结构,将两个不同的单元之间的共享位线栓柱延伸(一维线中排列,例如W方向),进一步到在两维区域(x和y方向)内尽可能大程度地共享,随后形成一个位线栓柱周围交叉的四个单元,每个漏区和埋置带延伸到侧边,附带的沟槽形成钩形结构。
Description
由于持续开发密集存储器的压力，DRAM单元的尺寸总是目前最关心的。目前的设计表明字线和位线相互垂直设置，存储器单元每两个成对排列，共用一个接触两个存储器单元位线的位线栓柱。图1示出了常规沟槽DRAM存储器单元布局的俯视局部示意图，图2示出了根据图1布局的三维局部剖面图。每对存储器单元与两个沟槽电容器1和由漏(源)以及埋置带2组成的两个有源存取通路相连，栅3与一个BL栓柱和下面的一个漏(源)区4相连。作为第一级金属线，字线5设置在有源存取器件上，同时形成器件的栅。位线栓柱连接到设置在垂直于字线的第二级金属上的各位线6，BLn，其中n为整数。存储器单元的尺寸通常由制备存储器单元中定义的最小特征尺寸限定。通常，最小特征尺寸等于存储器单元栅的宽度。测量常规的DRAM存储器单元为每单元8f2。按比例缩小显示在图1中，其中4个单元包围在8f×4f的区域内。由此，(32f2/4单元)＝8f2/单元。例如，0.15微米最小特征尺寸的DRAM包括每单元0.3μm×0.6μm＝0.18(μm)2芯片面积。以相互垂直的布局方式，在每一个单元的一个方向中设置2个单元，得到矩形排列取向。因此需要新的布局，能更紧密地排列，由此存在方形排列取向。
图1示出了常规存储器单元布局的俯视局部示意图。
图2示出了根据图1的布局的三维局部剖面图。
图3示出了本发明的DRAM的单元布局的俯视图，提供了具有每位线栓柱四个节点和两级字线的61/4f2DRAM单元结构。
图4示出了使用单元电容器作为沟槽电容器的本发明的布局的三维局部剖面图。
使用了相同的参考数字和符号。
图3示出了本发明的DRAM的单元布局的俯视图，提供了带有每位线栓柱四个节点(单元)和两级字线的61/4f2DRAM单元结构。位线(BL)栓柱和漏/源区10显示在4个单元的中心，每个都与俯视剖面图中示为圆形的单元电容器7相连。漏/源埋置带8将电容器7与它的各存储单元的漏/源相连。显示出在相连的漏/源区8和10之间的栅9以及各埋置带和BL栓柱。四个栅共享一个公共的BL栓柱和漏/源区10，漏/源区10将共享的漏/源区与四个栅和位线13相连。每个四栅结构称做四柱型单元，通常由参考数字15表示。如图所示，5f乘5f的特征尺寸将四个单元约束在一个平面的方形区域中。因此每个单元占据表面积为25f2/4＝6.25f2。通过和使用0.15微米最小特征尺寸的以上例子比较，本发明的布局占据的表面积为0.1406...(μm2)，小于8f2的常规单元的0.18(μm)2的表面积。更紧密的尺寸还表示稍微不同的位线和字线取向。在所述布局中，一些字线平行于位线，导体提供了到存储器单元的存取，在READ和WRITE期间和REFRESH期间将信息输入和输出到单元，操作周期性地存储单元信息，以补偿电容器的泄露。
图4示出了使用沟槽电容器作为单元电容器的本发明的布局的三维局部剖面图。沿易于示出结构的平面截取显示出图4中的许多元件(字线和位线)。沟槽电容器7向下延伸到芯片衬底内，这里显示为圆柱形。显示的电容器7仅为示例。此外，电容器可以为叠置电容器或沟槽与叠置电容器的一些组合。第0级金属级(称做0级字线)上的字线11，图3中显示的两个字线分别为字线n和字线n+1(其中n在这里代表整数)，连接到每个四节点结构15的两个栅9，在第2级金属中平行于位线13(两个位线分别显示为位线n+1和位线n)，第2级金属通过通孔连接到各位线栓柱和下面的漏/源区10。第二个第1级金属(称做1级字线)12上的字线服务于每个四节点结构(或四柱)15中的两个单元，通过类似于位线栓柱4的栓柱，通孔(也称做字线栓柱14)将栅9连接到第1级金属中的字线12。金属1中的字线12(由WLn+2和WLn+3表示)垂直于金属级0中的字线11。位线13平行(如以上的介绍中所使用)或垂直于0级金属中的字线11。
虽然与常规的存储器结构相比，通过对附加的金属级的介绍，所示的结构显示出附加的工艺复杂性，这不是必须的，因为位线可以制备在金属级上，也可以用在常规的存储器设计中。
在以上介绍的DRAM单元结构中，如以上介绍的图中所示，以上的图中所示可以如下制备：通过使用深沟槽(DT)腐蚀、DT多晶硅填充以及DT多晶硅化学机械抛光(CMP)等，从在图3所示的布局中形成多个沟槽电容器8开始，通过一系列的工艺步骤处理硅晶片。沟槽电容器的填充物作为一个电极，带有某些注入层的硅本体作为另一个电极。这些工艺步骤在本领域中已公知，可以包括进一步的工艺步骤，例如生成埋置极板、外扩散、多步骤重新腐蚀和重新填充、轴环侧壁氧化、退火步骤等，用于沟槽电容器的实际制造。通过以上工艺产生的沟槽电容器8通过埋置带10连接到在十字形晶体管的有源区(AA)内形成的有源器件。AA区通过环绕的浅沟槽隔离(STI)区相互隔离。使用反应离子腐蚀(RIE)技术以及使用镶嵌技术生成以上提到的金属层。生长以后作为栅氧化物的氧化硅层。在其上淀积薄Si3N4层。淀积掺杂硼的磷硅玻璃(BPSG)的第三个可能较厚的层。在以后将生成所有栅9的位置腐蚀所述BPSG层形成孔。以前淀积的Si3N4层作为腐蚀终止层。以孔的直径稍小于一个特征尺寸的方式进行光致抗蚀剂的曝光，使每个四柱的四个孔不相互接触。用亚硝酸盐剥离，除去形成的孔底部上的Si3N4，以便露出栅氧化物。然后将多晶硅淀积到孔内，厚度比孔的直径小。除去其余的BPSG和Si3N4。因此，由多晶硅制备成小圆柱形，形成栅。形成圆柱形硅栅之后，进行自对准离子注入步骤产生如场效应晶体管(FET)等的有源器件，作为到存储单元的穿通晶体管。BPSG淀积在圆柱形硅栅之间，进行CMP得到平面化表面，用于进一步的工艺步骤。
接下来，如图4所示，将第一个零级字线(0级字线)11或所谓的栅导体(GC)叠层直接淀积在沟槽电容器7上并延伸在每个四柱的四栅中的两个上。(也可以看到带波形字线的布局)。这些GC叠层接触以前制备的圆柱形硅栅，部分是由于以前提到的延伸，部分是由于线的狭窄部分。(图3示出了梯形延伸，而图4为矩形的。实际的形状取决于使用的光刻方法和设备的性能。)GC叠层含有DRAM制造中常见的多晶硅层、WSi2层和Si3N4层。这些零级字线11或GC叠层由可能由氮化物组成的薄隔离保护层覆盖。进一步淀积厚隔离层，通常为BPSG，形成隔离填充和覆盖零级字线11。随后在留给栅9的横向位置处腐蚀所述隔离层，形成到作为腐蚀终止的其余两个圆柱形硅栅的孔。由于以前淀积的薄保护层，所以没有露出相邻的栅叠层11。首先用类似于覆盖字线使用的薄保护层填充产生的孔，然后用多晶硅填充产生字线栓柱14，字线栓柱14达到随后垂直于零级字线11淀积的第一级字线12，如图4所示。第一级字线12还是由导电和/或不导电的材料的不同层组成。然而重要的是覆盖第一级字线的薄保护膜。进一步淀积由BPSG或TEOS制备的厚绝缘层之后，用类似于以前对零级字线11介绍的步骤，填充并覆盖第一级字线12，进行从每个四柱结构的中心到硅晶片表面的最终腐蚀。在所述腐蚀期间，通过以前提到的保护层保护相邻的字线11，12和字线栓柱14不暴露。此外用于最后的腐蚀步骤的光抗蚀剂曝光期间，可以进行额外偏置以减小孔的直径，并确保腐蚀不损伤以前产生的结构。孔用多晶硅填充，形成位线栓柱，达到位线13，最终形成在以前介绍的平行于零级字线11的两级字线11和12上。随后用公知和典型的back-end-of-line(BEOL)进一步处理布线结构。
虽然这里参考优选实施例和一些介绍的替换例详细地介绍了本发明，应该明白所述说明仅为示例，而不用于限定。还应该明白参考所述说明之后，本领域的普通技术人员显然可以对本发明的实施例和本发明的附加实施例的细节进行各种改变。所有的改变和附加的实施例都在以下要求的本发明的精神和实际范围内。
Claims (19)
1.一种半导体存储器，包括：
多个第一字线和多个第二字线，所述多个第一字线主要在与所述多个第二字线主要延伸的不同平面内延伸。
2.根据权利要求1的半导体存储器，包括多个电容器，选择性地连接到相关的所述多个第一和第二字线中的一组上，所述电容器由沟槽电容器、叠置电容器、或它们的组合组成。
3.根据权利要求1的半导体存储器，其中所述多个第一字线与所述多个第二字线正交。
4.根据权利要求1的半导体存储器，其中所述场效应晶体管组成垂直或水平的器件。
5.根据权利要求1的半导体存储器，其中每个单元占据的表面积为6.25f2。
6.一种半导体存储器，包括一个单元四柱，该单元包括设置在位线栓柱周围的四个晶体管栅极，每个单元四柱包括四个场效应晶体管和四个单元电容器，每个场效应晶体管的漏/源区通过带连接到相关的单元电容器。
7.根据权利要求6的半导体存储器，其中所述存储器在半导体衬底中实现，所述带埋置在所述半导体衬底内。
8.根据权利要求6的半导体存储器，其中所述存储器在半导体衬底中实现，所述场效应晶体管制备为水平或垂直器件或它们的组合。
9.根据权利要求6的半导体存储器，还包括多个第一字线和多个第二字线，所述多个第一字线主要在与所述多个第二字线主要延伸的不同平面内延伸。
10.根据权利要求9的半导体存储器，其中所述多个第一字线基本上垂直于所述多个第二字线设置。
11.根据权利要求6的半导体存储器，还包括主要在与所述多个第一字线和所述多个第二字线所在的平面不同并与所述多个第二字线正交设置的平面内延伸的位线。
12.根据权利要求6的半导体存储器，其中所述单元电容器由沟槽电容器、叠置电容器、沟槽/叠置电容器或它们的组合中的一个组成。
13.根据权利要求6的半导体存储器，其中每个单元占据的表面积为6.25f2。
14.一种半导体存储器的制造方法，包括：
在半导体衬底上设置栅氧化层；
在所述栅氧化层上设置氮化硅层；
在所述氮化硅层上设置BPSG填充层；
在所述BPSG填充层中腐蚀出多个孔，所述氮化硅层起腐蚀终止的作用；
进行氮化硅剥离，由此在所述孔中露出所述栅氧化物；以及
用厚度基本上小于每个孔的多晶硅填充所述多个孔。
15.根据权利要求14的半导体存储器的制造方法，还包括使用反应离子腐蚀技术、镶嵌技术或它们的组合组成的处理方法形成金属层的步骤。
16.一种半导体存储器，包括多个第一字线和多个第二字线，所述多个第一字线与所述多个第二字线正交设置。
17.根据权利要求16的半导体存储器，还包括多个单元电容器，选择性地连接到所述多个第一和第二字线中的一组上。
18.根据权利要求17的半导体存储器，其中每个所述单元电容器形成制备为叠置器件的器件的至少一部分。
19.根据权利要求17的半导体存储器，其中每个所述电容器形成制备为沟槽器件的器件的至少一部分。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/163,670 US6188095B1 (en) | 1998-09-30 | 1998-09-30 | 6¼ f2 DRAM cell structure with four nodes per bitline-stud and two topological wordline levels |
| US09/163670 | 1998-09-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1267090A true CN1267090A (zh) | 2000-09-20 |
| CN1225027C CN1225027C (zh) | 2005-10-26 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991208501A Expired - Fee Related CN1225027C (zh) | 1998-09-30 | 1999-09-30 | 带有每位线栓柱四个节点和两级字线布局的61/4f2DRAM单元结构 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6188095B1 (zh) |
| EP (1) | EP0991124A3 (zh) |
| JP (1) | JP2000114496A (zh) |
| KR (1) | KR20000023521A (zh) |
| CN (1) | CN1225027C (zh) |
| TW (1) | TW464871B (zh) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331733B1 (en) * | 1999-08-10 | 2001-12-18 | Easic Corporation | Semiconductor device |
| US6667502B1 (en) * | 1999-08-31 | 2003-12-23 | Micron Technology, Inc. | Structurally-stabilized capacitors and method of making of same |
| US6570211B1 (en) * | 2002-06-26 | 2003-05-27 | Advanced Micro Devices, Inc. | 2Bit/cell architecture for floating gate flash memory product and associated method |
| KR100866710B1 (ko) * | 2002-07-18 | 2008-11-03 | 주식회사 하이닉스반도체 | 반도체 소자의 워드라인 형성 방법 |
| US6727540B2 (en) * | 2002-08-23 | 2004-04-27 | International Business Machines Corporation | Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact |
| KR100539276B1 (ko) | 2003-04-02 | 2005-12-27 | 삼성전자주식회사 | 게이트 라인을 포함하는 반도체 장치 및 이의 제조 방법 |
| US7161226B2 (en) * | 2003-10-20 | 2007-01-09 | Industrial Technology Research Institute | Multi-layered complementary wire structure and manufacturing method thereof |
| JP2005285971A (ja) * | 2004-03-29 | 2005-10-13 | Nec Electronics Corp | 半導体装置 |
| US7501676B2 (en) * | 2005-03-25 | 2009-03-10 | Micron Technology, Inc. | High density semiconductor memory |
| US20080074927A1 (en) * | 2006-09-22 | 2008-03-27 | Franz Hofmann | Memory array having an interconnect and method of manufacture |
| US8310859B2 (en) * | 2008-09-30 | 2012-11-13 | Samsung Electronics Co., Ltd. | Semiconductor memory device having balancing capacitors |
| JP5653001B2 (ja) * | 2009-03-16 | 2015-01-14 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体装置及び半導体装置の補償容量の配置方法 |
| US8872344B2 (en) | 2010-06-09 | 2014-10-28 | Texas Instruments Incorporated | Conductive via structures for routing porosity and low via resistance, and processes of making |
| KR101119038B1 (ko) * | 2011-06-01 | 2012-03-16 | 주식회사 오킨스전자 | 적층구조를 갖는 반도체 패키지 지지장치 |
| US10834611B1 (en) * | 2019-09-05 | 2020-11-10 | International Business Machines Corporation | Network availability notification in predefined travel scenarios |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03188668A (ja) * | 1989-12-18 | 1991-08-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH03278573A (ja) * | 1990-03-28 | 1991-12-10 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2824713B2 (ja) * | 1992-04-24 | 1998-11-18 | 三菱電機株式会社 | 半導体記憶装置 |
| US5838038A (en) * | 1992-09-22 | 1998-11-17 | Kabushiki Kaisha Toshiba | Dynamic random access memory device with the combined open/folded bit-line pair arrangement |
| JPH07202022A (ja) * | 1993-12-28 | 1995-08-04 | Nippon Steel Corp | 半導体記憶装置 |
| US5770874A (en) * | 1994-11-14 | 1998-06-23 | Nippon Steel Corporation | High density semiconductor memory device |
| JPH08227982A (ja) * | 1994-11-14 | 1996-09-03 | Nippon Steel Corp | 高密度半導体記憶装置 |
| KR100190522B1 (ko) * | 1995-06-09 | 1999-06-01 | 김영환 | 반도체 메모리 집적회로 및 그 제조방법 |
| JP2950265B2 (ja) * | 1996-07-30 | 1999-09-20 | 日本電気株式会社 | 半導体記憶装置 |
-
1998
- 1998-09-30 US US09/163,670 patent/US6188095B1/en not_active Expired - Lifetime
-
1999
- 1999-08-21 EP EP99116439A patent/EP0991124A3/en not_active Withdrawn
- 1999-09-29 KR KR1019990041695A patent/KR20000023521A/ko not_active Application Discontinuation
- 1999-09-29 TW TW088116719A patent/TW464871B/zh not_active IP Right Cessation
- 1999-09-30 JP JP11280142A patent/JP2000114496A/ja active Pending
- 1999-09-30 CN CNB991208501A patent/CN1225027C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0991124A3 (en) | 2005-12-14 |
| US6188095B1 (en) | 2001-02-13 |
| EP0991124A2 (en) | 2000-04-05 |
| KR20000023521A (ko) | 2000-04-25 |
| JP2000114496A (ja) | 2000-04-21 |
| TW464871B (en) | 2001-11-21 |
| CN1225027C (zh) | 2005-10-26 |
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