CN1241020A - 制造金属氧化物半导体晶体管的方法 - Google Patents

制造金属氧化物半导体晶体管的方法 Download PDF

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CN1241020A
CN1241020A CN99109412A CN99109412A CN1241020A CN 1241020 A CN1241020 A CN 1241020A CN 99109412 A CN99109412 A CN 99109412A CN 99109412 A CN99109412 A CN 99109412A CN 1241020 A CN1241020 A CN 1241020A
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赵昶贤
李美香
高宽协
河大元
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Abstract

向半导体衬底中注入第一导电杂质离子,由此形成阱区,其上再形成栅极。向栅极两侧的阱区中注入第一非导电杂质,以便控制其中的衬底缺陷,从而形成具有第一深度的第一沉淀区。向栅极两侧的阱区中注入第二非导电杂质离子,从而形成具有比第一深度相对浅的第二深度的源/漏区。向源/漏区中注入第二非导电杂质,以便控制其中的衬底缺陷,从而形成第二沉淀区。这种衬底缺陷如位错、扩展缺陷和堆垛层错同P－N结区隔离开,由此形成稳定P－N结。

Description

制造金属氧化物半导体晶体管的方法
本发明涉及制造半导体器件的方法，特别涉及制造MOS晶体管的方法，其能够减少由衬底缺陷产生的P-N结漏电流。
随着半导体存储器件的集成水平的提高，发展了千兆位单元的DRAM(动态随机存取存储器)器件。由于千兆位单元器件的元件按比例缩小到0.18μm以下，所以可能产生较大应力。
如果应力超过任何临界值，则在硅衬底中产生位错，以此来解除应力。由于成比例缩小，所以形成器件隔离区的工艺从LOCOS(局部硅氧化)转换为STI(浅槽隔离)。但是，STI可能对半导体衬底施加比LOCOS大的应力。如在文章“stress-induces dislocation in siliconintegrated circuits”(P.M.Fahey et al.，IBM J.RES.DEVELOP，v.36，p.158，1992)中所述，近来不断报导提高由位错和扩展缺陷产生的结损伤。
在半导体的制造工艺中，由于很容易实现掺杂浓度和掺杂分布曲线而使离子注入技术在用于制造器件的P-N结的方法中是很重要的。然而，在这种离子注入工艺中具有高能量的离子穿透单晶硅。如果掺杂浓度超过任何临界值，则硅衬底的结晶性被破坏而形成非晶层。非晶层的结晶性通过下面的退火而恢复。在退火过程中，留下的缺陷被收集以产生扩展缺陷、堆垛层错和位错环(“formation of extended effects insilicon by high energy implantation of B and P”J.Y.Cheng etal.，Phys.v.80(4)p.2105，1996；“annealing behavilours of dislocation loopsnear the projected range in high-dose as implanted(001)Si”by S.N.Hsu etal.，J Appl.Phys.v.86(9).p.4503，1990)。
图1A是表示现有半导体衬底中的缺陷的XTEM(X-透射电子显微技术)照片。
参见图1A，如果前述位错、扩展缺陷和堆垛层错穿透半导体器件的P-N结区‘A’，则产生不正常结特性。
图1B是表示现有半导体衬底中的缺陷的SEM(扫描电子显微技术)。
参见图1B，通过前述离子注入工艺在靠近器件隔离区和有源区的边缘部分‘B’中产生缺陷。如果由于这些缺陷而使反向偏置电压施加于P-N结上，则对P-N结又施加了不正常的反向电流。
图2是表示现有半导体器件中P-N结的电子特性的曲线。
参照图2，在反向偏置电压施加于现有P-N结的情况下，曲线‘C’表示对于不正常结的反向偏置电流，曲线‘D’表示对于正常结的反向偏置电流。图中示出了施加于不正常结的反向偏置电流大于施加于正常结的反向偏置电流。这些特性可能增加辅助电流，因而在制造低功耗器件中产生严重问题、使元件失效并降低成品率。
因此本发明的主要目的是提供用于半导体器件的方法，其能够通过将晶格缺陷如位错、扩展缺陷和堆垛层错同P-N结区隔离开而形成稳定的P-N结。
根据本发明的目的，在半导体衬底上形成栅极。向栅极两侧的半导体衬底中注入导电杂质离子，从而形成源/漏区。向源/漏区中注入非导电杂质，从而形成沉淀区，以便控制其中的衬底缺陷。
根据本发明的目的，向半导体衬底中注入第一导电杂质离子，从而形成阱区。在阱区上形成栅极。向栅极两边的阱区中注入第一非导电杂质，以便控制其中的衬底缺陷，从而以第一深度形成第一沉淀区。向栅极两边的阱区中注入第二导电杂质离子，从而以比第一深度相对较浅的第二深度形成源/漏区。向源/漏区中注入第二非导电杂质以便控制其中的衬底缺陷，从而形成第二沉淀区。
本发明的晶体管包括：形成在半导体衬底中的第一导电阱区；通过向第一导电阱中注入第一非导电杂质以便控制其中的衬底缺陷而形成的具有第一深度的第一沉淀区；形成在第一导电阱上的栅极；形成在栅极两边的第一阱区中并具有比第一深度相对较浅的第二深度的第二导电源/漏区；和通过向源/漏区中注入第二非导电杂质以便控制其中的衬底缺陷而形成的第二沉淀区。
在该方法中，向阱区中注入第一非导电杂质以便控制其中的衬底缺陷，从而形成第一沉淀区。向源/漏区中注入第二非导电杂质以便控制其中的衬底缺陷，从而形成第二沉淀区。这样，将衬底缺陷如位错、扩展缺陷和堆垛层错同P-N结区隔离开，由此形成稳定P-N结。
附图中：
图1A是表示现有半导体衬底中的缺陷的XTEM(X-透射电子显微技术)照片；
图1B是表示现有半导体衬底中的缺陷的SEM(扫描电子显微技术)；
图2是表示现有半导体器件中P-N结的电子特性的曲线；以及
图3A-3D是表示根据本发明制造MOS晶体管的工艺步骤的流程图。
下面参照附图详细介绍本发明的最佳实施例。
图3A-3D依次表示根据本发明制造MOS晶体管的工艺步骤。
参照图3A，在半导体衬底100上形成器件隔离区102，以便确定有源区和无源区。器件隔离区102是用例如STI(浅槽隔离)形成的。有源区被分为PMOS和NMOS区。常规地，向PMOS区中注入N型杂质离子，从而形成N型阱区104a，向NMOS区中注入P型杂质离子，从而形成P型阱区104b。向半导体衬底100的整个表面注入第一非导电杂质，从而在N型和P型阱区104a和104b上形成第一沉淀区106。由于第一非导电杂质是选自氧、碳和氮中的一种，所以第一沉淀区是由选自SiO2、SiC和SiN中的一种形成的。
第一非导电杂质应由通过注入杂质如氧而不具有电极性化的稳定区形成的，该稳定区包括带有半导体衬底100的化学化合物，沉淀区只包括其本身。另外，第一非导电杂质的注入浓度应该比半导体衬底100(即硅衬底)的固溶度(1018原子/cm3)大，并小于第一沉淀区可能形成不希望的层的浓度。这意味着：如果注入到第一非导电杂质中的氧的浓度太高，会形成产生SIMOX(注氧隔离)结构的新SiO2层。因此不希望形成如SiO2层等新层。简而言之，氧的注入浓度应该低到使半导体衬底100不形成这种结构。在U.S.专利4749660中已经介绍了控制注入浓度的一种方法。
首先，参照图3C，在具有其间插入的栅氧化物层的半导体衬底100上形成栅极108。用栅极108作掩模，向有源区的半导体衬底100中注入用于形成LDD(低掺杂漏)的低浓度导电杂质离子，由此形成低浓度的源/漏区110。向N型阱区中注入P型杂质离子，向P型阱区中注入N型杂质离子。
然后，在栅极108两侧壁上形成间隔层109。例如，在包括栅极108的半导体衬底100上形成氮化硅层之后，各向异性地腐蚀该氮化硅层，以形成间隔层109。
用间隔层109和栅极108作掩模，注入用于减小薄层电阻和接触电阻的高浓度导电杂质离子，由此形成高浓度的源/漏区114。向N型阱区中注入P型杂质离子，向P型阱区中注入N型杂质离子。然后，在半导体衬底100中形成相等深度的高浓度和低浓度的源/漏区114和110，或者高浓度的源/漏区114形成得比低浓度的源/漏区110相对较深。高浓度的源/漏区114形成得比第一沉淀区106浅。
接下来通过前述方法，用栅极108和间隔层109作掩模，注入第二非导电杂质，从而形成第二沉淀区116。第二非导电杂质是选自氧、碳和氮中的一组。第二非导电杂质的注入浓度应该大于半导体衬底100的固溶度(1018原子/cm3)，并小于第一沉淀区106可能形成不希望的层的浓度。当形成第一沉淀区106时，这与前面的意思相同。第二沉淀区116的深度比高浓度的源/漏区114的浅。
通过注入非导电杂质形成的第一和第二沉淀区106和116可以起到如下作用：
由离子注入产生的晶格缺陷、由STI应力产生的晶格缺陷和非晶层产生小层叠缺陷和位错环。之后，这些缺陷生长为衬底缺陷，如扩展缺陷和位错。离子注入缺陷在“Ion Implantation Science and Technology”J.F.Ziegler，pp.63-92，Academic Press 1998中已有介绍。
[公式1]
∈＝(a’-a)/a
在[公式1]中，∈是半导体衬底的张力，a是半导体衬底中的球形空间的半径，a’是沉淀的尺寸。[公式1]表示使半径a的弹性体进入半径a’的半导体衬底中的球形空间而产生的张力。
[公式2]
Ui＝4×G×b×a3×∈×sinθ/r
在[公式2]中，Ui是在作为衬底缺陷的电势和半径a’的沉淀之间操作的能量，G是半导体衬底(即硅衬底)的弹性系数，b是位错的程度，a是半径，其与球形空间的沉淀半径几乎相同，r是沉淀和电势之间的距离，∈是[公式1]中的半径。[公式2]在“Impurities andImperfections”E.R.Parker，J.Washburm，ASM，Metals Park，Ohio，p.155，1995中有介绍。
参照图3D，本发明的MOS晶体管包括：形成在半导体衬底100中的阱区104a和104b；形成在阱区104a和104b中的第一沉淀区106；形成在阱区104a和104b中的栅极108；形成在栅极两侧的阱区104a和104b中的源/漏区110和114，这里源/漏区110和114的深度比第一沉淀区106的浅；形成在源/漏区110和114中的第二沉淀区116。
如果沉淀区，如[公式2]中的，是在硅的单晶中，则会产生位错对其沉淀起作用的力。然后，该作用力使位错如半导体缺陷拉出沉淀或不再生长。在距P-N结有一点距离处形成沉淀时，衬底缺陷可能远离P-N结的界面。因此衬底缺陷不可能穿透其界面。结果防止了由衬底缺陷引起的界面损伤。
由于在现有半导体器件中P-N结区可能被衬底缺陷如位错损伤，所以P-N结区产生不正常反向偏置电流特性。但是在本发明中，靠近P-N结区形成沉淀区，由此防止衬底缺陷的生长和P-N结区的损伤。

Claims (13)

1.一种制造MOS晶体管的方法，包括以下步骤：
在半导体衬底上形成栅极；
向所述栅极两侧的所述半导体衬底中注入导电杂质离子；和
向所述源/漏区中注入非导电杂质，形成控制其中的衬底缺陷的沉淀区。
2.根据权利要求1的方法，其特征在于，所述非导电杂质是选自氧、碳和氮中的一种。
3.根据权利要求1的方法，其特征在于，所述非导电杂质的注入浓度约为1018原子/cm3，或是在SIMOX(注氧隔离)中抑制不希望的层如SiO2层的形成的预定值。
4.一种制造MOS晶体管的方法，包括以下步骤：
向半导体衬底中注入第一导电杂质离子，从而形成阱区；
在所述阱区上形成栅极；
向所述栅极两侧的所述阱区中注入第一非导电杂质，以便控制其中的衬底缺陷，从而形成具有第一深度的第一沉淀区；
向所述栅极两侧的所述阱区中注入第二导电杂质离子，从而形成具有第二深度的源/漏区，其中所述第二深度比所述第一深度相对浅；和
向所述源/漏区中注入第二非导电杂质，以便控制其中的衬底缺陷，从而形成第二沉淀区。
5.根据权利要求4的方法，其特征在于，所述非导电杂质是选自氧、碳和氮中的一种。
6.根据权利要求4的方法，其特征在于，所述第二非导电杂质是选自氧、碳和氮中的一种。
7.根据权利要求4的方法，其特征在于，所述第一非导电杂质的注入浓度约为1018原子/cm3，或是在SIMOX(被注入氧分离)中抑制不希望的层如SiO2层的形成的预定值。
8.根据权利要求4的方法，其特征在于，所述第二非导电杂质的注入浓度约为1018原子/cm3，或是在SIMOX中抑制不希望的层如SiO2层的形成的预定值。
9.制造DRAM晶体管的方法，包括：
在半导体衬底中形成第一导电阱区；
通过向所述第一导电阱区中注入第一非导电杂质以便控制其中的衬底缺陷而形成的具有第一深度的第一沉淀区，；
在所述第一导电阱上形成栅极；
在所述栅极两侧的所述第一阱区中形成的具有第二深度的第二导电源/漏区，其中所述第二深度比所述第一深度相对浅；和
通过向所述源/漏区中注入第二非导电杂质以便控制其中的衬底缺陷而形成的第二沉淀区。
10.根据权利要求9的方法，其特征在于，所述第一非导电杂质是选自氧、碳和氮组成的一组。
11.根据权利要求9的方法，其特征在于，所述第二非导电杂质是选自氧、碳和氮中的一种。
12.根据权利要求9的方法，其特征在于，所述沉淀区是以抑制在SIMOX(注氧隔离)中不希望的层如SiO2层的形成的预定浓度即约为1018原子/m3注入所述第一非导电杂质形成的。
13.根据权利要求9的方法，其特征在于，所述沉淀区是以抑制在SIMOX(注氧隔离)中不希望的层如SiO2层的形成的预定浓度即约为1018原子/m3注入所述第二非导电杂质形成的。
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