CN1239322A - 采用条纹图形的覆盖测定技术 - Google Patents

采用条纹图形的覆盖测定技术 Download PDF

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CN1239322A
CN1239322A CN99108894A CN99108894A CN1239322A CN 1239322 A CN1239322 A CN 1239322A CN 99108894 A CN99108894 A CN 99108894A CN 99108894 A CN99108894 A CN 99108894A CN 1239322 A CN1239322 A CN 1239322A
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K·P·穆勒
V·C·普拉卡斯
C·J·古尔德
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Siemens AG
International Business Machines Corp
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种测定半导体器件制造过程中在晶片上进行的两个掩蔽工序之间不对齐的方法，先在掩蔽工序使用的两个掩模上分别配备特殊的对齐图形，再将对齐图形的各影象彼此重叠起来，形成条纹图形。将条纹图形与已知的对应于掩模不对齐的特定量的其它条纹图形相比较，看其是否对应于容许的对齐情况。

Description

采用条纹图形的覆盖测定技术
本发明涉及半导体器件的制造，更具体地说，涉及标记图形在覆盖测定中的应用，而覆盖测定正是这种制造工艺使用的掩模对齐工序中重要的一个环节。
在大多数半导体器件特别是集成电路器件的制造过程中，许多处理工序是在晶片阶段进行的。在这类制造过程中，较大晶片例如12英寸直径晶片是经过一系列工序的处理形成不同导电类型的各种区域和各种各样确定特定集成电路器件的接线的。所有这些完成之后，晶片经过切割，形成大量的芯片，每一芯片含一个集成电路。总希望制成的集成电路都具有大体上一致的特性。
通常，这类器件的制造包括一系列处理工序，这些工序有很多是由掩模控制的。这些掩模事先设置在晶片表面上，其作用是确定各处理工序能在晶片的各特定区域起作用的位置。要使经处理的各区域在位置上达到所要求的精确度，特别是要使晶片上表成的集成电路达到所要求一致性时，重要的一点是使这些掩模彼此大致上对齐。
要使一系列处理工序中使用的掩模达到所求的对齐程度，通常是在掩模上采用特殊的标记或记号在晶片各边缘上打印一致的标记，并用这些晶片标记进行对齐工序中重要的覆盖测定。
此外，还有一点很重要，即及早检测出处理过程中任何显著的不对齐情况，以便在进一步进行处理之前及时加以校正。
目前，检测不对齐情况的测定法采用蚀刻在晶片上大小不同一般为方形或矩形的框作为对齐标记，用这些不同大小的框彼此互套用来检测不对齐情况。这种方法受到两个条件的限制：一是框形可能出现的不对称和形成各框所使用的线条的宽度，二是要求各线条够长够宽以便可以直接测量。这个限制使框框法用在目前工艺水平元器件、大小等于或小于0.25微米的集成电路中时不能充分发挥作用。
本发明提供一种新型的确定掩模不对齐的方法，特别适用于零部件大小等于或小于0.25微米的器件的制造。
本发明是在采用条纹图形的基础上测定半导体器件制造过程中印制在各不同层面上两个不同掩模图形之间的任何不对齐情况。条纹图形是将两个彼此贴近的间距和线条组成的图形(一般说来为两个仅有小小差别的重复图形)重叠起来观看时形成的特殊图形。条纹图形的结构和位置在提供两线条/间距重复图形不对齐的程度。
本发明的半导体器件制造过程中用以检测两个独立掩蔽工序中不对齐情况的方法如下。给两个两掩蔽工序中使用的各掩模配备这样一种重复性的标记图形，这种图形两个彼此重叠在一起时会产生能表示两个图形不对齐程度的条纹图形。接着，依次用各掩模在处理中彼此重叠的半导体晶片上印制两个掩模上的两个图形。将观测到的条纹图形与已知的规定两个掩模之间不对齐情况容许范围的条纹图形相比较，从而制断晶片连续的处理过程在质量上是否得到保证。
更简单地说，本发明涉及半导体器件制造过程中检测两掩蔽工序不对齐情况的一种方法。这种方法包括下列步骤：给两个掩蔽工序使用的各掩模配备这样一种重复性的标记图形，这种图形两个重叠在一起时会产生能表示两个掩模不对齐程度的条纹图形；用两个掩模在处理中的半导体圆片表面上形成两个掩模彼此重叠的标记图形，并产生条纹图形；用光观测所产生的条纹图形；将观测到的条纹图形与两掩模之间达到容许对准程度时相应的条纹图形相比较。
从下面结合附图所作的更详细说明可以更好地理解本发明。
图1示出了100条平行直线和等宽间距组成的重复图形。
图2示出了类似的重复图形，其中各线条和间距的宽度比图1的图形增加1％。
图3示出了图2的图形覆盖在图1的图形上、各图形左侧的第一条线对齐时得出的条纹图形。
图4示出了图2的图形覆盖在图1的图形上、图2图形的第一条线向左偏移第一偏移量时得出的条纹图形。
图5示出了图2的第一条线向左的偏移量为图4所示偏移量的两倍时同类型覆盖情况的条纹图形。
图6示出了与二维对准时使用的方格盘有关的典型条纹图形。
现在参看图1，图中示出了重复对齐图形，图形展示的距离举例说为42微米，由100条直线和间距组成，各直线和间距分别宽210微米。在本发明的实施例中，这种对齐图形可在所控制的两个工艺中使用的两个掩模的第一掩模上形成。接着，依次在用以确定处理在硅圆片上的效果的光致抗蚀剂上形成上述线条重复图形。这个重复图形最好蚀刻在晶片的边缘区域(切口)上，这样做有好处。
接着，给要使用的第二掩模也配备线条/间距组成的类似重复图形，但各线条和间距的宽度比参看图1和图2所述的宽一些。将此重复图形重叠到已蚀刻在硅晶片上的线条/间距图形上，使第二图形的第一条线与早先蚀刻在硅晶片上图形的第一条线对齐。一般说来，在硅晶片与第二掩模之间先配备控制第二处理过程的光致抗蚀剂。接着，在光致抗蚀剂上有效蚀刻出此第二线条/间距图形，将图2的线条/间距图形重叠到图1的图形上。
图3中所示的条纹图形表明，两线条/间距图形的头两条线准确对齐，这通常保证了两掩模所提供的掩模图形起码在垂直于线条/间距图形各线条的方向上达到所要求的紧密对准。
但若象图4或图5所示的那一种条纹图形，则表明第二掩模没有对好，在此情况下，就要卸除第二掩模及其光致抗蚀剂，用重新就位的掩模重新绘出新光致抗蚀剂的图形，根据早先得出的结果校正不对齐的情况。
具体地说，在图2的图形如图4中所示的那样向左偏移105纳米的情况下，实心黑方框出现在从图3中的向右偏移10.5微米的位置。这显示了不对齐放大了100倍的情况，这个放大倍数是通过在图1图形的基础上将图2的图形扩大1％确定的。在进一步向左偏移105纳米的不对齐的情况下，上述条纹图形右端有一个实心黑方框形成，在条纹图形在端有另一个黑方框形成，如图5中所示。
本发明最好这样运用有利：先标定出各种不同的不对齐情况相应的一系列条纹图形，然后观察实际工作的条纹图形，看其是否与所标定的表示容许不对齐情况的条纹图形相当。
一般说来，形成的条纹图形是用光观测用肉眼比较的，但也可以将系统设计成试验自动化的那一种。
各种灵敏度的试验图形可以通过改变图形线条和间距的宽度和/或其宽度上的差别设计出来。宽度的差别越小，试验的灵敏度就越高，但一般说来应用起来也就更困难了。
因此，通常要得出合乎要求的灵敏度或放大倍数，就要适当选取用来产生条纹图形的两图形的参数。这种方法可用来试验水平或垂直方向不对齐的情况。此外，用方形方格盘或两图形大小略不相同的方格盘可以测定出垂直和水平方向的不对齐情况。不对齐的情况不同，得出的条纹图形也不同，图6示出了典型的条纹图形。
不言而喻，这里说明的个别方法仅仅是对本发明一般原理的说明而已。在不脱离本发明精神实质的前提下是可以进行种种修改的，例如采用曲线和间距组成的重复图形或其它线条和间距组成的重复图形。

Claims (4)

1.一种检测半导体制造过程中两个掩蔽工序不对齐情况的方法，它包括下列步骤：
给掩蔽工序使用的两个掩模配备一种重复图形，这种重复图形彼此重叠在一起时能产生表示两个掩模不对齐程度的条纹图形；
用所述两个掩模在处理中的半导体晶片表面形成两个掩模彼此重叠时的标记图形，以产生条纹图形；
用光观测所产生的条纹图形；
将所观测的条纹图形与两个掩模达到容许的对齐情况时相应的条纹图形相比较。
2.如权利要求1所述的方法，其中两个掩模上的重复图形由多个线条和间距组成，两个图形的区别仅在于线条和间距的宽度上。
3.如权利要求2所述的方法，其中各图形中的各线条和间距，宽度均匀，两图形线条和间距的宽度差也均匀。
4.如权利要求1所述的方法，其中两个掩模各自的标记图形为相同的方块组成的方格盘图形，两个图形中各方块的大小相差一定值。
CN99108894A 1998-06-15 1999-06-15 采用条纹图形的覆盖测定技术 Pending CN1239322A (zh)

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US09/097,784 US6150231A (en) 1998-06-15 1998-06-15 Overlay measurement technique using moire patterns
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