CN1211822A - 用于半导体存储器元件的熔丝装置 - Google Patents

用于半导体存储器元件的熔丝装置 Download PDF

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CN1211822A
CN1211822A CN98116946A CN98116946A CN1211822A CN 1211822 A CN1211822 A CN 1211822A CN 98116946 A CN98116946 A CN 98116946A CN 98116946 A CN98116946 A CN 98116946A CN 1211822 A CN1211822 A CN 1211822A
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fuse
fuses
equipment
semiconductor
planes
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CN1134842C (zh
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H·戈贝尔
G·克劳瑟
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Infineon Technologies AG
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Siemens AG
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明涉及一种用于半导体存储器元件的熔丝装置,具有若干熔丝(1),这些熔丝配置在一个半导体上并且可以分别通过能量作用为了分断一个导电连接而编程。为了节省芯片面积,熔丝(1)至少重叠配置在两个平面(2,3)上。

Description

用于半导体存储器元件的熔丝装置
本发明涉及一种用于半导体存储器元件的熔丝装置,此熔丝装置具有若干熔丝,这些熔丝制作在半导体上并且可以分别通过能量作用而分断或者产生导电连接而实现编程。
大家知道,为了在半导体存储器元件中永久的存储数据,并且为了在这些半导体存储器元件上对冗余进行编程而采用熔丝。在第一种情况下熔丝的状态(“导电”或“不导电”)确定了一个数据量(“0”或“1”),而在后一种情况下当一个存储器单元出现故障时通过熔丝的激活而接通一个冗余的存储器单元。
通常熔丝由例如多晶硅或一种其它的适当材料构成,通过能量作用可以熔化,从而使本来存在的导电连接分断。但是也可以设想来用一种材料,这种材料通过能量作用由不导电状态过渡到导电状态,以便构成导电连接。但是下面应从这种情况出发,即通过能量的作用使现存的导电连接遭到破坏。
能量作用例如可以通过一个激光光束照射在一个熔丝上,或者也可以简单地通过如下情况进行,即一个比较大的电流送入一个特定的熔丝中并使其熔化。
到目前为止的熔丝装置,是采用制作在半导体表面上或半导体存储器元件芯片上,例如以矩阵形式相邻排列的若干熔丝。随着熔丝数量的增大,就是说随着半导体存储元件存储量的增大,所需的芯片面积总量亦随之增大。
为了尽可能的减小所需的芯片面积,到目前为止曾试图尽量减小熔丝几何尺寸。但是,这种措施的限制在于,在熔丝激活和编程时,就是说例如在用一个激光光束照射熔丝时,各个分立的熔丝之间应相互保持一段最小的间距,以便通过激光光束照射时能够有目的的、准确的将所希望的熔丝熔断。
因此本发明的任务在于,提出一种熔丝装置,这种熔丝装置以具有显著减小的安装位置需求为特征,并且其中各个分立的熔丝仍然能够有目的的和可靠的激活。
此项任务按照本发明在本文开始所述类型的一个熔丝装置上是这样解决的,即这些熔丝至少制作在半导体上的两个平面内。就是说这些熔丝上下排列在许多个、例如n个平面上。这样,熔丝在半导体上所需要的面积近似减小了n倍,如果不考虑熔丝接线端布线的话。
熔丝的各个平面各通过一个绝缘层、例如二氧化硅相互隔离。对于这些熔丝本身而言,例如采用多晶硅,这种材料通过电流流过或通过至少两个激光光束的重叠作用能够导致熔断从而激活熔丝。这两个起作用的激光光束相交在待激活的熔丝上。
就是说在本发明中这些熔丝配置在若干个平面上,这些平面通过绝缘层相互隔离。通常熔丝的编程是通过一个激光光束进行的,用此光束将熔丝材料熔化,从而将导电连接分断。
在若干个上下重叠的熔丝平面的情况下,这些保险或者可以通过使熔丝材料导致熔化的一个特定的电流、或者也可以通过若干激光光束的重叠进行编程。其中,激光光束的强度应这样选择,即唯一的一个光束还不能使材料损坏,通过若干光束重叠在一点上(即在待编程的熔丝所在位置)使增大的光强足以使此熔丝损坏。
下面藉助于附图对本发明进一步加以阐述,在唯一的一个附图上示出了在两个平面上的一个熔丝装置,其中为了更好的表示这两个平面而省略了起隔离作用的绝缘层。
在此图中,由多晶硅构成的熔丝1配置在Z方向上的上下重叠的两个平面2、3上,在一个在x-y平面延伸的在图中未示出的半导体的表面上,并且通过同样未示出的由二氧化硅构成的绝缘层相互隔离。
一个待编程的熔丝4置于两个激光光束5、6作用之下,这两个光束相交于熔丝4范围的一个点7上,这样,在那里熔丝4熔化从而分断了导电连接。其中,激光光束5、6的能量是这样整定的,即单独一个光束还不能引起熔化,这样可以保证只有有目的的将熔丝4破坏,在这里激光光束5,6相交而此时其它的熔丝1均保持完好。
取代相交的激光光束5、6也可以将一个这样的电流送入熔丝4,使得熔丝4熔化并且因此而损坏。
参考符号表
1熔丝
2平面
3平面
4待编程的熔丝
5激光光束
6激光光束
7相交点

Claims (4)

1.用于半导体存储器元件的熔丝装置具有若干熔丝(1),这些熔丝配置在一个半导体上并且可以分别通过能量作用而分断或者产生导电连接而实现编程,
其特征在于,
熔丝(1)至少配置在半导体的两个平面上并且可以至少通过两个激光光束(5,6)的重叠作用(7)而编程,其中,重叠的激光光束(5,6)相交在待编程的熔丝(4)上。
2.根据权利要求1所述熔丝装置,其特征在于,熔丝(1)的平面(2,3)通过一个绝缘层相互隔离。
3.根据权利要求2所述熔丝装置,其特征在于,绝缘层是由二氧化硅构成的。
4.根据权利要求1至3其中之一所述熔丝装置,其特征在于,熔丝(1)是由多晶硅构成的。
CNB981169465A 1997-08-28 1998-08-28 用于半导体存储器元件的熔丝装置 Expired - Fee Related CN1134842C (zh)

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DE19737611.8 1997-08-28
DE19737611A DE19737611C2 (de) 1997-08-28 1997-08-28 Fuse-Anordnung für Halbleiterspeichervorrichtung

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CN1134842C CN1134842C (zh) 2004-01-14

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DE19946495C2 (de) * 1999-09-28 2002-10-24 Infineon Technologies Ag Verfahren zur Verringerung der Anzahl der Pads auf einem Halbleiterchip
KR100399411B1 (ko) * 2001-03-09 2003-09-26 삼성전자주식회사 내장형 메모리 및 이 메모리의 퓨즈 배치 방법
US6700096B2 (en) * 2001-10-30 2004-03-02 Semiconductor Energy Laboratory Co., Ltd. Laser apparatus, laser irradiation method, manufacturing method for semiconductor device, semiconductor device, production system for semiconductor device using the laser apparatus, and electronic equipment
US7105048B2 (en) * 2001-11-30 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Laser irradiation apparatus
US20040247013A1 (en) * 2003-05-14 2004-12-09 Clark Daniel P. Calibration device for a dental furnace
US7154396B2 (en) * 2004-12-30 2006-12-26 Nokia Corporation Ultra wideband radio frequency identification techniques
US7983024B2 (en) * 2007-04-24 2011-07-19 Littelfuse, Inc. Fuse card system for automotive circuit protection

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JPS60127598A (ja) * 1983-12-14 1985-07-08 Toshiba Corp 半導体集積回路装置
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DE19737611A1 (de) 1999-03-04
EP0899745A3 (de) 1999-10-06
DE19737611C2 (de) 2002-09-26
KR100286050B1 (ko) 2001-04-16
US6274410B2 (en) 2001-08-14
TW385448B (en) 2000-03-21
US20010000758A1 (en) 2001-05-03
EP0899745A2 (de) 1999-03-03
JPH11150239A (ja) 1999-06-02
JP3728111B2 (ja) 2005-12-21
KR19990023867A (ko) 1999-03-25
US6180992B1 (en) 2001-01-30
CN1134842C (zh) 2004-01-14

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