CN1188910C - 半导体芯片及其制作方法 - Google Patents

半导体芯片及其制作方法 Download PDF

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Publication number
CN1188910C
CN1188910C CNB011117788A CN01111778A CN1188910C CN 1188910 C CN1188910 C CN 1188910C CN B011117788 A CNB011117788 A CN B011117788A CN 01111778 A CN01111778 A CN 01111778A CN 1188910 C CN1188910 C CN 1188910C
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dielectric
layer
metal
chip
supporting structure
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Expired - Fee Related
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CNB011117788A
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CN1314710A (zh
Inventor
J·J·埃利斯－莫纳格翰
P·M·菲尼
R·M·格夫肯
H·S·兰迪斯
R·A·普雷维蒂－科利
B·L·B·路透
M·J·鲁藤
A·K·斯坦珀
S·J·杨基
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Ultratech Corp
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International Business Machines Corp
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Abstract

一种半导体芯片的方法和结构，它包含：多个互连金属化层；所述互连金属化层上的至少一个可形变的介电材料层；支持结构，它包含耦合到所述可形变的介电材料的比所述可形变的介电材料坚固的电介质；以及至少一个耦合到所述支持结构的输入/输出键合焊点，其中所述支持结构对所述焊点进行支持，以避免所述可形变的介电材料破裂。

Description

半导体芯片及其制作方法
技术领域
本发明一般涉及到半导体芯片，更确切地说是涉及到在键合工艺过程中保护芯片的结构。
背景技术
低介电常数(k)层间介电(ILD)材料(例如甩涂玻璃(SOG)、Hydrogen silsesquioxane(HSQ)、甲基硅烷(MSQ)、苯并环丁烯(BCB)等)，已经普遍用作先期制造的半导体芯片的输入/输出(I/O)和机械支持结构。在已经完成半导体芯片的逻辑功能选择之后，制作这种I/O和支持结构。因此，由于它们是在生产线的后期制作，故这种结构/工艺有时被称为“后部工艺”(BEOL)。
然而，比之二氧化硅，许多低k材料是易碎的或柔软的，因而当施加键合力时，低k材料很容易被损伤。更具体地说，在键合工艺(例如超声金属丝键合)过程中或在制作焊料球(C4)连接的过程中施加的力，能够损伤低k介电材料。于是，来自超声能量(金属丝键合)、毛细管压力和温度的损伤就能够使低k绝缘体强度降低或破裂。
而且，比之二氧化硅，诸如聚亚芳基醚(美国密执安Midland的Dow Chemical制造的商品名为SILK的以及美国加州Sunnyvale的Honeywell制造的FLARE)、或氧化硅气凝胶、含碳的CVD电介质、Methyl sisquoxiane(MSQ)、Hydrogen-sisquoxiane(HSQ)之类的超低介电常数材料(k＜3)，其机械强度很差。机械强度不足对于使用超低介电常数材料作为层间电介质的互补金属氧化物半导体(CMOS)的金属丝键合连接来说是严重的问题。因此需要能够提供低k绝缘体与C4/金属丝键合结构之间的兼容性的新的工艺和结构。
关于上述问题的目前做法包括提高低k电介质的材料性质(诸如提高强度和粘合性的工艺)、将多个金属膜集成在铜上以提供与目前的C4/金属丝键合工艺的兼容性、以及对铜进行硅化以改善氮化物粘合性。Mukul Saran等人最近的文章1998 IEEE 38th Annual IRPS-Reno，NV，March 31，1998，p.225-231(此处列为参考)描述了使用金属网格来提供介电叠层的机械加固，以便消除Al或Au丝在金属丝键合到铝焊点过程中的键合焊点损伤。
发明内容
因此，本发明的目的是提供一种半导体芯片的结构和方法。
根据本发明的第一方面，提供了一种半导体芯片，它包含：多个互连金属化层；所述互连金属化层上的至少一个可形变的介电材料层；支持结构，它包含耦合到所述可形变的介电材料的比所述可形变的介电材料坚固的电介质；以及至少一个耦合到所述支持结构的输入/输出键合焊点，其中所述支持结构对所述焊点进行支持，以避免所述可形变的介电材料破裂。
根据本发明的第二方面，提供了一种集成电路芯片，它包含：逻辑电路；覆盖所述逻辑电路的外部绝缘体；以及所述绝缘体上的电连接到所述逻辑电路的接触，其中所述外部绝缘体包括：具有第一介电常数的第一介电层；以及耦合到所述第一介电层的支持结构，其包括具有比所述第一介电常数高的第二介电常数的电介质。
根据本发明的第三方面，提供了一种集成电路芯片，它包含：逻辑电路；覆盖所述逻辑电路的外部绝缘体；以及所述绝缘体上的能够电连接到所述逻辑电路的接触，其中所述接触包含延伸在所述外部绝缘体上的金属结构。
根据本发明的第四方面，提供了一种集成电路芯片，它包含：逻辑电路；覆盖所述逻辑电路的外部绝缘体；以及所述绝缘体上的电连接到所述逻辑电路的接触，其中所述外部绝缘体具有网格结构，它包括具有第一介电常数的第一电介质和具有比所述第一介电常数高的第二介电常数的第二电介质。
根据本发明的第五方面，提供了一种集成电路芯片，它包含：逻辑电路；覆盖所述逻辑电路的外部绝缘体；以及所述外部绝缘体上的电连接到所述逻辑电路的接触，其中所述外部绝缘体包括所述逻辑电路与所述接触之间的支持柱。
根据本发明的第六方面，提供了一种制造半导体芯片的方法，所述方法包含：制作多个互连金属化层；制作所述互连金属化层上的至少一个可形变的介电材料层；制作支持结构，它包含耦合到所述可形变的介电材料的比所述可形变的介电材料坚固的电介质；以及制作至少一个输入/输出键合焊点，其中所述支持结构被制作成对所述焊点进行支持，以避免所述可形变的介电材料破裂。
根据本发明的第七方面，提供了一种制作集成电路芯片的方法，它包含：制作逻辑电路；制作覆盖所述逻辑电路的外部绝缘体；以及制作所述绝缘体上的电连接到所述逻辑电路的接触，其中所述外部绝缘体的所述制作包括：制作具有第一介电常数的第一介电层；以及制作具有比所述第一介电常数高的第二介电常数的支持结构，所述支持结构与第一介电质相耦合。
因此，本发明提供的一种半导体芯片的结构和方法，它包括多个互连金属化层、互连金属化上的至少一个可形变的介电材料层、至少一个输入/输出键合焊点，以及包括对焊点进行支持的避免可形变的介电材料发生破裂的相当坚固的电介质的支持结构。
此支持结构包括可形变介电材料上的覆盖层，其中的覆盖层与图形化的最后金属层共平面，即覆盖层的厚度大于图形化的最后金属层的厚度。支持结构还可以包括被竖固的电介质分隔的图形化的金属层，其中图形化的金属层被多个通过坚固的电介质的金属连接连在一起，或可以包括从最后的金属层延伸进入可形变的介电材料的金属支柱结构。支柱结构可以是多个逐层制作在可形变的介电材料中的金属块。金属块能够组成人字形图形剖面或台阶形剖面结构。
本发明的另一个实施例是一种集成电路芯片，它包括逻辑电路、覆盖逻辑电路的外部绝缘体、以及绝缘体上的能够电连接到逻辑电路的接触。外部绝缘体包括具有第一介电常数的第一介电层和具有比第一介电常数高的第二介电常数的支持结构。
本发明的另一个实施例是一种集成电路芯片，它包括逻辑电路、覆盖逻辑电路的外部绝缘体、以及绝缘体上的能够电连接到逻辑电路的接触。此接触包括延伸在外部绝缘体上的金属结构。此金属结构具有柱形或锥形形状。
本发明的另一个实施例是一种集成电路芯片，它包括逻辑电路、覆盖逻辑电路的外部绝缘体、绝缘体上的能够电接触到逻辑电路的接触、以及包括具有第一介电常数的第一电介质和具有比第一介电常数高的第二介电常数的第二电介质的网格结构。此网格结构可以是第二电介质在第一介电层中的交错图形、第一电介质和第二电介质组成的交替层、或各个第一电介质部分之间的第二电介质的侧壁间隔。
本发明的另一个实施例是一种集成电路芯片，它包括逻辑电路、覆盖逻辑电路的外部绝缘体、以及外部绝缘体上的能够电接触到逻辑电路的接触。外部绝缘体包括逻辑电路与接触之间的支持柱。此支持柱是外部绝缘体中的部分金属化的通孔层，并可以是以绝缘体填充的空柱。支持柱可以包括热沉，并可以被隔开，使布线能够位于外部绝缘体中。
本发明克服了与上述常规BEOL结构相关的问题。更具体地说，本发明包含BEOL结构顶部上或BEOL结构内部的额外的结构，在金属丝或C4键合工艺过程中加强了对层间电介质(ILD)的支持。
附图说明
从参照附图对本发明的最佳实施例的下列详细描述中，可以更好地理解上述的和其它的目的、情况和优点，其中：
图1是最后金属(LM)层上的本发明的覆盖层的示意图；
图2是具有焊点的LM层上的本发明的覆盖层的示意图；
图3是与LM共平面的LM层处的厚度等于LM的本发明的覆盖层的示意图；
图4是与LM层共平面的厚度大于LM层的本发明的覆盖层的示意图；
图5是LM-1与LM之间的本发明的覆盖层的示意图以及铆钉设计；
图6是具有支柱的本发明的覆盖层的示意图；
图7是本发明的垂直叠层的示意图；
图8是本发明的人字形叠层的示意图；
图9是本发明的楼梯形叠层的示意图；
图10是含有金属柱的本发明的键合焊点的示意图；
图11是被腐蚀过的图10所示结构的示意图；
图12是基底和网格的单层混合介电材料的示意图；
图13示意图示出了本发明的网格交错图形；
图14示意图示出了不同电介质组成的单线；
图15是建立本发明网格的开始阶段的示意图；
图16是制作的本发明网格结构的示意图；
图17是建立本发明网格的另一阶段的示意图；
图18是建立本发明网格的最后阶段的示意图；
图19是制造本发明网格结构的开始阶段的示意图；
图20是本发明网格结构的示意图；
图21是本发明网格结构的示意图；
图22是本发明网格结构的示意图；
图23是本发明网格结构的示意图；
图24示意图示出了本发明的金属柱；
图25示意图示出了本发明键合焊点柱支持；
图26是本发明键合焊点柱支持的示意图；
图27是本发明键合焊点柱支持的放大示意图；
图28是本发明键合焊点柱支持的示意图；
图29是本发明键合焊点柱支持的示意图；
图30是本发明键合焊点柱支持的示意图；
图31是本发明键合焊点柱支持的剖面示意图；
图32是本发明键合焊点柱支持的放大剖面示意图；
图33示意图示出了在铜焊点与最后的铜层之间具有额外的金属层的结构的例子；
图34示意图示出了取消了图34所示的额外金属层的结构；
图35是为了提供根据本发明的布线沟道而在根部之间得到的间隔的俯视示意图；以及
图36是根据本发明的高度粘合结构的示意图。
附图标号
501    PSG或BPS
352    LM-1层
361    LM
363    LM-1
364-1  氧化物
364-2  氮化物
511    LM-2
512    LM-3
具体实施方式
本发明克服了与上述常规BEOL结构相关的问题。更具体地说，本发明包含BEOL结构顶部上或BEOL结构内部的额外的结构，在金属丝或C4键合工艺过程中加强了对层间电介质(ILD)的支持。
图1示出了本发明的第一实施例，此实施例包括最后金属化层(LM)11、倒数第二金属化层(LM-1)13、连接金属化层11和13的导电通孔12、以及提供电绝缘但对于提供适当的机械支持来说太易碎的层间电介质14。除了常规的结构之外，本发明还包括保护用的覆盖层10。
本发明增加了最后金属化(LM)层11上的保护用覆盖层10。覆盖层10的厚度在1-20微米之间，且最好是10微米厚。覆盖层10可以由例如二氧化硅(SiO2)、甩涂玻璃(SOG)、氮化硅、掺杂的(例如掺F、B、P的)SiO2、HSQ、MSQ、或其它相似的保护物质制作。最佳实施例可以包含50nm氮化物、1微米氧化物、1微米氮化物、10微米氧化物(氮化物＝SixNyHz，氧化物＝SiO2)，但也可以是任何相似的结构。注意开始的50nm氮化物仅仅在氧化物对最后的金属的粘合性差时才需要，而最后的10微米氧化物可以是具有良好机械性质的任何电介质。
用诸如溅射、化学汽相淀积(CVD)之类的标准淀积方法，覆盖层10被淀积在LM层11上。此外，如图2所示，可以淀积导电焊点20。焊点20包含能够淀积和图形化的诸如Al(99.5％)Cu(0.5％)的任何标准金属。焊点20最好包含由50nm的TaN、3微米的Al(99.5％)Cu(0.5％)和100nm的TiN组成的叠层。这样就制备了金属丝键合或C4键合工艺的结构。
标准的最后钝化氧化物/氮化物的厚度通常小于1微米，而覆盖层10的厚度最好大于10微米。厚度比较大的覆盖层10提供了坚固的表面以吸收与金属丝键合、焊料隆起、封装等相关的外力。
图3示出了另一个实施例。在此实施例中，覆盖层30被制作在LM11层处。可以用镶嵌或其它相似的工艺，将LM 11建立在覆盖层30中。在此实施例中，覆盖层30成为最后介电层的一部分。此实施例增加了与最后金属层11共平面的冲击吸收层30。因此，此实施例能够单独用来产生更坚固的结构，其形貌相同，或能够与图2所示的结构组合。如图4所示，LM 11层的厚度可以与覆盖层30相同或更厚。
图5示出了另一个实施例，它包括位于LM-1与LM之间的覆盖层51。这是一种“铆钉”设计，其中LM-1被导电金属(杆)12固定到LM。如图5所示，覆盖层51位于铆钉的基底13与头部11之间。最好用镶嵌工艺来制作覆盖层51和铆钉52结构；但如本公开给定的技术领域的一般熟练人员所知，能够采用任何相似的工艺。最好在制作覆盖层51之后，用标准的金属淀积方法，来制备LM 11和相关的ILD 14。此实施例可能使最后金属12能够被制作在低k电介质中。
如图6所示，本发明的另一个实施例包含覆盖层和支柱结构。支持结构(支柱)60最好由相似于覆盖层61的材料制成。可以借助于腐蚀深的通孔/孔，并用覆盖层61的材料填充孔，来制作支柱60。作为变通，如图7-9所示，借助于在各个层放置材料柱而形成支柱70、80、90，以便建立层叠的块状结构。
建立的各个块可以彼此直接层叠(见图7)、成人字形图形(见图8)、或成台阶状叠层(见图9)。如本技术领域一般熟练人员所知，借助于修正各个连续层的淀积/腐蚀工艺，来控制各个建立的块的位置。
利用这一实施例，支柱结构90可以位于设计要求允许的任何位置，以便不影响BEOL结构。支柱提供了从最后金属焊点表面到硅衬底的坚固的路径。这一坚固的“台面”支持着制作在低k电介质上的最后的金属焊点。
本发明的另一个实施例包含使金属丝键合或C4接合过程中产生的能够损伤易碎的低k介电材料的力得以消散的金属键合焊点设计。如图10所示，本发明的这一实施例包括结构100，它可以是圆形、正方形、或其它形状的金属柱，并位于LM或键合焊点11上方。金属丝键合或C4键合将出现在用来消散或吸收与键合工艺相关的力的这一结构100处。
更具体地说，如图10所示，金属柱100(例如铜、铝或钨)被建立在先期制作的键合焊点11上。如有需要，可以淀积一个界面金属膜/焊点102，以便将柱100固定到LM或键合焊点11。
可以用任何熟知的工艺来制作柱100。例如，可以淀积由牺牲掩蔽材料103组成的膜(例如厚度为0.1-50微米，最好是10微米)。此掩蔽材料103可以是光刻胶、聚酰亚胺、光聚酰亚胺等。可以用光刻和腐蚀方法(干法、湿法)来图形化掩蔽膜103，以便暴露待要放置金属柱100的区域。用溅射或蒸发方法来淀积金属柱100的材料。可以用湿法化学或干法腐蚀方法来清除掩蔽材料103。如图11所示，额外的金属焊点或界面金属110可以增加到金属柱100的顶部，以便得到对键合材料的更好的粘合。此支柱防止了探针通过下一层11凸入到低k电介质中。
图12示出了另一个实施例，它包括建立在BEOL结构130中的网格结构131。网格结构131包含标准的k较高的电介质(例如SiO2、掺P、B、F等的玻璃、SixNyHz、SixCyHz)，并可以被设计成一个或几个BEOL层。本发明可以与BEOL中的不同的介电材料混合和匹配，以尽可能提高ILD和支持网格的所希望的性质。网格线可以构成任何图形。例如，图13示出了一种交错的网格图形，而图14示出了不同电介质的单线。
网格结构131将提高BEOL结构的有效介电常数k，同时还用作坚固的框架，以防止在后续工艺、测试、金属丝键合、焊料球隆起、封装等过程中对易碎的低k电介质131造成损伤。
如本公开给定的技术领域中的一般熟练人员所知，可以用各种常规工艺来构成本实施例。例如，如图15所示，可以淀积由k较高的电介质组成的膜。如图16所示，可以用光刻或其它相似的方法来确定网格结构。如图17和图18分别所示，淀积并整平(例如用化学机械抛光(CMP))或腐蚀低k材料130。作为变通，可以对低k电介质130进行图形化，并可以淀积和整平标准的电介质131。此外，若有需要，可以将硬掩模用于顶部作为腐蚀或CMP停止层。
而且，如图19所示，借助于淀积和图形化低k电介质130(亦即甩涂光刻胶、图形化光刻胶、腐蚀电介质131、剥离光刻胶)，可以构成此实施例。如图20所示，标准的高k等离子体CVD或PVD介电材料131被淀积成与图形共形。如图21所示，用各向异性干法腐蚀方法对标准电介质131进行腐蚀，使标准电介质的侧壁220成为网格。如图22所示，重新淀积更多的低k电介质130以填充此图形，如图23所示，随之以整平腐蚀或CMP。再次可以使用硬掩模作为腐蚀或CMP停止层。
图24所示的另一个实施例是一系列支持C4 251或金属丝键合焊点256的层叠的金属填充形状(例如柱)250。这些金属柱250包括一系列制作在接触252、金属253和通孔层254处的金属柱。利用钨通孔/互连和/或局部互连(亦即BPSG、PSG、SiO2、SixNyHz、SixCyHz等)，制作在接触层252处的开始的柱，被置于浅沟槽隔离(STI)255上或无机电介质上。柱250延续到最后焊点256，提供了焊点结构的机械稳定性。柱被置于使金属丝259能够通过焊点256下方的区域中。于是，如图24所示，本发明不限制金属丝259的性能，还提供了坚固的C4结构251。
金属柱250与双重镶嵌工艺兼容。与金属柱相关的通孔可以是任何尺寸，其直径最好是2微米或更大。除了提供机械强度之外，在制作金属层253的过程中，可以制作金属线257。金属线吸取热量，并通过C4焊点251消散热量。金属线257是延伸超过柱250(设计允许处)的金属线以作为热沉。而且，可以使用棒偏离(例如长度对宽度比率大于2的通孔)来使稳定区最大。如图25所示，可以适当地分隔各个柱，以便得到恰当的机械强度。
图26所示的另一个实施例包括“复合”柱270，它具有用上述方法制作的“楼梯”结构。此“复合”柱270在低k电介质271周围建立一个金属外壳作为标准金属丝和通孔的一部分。图27所示的结构被诸如氮化物层272、氧化物层273和氮化物层274之类的一系列绝缘层覆盖。层275可以是另一种绝缘体、光刻胶、焊点等。
如图27更详细地所示的那样，复合柱270的各个“楼梯”包括被低k电介质282、标准绝缘体(例如SiO2、SixNyHz、SixCyHz等)283以及氮化物SixNyHz、SixCyHz等284组成的交替的层围绕的金属(例如Cu、Al等)台阶部分280和线281(例如Ta、Ti、W，包括氮化的或掺硅的合金等)。注意，结合聚合物低k电介质使用了无机绝缘体283、284，这并非所有低k电介质所要求的。
这些复合柱结构270还能够被用作热沉。如果低k电介质是很差的导热体，则这是很重要的。如表1所示，这些复合柱结构270占用比较小的芯片面积。
表1
实施例柱 @焊点 芯片面积(cm2) 柱面积(μm2) 柱/焊点的数目 柱使用的％M1-M6
图25-26  10000  1  4  20  0.8％
图27-29  10000  1  46  5  2.3％
图28示出了用来从区域291清除低k电介质的光刻胶290。图29示出了图27和28所示的各种结构的相对尺寸的例子。在图29中，光刻胶290和部分氮化物层274被向下腐蚀到点300。然后在图30中，用诸如硬质甩涂玻璃310之类的坚固物质填充窗口291，并在结构上制作焊点311。甩涂玻璃(或其它的坚固材料)增加了柱结构的机械强度。
图31示出了5个柱支持320的俯视图，它可以是诸如图26所示的那种上述的本发明柱中的任何一种。柱320的位置被选择成使结构的强度尽可能高。虽然在图31中示出了一个例子，但如根据本公开的本技术领域熟练人员所知，可以使用不同图形的柱来改变结构的强度。
图32示出了一种柱(例如图26所示的那种柱)的俯视图。例如，甩涂玻璃部分291占据中心，铜部分270围绕甩涂玻璃291，而低k电介质271构成外围部分。
现参照图33和34，示出了使用本发明来消除额外的金属层。更具体地说，图33中的结构包括势垒电介质340(诸如氮化物电介质)、介电层341、342、焊点层343(诸如铜焊点)、以及焊料球C4布线层345。此外，图33所示结构包括焊点层343上的金属层344(例如铝)。金属层344的有凹槽的形状有助于将焊点343保持在势垒电介质340。相反，在图34中，锚定的结构350(例如能够如上述图5所述那样制作的最后金属化和倒数第二金属化层)代替了焊点343和有凹槽的金属化层344。这简化了结构，使之更小和更轻，并缩短了加工时间和复杂性。此外，图34所示的结构包括进一步增强结构的氧化物层351。“根部”352 LM-1层的长度和取向能够被修正以获得不同焊点结构形貌所需的粘合强度。
现参照图35和36，示出了本发明的另一个实施例。更具体地说，图35示出了结构的俯视图，而图36示出了沿图35的A-A线的结构剖面图。在图35和36中，C4结构被示为360，最后的金属化层被示为361，倒数第二金属化层被示为363，而将最后的金属化层361连接到倒数第二金属化层363的杆状通孔被示为362。此外，图36示出了上述实施例讨论的那样利用的各种各样的介电绝缘层364。如在前述实施例中讨论的那样，此结构在最后金属化层361与相邻的电介质之间提供了优异的粘合性。
因此，本发明提供了用来提高最后金属化层与相邻电介质之间的粘合性的许多变通方法。如本公开给定的技术领域的一般熟练人员所知，本发明不局限于上面公开的结构。而是包含利用任何形式的上述支持结构的任何相似的结构。因此，虽然根据最佳实施例已经描述了本发明，但本技术领域熟练人员可以理解，本发明能够以所附权利要求的构思与范围内的修正而加以实施。

Claims (48)

1.一种半导体芯片，它包含：
多个互连金属化层；
所述互连金属化层上的至少一个可形变的介电材料层；
支持结构，它包含耦合到所述可形变的介电材料的比所述可形变的介电材料坚固的电介质；以及
至少一个耦合到所述支持结构的输入/输出键合焊点，
其中所述支持结构对所述焊点进行支持，以避免所述可形变的介电材料破裂。
2.权利要求1的半导体芯片，其中所述支持结构包含所述可形变介电材料层上的覆盖层。
3.权利要求2的半导体芯片，其中所述支持结构包括所述互连金属化层的图形化最后金属层，且所述覆盖层与所述图形化的最后金属层共平面。
4.权利要求2的半导体芯片，其中所述支持结构包括所述互连金属化层的图形化最后金属层，且所述覆盖层的厚度大于所述图形化的最后金属层。
5.权利要求1的半导体芯片，其中所述支持结构包括被所述比所述可形变的介电材料坚固的电介质分隔的图形化的金属层，所述图形化的金属层被多个通过所述坚固的电介质的金属连接连在一起。
6.权利要求1的半导体芯片，其中所述支持结构包括从所述互连金属化层的最后金属层延伸进入所述可形变的介电材料层的金属支柱结构。
7.权利要求6的半导体芯片，其中所述金属支柱结构包含多个逐层制作在所述可形变的介电材料层中的金属块。
8.权利要求7的半导体芯片，其中所述金属块组成人字形图形剖面。
9.权利要求7的半导体芯片，其中所述金属块组成台阶形剖面结构。
10.一种集成电路芯片，它包含：
逻辑电路；
覆盖所述逻辑电路的外部绝缘体；以及
所述绝缘体上的电连接到所述逻辑电路的接触，
其中所述外部绝缘体包括：
具有第一介电常数的第一介电层；以及
耦合到所述第一介电层的支持结构，其包括具有比所述第一介电常数高的第二介电常数的电介质。
11.权利要求10的集成电路芯片，其中所述支持结构包含所述第一介电层上的覆盖层。
12.权利要求11的集成电路芯片，其中所述外部绝缘体上具有图形化的最后金属层，且所述覆盖层与所述图形化的最后金属层共平面。
13.权利要求11的集成电路芯片，其中所述外部绝缘体上具有图形化的最后金属层，且所述覆盖层的厚度大于所述图形化的最后金属层。
14.权利要求10的集成电路芯片，其中进一步包括位于所述支持结构之中的被具有所述第二介电常数的第二介电层分隔的图形化的金属层，所述图形化的金属层被多个通过所述第二介电层的金属连接连在一起。
15.权利要求10的集成电路芯片，其中所述支持结构之中还包括：
具有所述第二介电常数且包括图形化的最后金属层的第二介电层；以及
从所述最后金属层延伸进入所述第一电介质的金属支柱结构。
16.权利要求15的集成电路芯片，其中所述金属支柱结构包含多个逐层制作在所述第一电介质中的金属块。
17.权利要求16的集成电路芯片，其中所述金属块组成人字形图形剖面。
18.权利要求16的集成电路芯片，其中所述金属块组成台阶形剖面结构。
19.一种集成电路芯片，它包含：
逻辑电路；
覆盖所述逻辑电路的外部绝缘体；以及
所述绝缘体上的能够电连接到所述逻辑电路的接触，
其中所述接触包含延伸在所述外部绝缘体上的金属结构。
20.权利要求19的集成电路芯片，其中所述金属结构具有圆柱形形状。
21.权利要求19的集成电路芯片，其中所述金属结构具有正方形柱形形状。
22.一种集成电路芯片，它包含：
逻辑电路；
覆盖所述逻辑电路的外部绝缘体；以及
所述绝缘体上的电连接到所述逻辑电路的接触，
其中所述外部绝缘体具有网格结构，它包括具有第一介电常数的第一电介质和具有比所述第一介电常数高的第二介电常数的第二电介质。
23.权利要求22的集成电路芯片，其中所述网格结构包含所述第二电介质在所述第一介电层中的交错图形。
24.权利要求22的集成电路芯片，其中所述网格结构包含所述第一电介质和所述第二电介质组成的交替层。
25.权利要求22的集成电路芯片，其中所述网格结构包含所述各个第一电介质部分之间的所述第二电介质的侧壁间隔。
26.一种集成电路芯片，它包含：
逻辑电路；
覆盖所述逻辑电路的外部绝缘体；以及
所述外部绝缘体上的电连接到所述逻辑电路的接触，
其中所述外部绝缘体包括所述逻辑电路与所述接触之间的支持柱。
27.权利要求26的集成电路芯片，其中所述支持柱包含所述外部绝缘体中的部分金属化和通孔层。
28.权利要求26的集成电路芯片，其中所述支持柱被隔开，使布线能够位于所述外部绝缘体中。
29.权利要求26的集成电路芯片，其中所述支持柱包含用绝缘体填充的复合金属柱。
30.权利要求26的集成电路芯片，其中所述支持柱包含热沉。
31.一种制造半导体芯片的方法，所述方法包含：
制作多个互连金属化层；
制作所述互连金属化层上的至少一个可形变的介电材料层；
制作支持结构，它包含耦合到所述可形变的介电材料的比所述可形变的介电材料坚固的电介质；以及
制作至少一个输入/输出键合焊点，
其中所述支持结构被制作成对所述焊点进行支持，以避免所述可形变的介电材料破裂。
32.权利要求31的方法，其中所述支持结构的所述制作包含制作所述可形变介电材料层上的覆盖层。
33.权利要求32的方法，其中所述支持结构的所述制作包括制作所述互连金属化层的图形化最后金属层，使所述覆盖层与所述图形化的最后金属层共平面。
34.权利要求32的方法，其中所述支持结构的所述制作包括制作所述互连金属化层的图形化最后金属层，使所述覆盖层的厚度大于所述图形化的最后金属层。
35.权利要求31的方法，其中所述支持结构的所述制作包括制作被比所述可形变的介电材料坚固的电介质分隔的图形化的金属层，使所述图形化的金属层被通过所述坚固的电介质的多个金属连接连在一起。
36.权利要求31的方法，其中所述支持结构的所述制作包括制作从所述互连金属化层的最后金属层延伸进入所述可形变的介电材料层的金属支柱结构。
37.权利要求36的方法，其中所述金属支柱结构的所述制作包含在所述可形变的介电材料层中逐层制作多个金属块。
38.权利要求37的方法，其中所述金属块被制作成人字形图形剖面。
39.权利要求37的方法，其中所述金属块被制作成台阶形剖面结构。
40.一种制作集成电路芯片的方法，它包含：
制作逻辑电路；
制作覆盖所述逻辑电路的外部绝缘体；以及
制作所述绝缘体上的电连接到所述逻辑电路的接触，
其中所述外部绝缘体的所述制作包括：
制作具有第一介电常数的第一介电层；以及
制作具有比所述第一介电常数高的第二介电常数的支持结构，所述支持结构与第一介电质相耦合。
41.权利要求40的方法，其中所述支持结构的所述制作包含制作所述第一介电层上的覆盖层。
42.权利要求41的方法，其中进一步包括在所述外部绝缘体之中制作所述第一介电层上的图形化的最后金属层，使所述覆盖层与所述图形化的最后金属层共平面。
43.权利要求41的方法，其中进一步包括在所述外部绝缘体之中制作所述第一介电层上的图形化的最后金属层，使所述覆盖层的厚度大于所述图形化的最后金属层的厚度。
44.权利要求40的方法，其中进一步包括在所述支持结构之中制作被所述第一介电层上的具有所述第二介电常数的第二介电层分隔的图形化的金属层，使所述图形化的金属层被通过所述第二介电层的多个金属连接连在一起。
45.权利要求40的方法，其中进一步包括在所述支持结构之中：
制作具有所述第二介电常数且包括图形化的最后金属层的第二介电层；以及
制作从所述最后金属层延伸进入所述第一电介质的金属支柱结构。
46.权利要求45的方法，其中所述金属支柱结构的所述制作包含在所述第一电介质中逐层制作多个金属块。
47.权利要求46的方法，其中所述金属块被制作成人字形图形剖面。
48.权利要求46的方法，其中所述金属块被制作成台阶形剖面结构。
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