CN118351781A - 像素电路和显示装置 - Google Patents

像素电路和显示装置 Download PDF

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Publication number
CN118351781A
CN118351781A CN202410550146.7A CN202410550146A CN118351781A CN 118351781 A CN118351781 A CN 118351781A CN 202410550146 A CN202410550146 A CN 202410550146A CN 118351781 A CN118351781 A CN 118351781A
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CN
China
Prior art keywords
transistor
gate
coupled
electrode coupled
gate electrode
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Pending
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CN202410550146.7A
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English (en)
Inventor
金东辉
金那英
金喆镐
李王枣
全珍
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of CN118351781A publication Critical patent/CN118351781A/zh
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
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Abstract

本公开涉及像素电路和显示装置，所述像素电路包括第一晶体管至第三晶体管、存储电容器和发光元件。所述第一晶体管包括第一电极、耦接到第二节点的第二电极、耦接到第一节点的第一栅电极和直接耦接到所述第二节点的第二栅电极。所述第二晶体管包括耦接到数据线的第一电极、耦接到所述第一节点的第二电极和耦接到第一扫描线的第一栅电极。所述第三晶体管包括耦接到第三电源线的第一电极、耦接到所述第一节点的第二电极和耦接到基准扫描线的第一栅电极。所述存储电容器耦接在所述第二节点与所述第一节点之间。所述发光元件耦接到所述第二节点。

Description

像素电路和显示装置
本申请是申请日为2020年4月26日、申请号为202010337624.8、发明名称为“像素电路和显示装置”的发明专利申请的分案申请。
技术领域
本发明构思的示例性实施例涉及像素电路和包括该像素电路的显示装置。
背景技术
像素包括发光元件和配置为将与数据信号对应的电流传输到发光元件的晶体管(或多个晶体管)。
晶体管的阈值电压具有变化，并且还可以根据用途而变化。因此，包括像素的显示装置可以通过各种补偿技术(例如，内部补偿技术、外部补偿技术等)补偿像素中的晶体管的阈值电压。例如，当显示装置使用内部补偿技术时，显示装置可以在像素中写入数据信号的同时补偿晶体管的阈值电压。
随着包括像素的显示装置的分辨率增加或者显示装置的驱动频率增加，用于补偿像素中的晶体管的阈值电压的补偿时间可能变得不足。
发明内容
本公开提供一种像素电路和显示装置，可以自由地调整阈值电压的补偿时间，并且可以更充分地确保阈值电压的补偿时间。
根据本发明构思的示例性实施例，像素电路可以包括：第一电源线、第二电源线、第三电源线和第四电源线；数据线，配置为传输数据信号；第一扫描线和第二扫描线，配置为依次传输第一栅极信号；基准扫描线，配置为传输第二栅极信号；发光控制线，配置为传输第三栅极信号；第一晶体管，包括第一电极、耦接到第二节点的第二电极、耦接到第一节点的栅电极和耦接到第二节点的背栅电极；第二晶体管，包括耦接到数据线的第一电极、耦接到第一节点的第二电极和耦接到第一扫描线的栅电极；第三晶体管，包括耦接到第三电源线的第一电极、耦接到第一节点的第二电极和耦接到基准扫描线的栅电极；第四晶体管，包括耦接到第二节点的第一电极、耦接到第四电源线的第二电极和耦接到第二扫描线的栅电极；第五晶体管，包括耦接到第一电源线的第一电极、耦接到第一晶体管的第一电极的第二电极和耦接到发光控制线的栅电极；电容器，耦接在第二节点与第一节点之间；以及发光元件，耦接到第二节点和第二电源线。
第一晶体管的背栅电极可以设置为与第一晶体管的栅电极重叠，绝缘层介于第一晶体管的背栅电极与第一晶体管的栅电极之间。
第一晶体管至第四晶体管中的每一个可以包括氧化物半导体，并且第五晶体管可以包括硅半导体。
第一晶体管至第五晶体管中的每一个的栅电极可以设置在半导体上。
第一晶体管的背栅电极和第五晶体管的栅电极可以设置在同一层上。
第二晶体管还可以包括耦接到第二晶体管的栅电极的背栅电极。
第三晶体管还可以包括耦接到第三晶体管的栅电极的背栅电极。
第四晶体管还可以包括耦接到第四晶体管的栅电极的背栅电极。
在第一区间中，第三晶体管可以响应于具有导通电压电平的第二栅极信号而导通，并且第四晶体管可以响应于具有导通电压电平的第一栅极信号而导通。
在第二区间中，第五晶体管可以响应于具有导通电压电平的第三栅极信号而导通，并且第四晶体管可以截止，并且第二区间可以与第一区间不同并且比第一区间长。
在第三区间中，第二晶体管可以响应于具有导通电压电平的第一栅极信号而导通，并且数据信号可以被写入电容器中。第三区间可以与第一区间和第二区间不同，并且可以具有与第一区间的宽度相同的宽度。
在第四区间中，第五晶体管可以响应于具有导通电压电平的第三栅极信号而导通，并且发光元件可以以与数据信号对应的亮度发光。
第一区间至第四区间可以被包括在第一帧中，第二晶体管至第四晶体管可以在继第一帧之后的第二帧中保持截止状态，并且第二帧中的当第五晶体管截止时的第一时段可以比第一帧中的当第五晶体管截止时的第二时段长。
第二帧中的当发光元件可以发光时的时段可以与第一帧中的当发光元件可以发光时的时段基本相同。
根据本发明构思的示例性实施例，显示装置可以包括：显示器，包括第一电源线、第二电源线、第三电源线、第四电源线、数据线、第一扫描线、第二扫描线、基准扫描线、发光控制线和像素；数据驱动器，配置为将数据信号供应到数据线；以及栅极驱动器，配置为将第一栅极信号依次供应到第二扫描线和第一扫描线，将第二栅极信号供应到基准扫描线以及将第三栅极信号供应到发光控制线。像素可以包括：第一晶体管，包括第一电极、耦接到第二节点的第二电极、耦接到第一节点的栅电极和耦接到第二节点的背栅电极；第二晶体管，包括耦接到数据线的第一电极、耦接到第一节点的第二电极和耦接到第一扫描线的栅电极；第三晶体管，包括耦接到第三电源线的第一电极、耦接到第一节点的第二电极和耦接到基准扫描线的栅电极；第四晶体管，包括耦接到第二节点的第一电极、耦接到第四电源线的第二电极和耦接到第二扫描线的栅电极；第五晶体管，包括耦接到第一电源线的第一电极、耦接到第一晶体管的第一电极的第二电极和耦接到发光控制线的栅电极；电容器，耦接在第二节点与第一节点之间；以及发光元件，耦接到第二节点和第二电源线。
在第一区间中，栅极驱动器可以将具有导通电压电平的第二栅极信号供应到基准扫描线，并且可以将具有导通电压电平的第一栅极信号供应到第二扫描线。
在第二区间中，栅极驱动器可以将具有导通电压电平的第三栅极信号供应到发光控制线，并且可以将具有截止电压电平的第一栅极信号供应到第二扫描线，并且第二区间可以与第一区间不同，并且可以比第一区间长。
在第三区间中，栅极驱动器可以将具有导通电压电平的第一栅极信号供应到第一扫描线，第三区间可以与第一区间和第二区间不同，并且可以具有与第一区间的宽度相同的宽度。
在第四区间中，栅极驱动器可以将具有导通电压电平的第三栅极信号供应到发光控制线，并且发光元件可以以与数据信号对应的亮度发光。
第一区间至第四区间可以被包括在第一帧中，第二晶体管至第四晶体管可以在继第一帧之后的第二帧中保持截止状态，并且第二帧中的当第五晶体管截止时的第一时段可以比第一帧中的当第五晶体管截止时的第二时段长。
根据本发明构思的示例性实施例，像素可以包括：基底；缓冲层，设置在基底上；第一绝缘层至第五绝缘层，依次设置在缓冲层上；第一半导体图案，设置在缓冲层上；第一栅电极，设置在第一绝缘层上；背栅电极，设置在第一绝缘层上；第二半导体图案，设置在第二绝缘层上；第二栅电极，设置在第三绝缘层上；电源线，设置在第四绝缘层上并通过穿过第一绝缘层至第四绝缘层的接触孔接触第一半导体图案；第一桥接图案，设置在第四绝缘层上，通过穿过第一绝缘层至第四绝缘层的接触孔接触第一半导体图案，并通过穿过第三绝缘层和第四绝缘层的接触孔接触第二半导体图案；以及第二桥接图案，设置在第四绝缘层上，通过穿过第三绝缘层和第四绝缘层的接触孔接触第二半导体图案，并通过穿过第二绝缘层至第四绝缘层的接触孔接触背栅电极。
附图说明
通过参照附图详细地描述本发明构思的示例性实施例，将更全面地理解本发明构思的以上和其他特征。
图1是示出根据本发明构思的示例性实施例的显示装置的框图。
图2是示出根据本发明构思的示例性实施例的在图1的显示装置中包括的像素的电路图。
图3是示出根据本发明构思的示例性实施例的沿着图2的线I-I’截取的像素的剖视图。
图4是示出根据本发明构思的示例性实施例的在图2的像素中测量的信号的波形图。
图5A至图5D是示出根据本发明构思的示例性实施例的根据图4的波形图的像素的操作的电路图。
图6是示出根据本发明构思的示例性实施例的在图2的像素中测量的信号的波形图。
图7A至图7C是示出根据本发明构思的示例性实施例的在图1的显示装置中包括的像素的电路图。
具体实施方式
本发明构思的示例性实施例涉及能够更充分地确保用于补偿晶体管的阈值电压的补偿时间的像素电路和显示装置。
在下文中，将参照附图更充分地描述本发明构思的示例性实施例。在整个本申请中，同样的附图标记可以指代同样的元件。
图1是示出根据本发明构思的示例性实施例的显示装置的框图。
参照图1，显示装置100可以包括显示器110、栅极驱动器120、数据驱动器(或源极驱动器)130和时序控制器140。
显示器110可以包括栅极线GL1至GLn、GRL1至GRLn和EL1至ELn(其中，n是正整数)、数据线DL1至DLm(其中，m是正整数)以及像素PX。显示器110还可以包括电源线(例如，第一电源线至第四电源线)。栅极线GL1至GLn、GRL1至GRLn和EL1至ELn可以包括扫描线GL1至GLn、基准扫描线GRL1至GRLn和发光控制线EL1至ELn。像素PX可以设置在由栅极线GL1至GLn、GRL1至GRLn和EL1至ELn以及数据线DL1至DLm界定的区域(例如，像素区域)中。
像素PX可以耦接到扫描线GL1至GLn中的至少一条、基准扫描线GRL1至GRLn中的一条、发光控制线EL1至ELn中的一条以及数据线DL1至DLm中的一条。例如，像素PX可以耦接到第i条扫描线GLi、第i条基准扫描线GRLi、第i条发光控制线ELi和第j条数据线DLj(其中，i和j是正整数)。
像素PX可以响应于通过第i条扫描线GLi提供的第一栅极信号写入通过第j条数据线DLj提供的数据信号，响应于通过第i条基准扫描线GRLi提供的第二栅极信号补偿数据信号(例如，补偿由像素PX中的晶体管的阈值电压导致的误差)，并且响应于通过第i条发光控制线ELi提供的第三栅极信号以与被补偿的数据信号对应的亮度发光。
像素PX的配置将参照图2在下文描述。
栅极驱动器120可以基于栅极控制信号GCS生成第一栅极信号(或第一扫描信号)、第二栅极信号(或第二扫描信号)或第三栅极信号(或发光控制信号)，将第一栅极信号依次提供给扫描线GL1至GLn，将第二栅极信号依次提供给基准扫描线GRL1至GRLn，并且将第三栅极信号依次或同时提供给发光控制线EL1至ELn。此处，栅极控制信号GCS可以包括开始信号或时钟信号等，并且可以从时序控制器140提供。例如，栅极驱动器120可以包括移位寄存器，该移位寄存器使用时钟信号依次生成或输出与开始信号的脉冲类型对应的第一栅极信号、第二栅极信号或第三栅极信号的脉冲类型。
尽管已经描述了栅极驱动器120生成全部第一栅极信号至第三栅极信号，但是栅极驱动器120不限于此。例如，栅极驱动器120可以包括生成第一栅极信号的第一栅极驱动电路(或第一扫描驱动器)、生成第二栅极信号的第二栅极驱动电路(或第二扫描驱动器)以及生成第三栅极信号的第三栅极驱动电路(或发光驱动器)。
根据本发明构思的示例性实施例，栅极驱动器120可以生成独立于第一栅极信号的第二栅极信号，并且第二栅极信号的脉冲宽度可以被设置或调整为与第一栅极信号的脉冲宽度不同。例如，具有用于使像素PX中的晶体管导通的导通电压电平的第二栅极信号的宽度可以大于具有导通电压电平的第一栅极信号的宽度。因此，当第二栅极信号用于补偿像素PX中的晶体管的阈值电压时，能够调整并更充分地确保用于补偿晶体管的阈值电压的补偿时间。
第一栅极信号和第二栅极信号将参照图4在下文描述。
数据驱动器130可以基于从时序控制器140提供的图像数据DATA2和数据控制信号DCS生成数据信号，并且可以向显示器110(或像素PX)提供数据信号。此处，数据控制信号DCS是用于控制数据驱动器130的操作的信号，并且可以包括用于指示有效数据信号的输出的负载信号(或数据使能信号)。
时序控制器140可以从外部装置(例如，图形处理器)接收输入图像数据DATA1和控制信号CS，基于控制信号CS生成栅极控制信号GCS和数据控制信号DCS，并且转换输入图像数据DATA1以生成图像数据DATA2。例如，时序控制器140可以将以RGB格式的输入图像数据DATA1转换为以符合显示器110中的像素阵列的PenTile(例如，RGBG)格式的图像数据DATA2。
显示器110可以供应有电源电压VDD、VSS、Vref和Vint。电源电压VDD、VSS、Vref和Vint是操作像素PX所需的电压。例如，第一电源电压VDD可以具有比第二电源电压VSS的电压电平高的电压电平。电源电压VDD、VSS、Vref和Vint将参照图2在下文描述。
栅极驱动器120、数据驱动器130和时序控制器140中的至少一个可以设置于显示器110上，或者可以被实现为集成电路(IC)，以便以带载封装的形式耦接到显示器110。可替代地，栅极驱动器120、数据驱动器130和时序控制器140中的至少两个可以被实现为单个IC。
图2是示出了根据本发明构思的示例性实施例的在图1的显示装置中包括的像素的电路图。
参照图2，像素PX可以耦接到第一电源线PL1、第二电源线PL2、第三电源线PL3、第四电源线PL4、第一扫描线GL1、第二扫描线GL2、基准扫描线GRL、发光控制线EL和数据线DL。第一电源线PL1可以传输第一电源电压VDD，第二电源线PL2可以传输第二电源电压VSS，第三电源线PL3可以传输第三电源电压Vref(或基准电压)，并且第四电源线PL4可以传输第四电源电压Vint(或初始化电压)。第一扫描线GL1和第二扫描线GL2(或先前扫描线)可以被包括在参照图1描述的扫描线GL1至GLn中。第一栅极信号可以在第一扫描线GL1之前被供应到第二扫描线GL2。基准扫描线GRL(或基准扫描线)可以被包括在参照图1描述的基准扫描线GRL1至GRLn中，并且发光控制线EL可以被包括在参照图1描述的发光控制线EL1至ELn中。数据线DL可以被包括在参照图1描述的数据线DL1至DLm中。
像素PX(或像素电路)可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、电容器Cst和发光元件LD。发光元件LD可以具有寄生电容器Cpar(或寄生电容)。
第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4中的每一个可以是N型晶体管，而第五晶体管T5可以是P型晶体管。例如，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4中的每一个可以包括氧化物半导体，并且第五晶体管T5可以包括硅半导体(例如，低温多晶硅(LTPS))。
第一晶体管T1(或驱动晶体管)可以包括第一电极、耦接到第二节点N2的第二电极、耦接到第一节点N1的栅电极以及耦接到第二节点N2的背栅(back-gate)电极。此处，背栅电极可以设置为与栅电极重叠，绝缘层介于背栅电极和栅电极之间，背栅电极可以形成晶体管的主体，并且可以用作栅电极。换言之，第一晶体管T1可以被实现为还包括背栅电极的背栅晶体管。背栅晶体管将参照图3在下文描述。
由于第一晶体管T1的背栅电极耦接到第二节点N2，因此当像素PX发光时，第一晶体管T1的第二电极(例如，源电极)的电压变化也可以被传送到栅电极的电压变化。因此，可以保持将在下文描述的通过补偿操作设置的第一晶体管T1的第二电极与栅电极之间的电压(例如，栅源电压)，并且像素PX可以以期望的亮度发光。
第二晶体管T2(或开关晶体管)可以包括耦接到数据线DL的第一电极、耦接到第一节点N1的第二电极、耦接到第一扫描线GL1的栅电极以及耦接到第一扫描线GL1(或栅电极)的背栅电极。换言之，第二晶体管T2可以被实现为背栅晶体管。
由于第二晶体管T2的背栅电极耦接到第一扫描线GL1，因此第二晶体管T2可以具有双栅晶体管的结构，并且可以更精确地执行开关操作。因此，即使第二晶体管T2的导通时段变短，也可以将数据信号Vdata更精确地传输到第一节点N1。
第三晶体管T3(或补偿晶体管)可以包括耦接到第三电源线PL3的第一电极、耦接到第一节点N1的第二电极以及耦接到基准扫描线GRL的栅电极。
第四晶体管T4(或初始化晶体管)可以包括耦接到第二节点N2的第一电极、耦接到第四电源线PL4的第二电极以及耦接到第二扫描线GL2的栅电极。
第五晶体管T5(或发光晶体管)可以包括耦接到第一电源线PL1的第一电极、耦接到第一晶体管T1的第一电极的第二电极以及耦接到发光控制线EL的栅电极。
电容器Cst(或存储电容器)可以耦接在第一节点N1与第二节点N2之间。
发光元件LD可以耦接在第二节点N2与第二电源线PL2之间，并且可以以与经由第一晶体管T1供应的电流(或驱动电流)对应的亮度发光。发光元件LD可以被实现为有机发光二极管，但不限于此。换言之，发光元件LD可以被实现为无机发光二极管或多个无机发光二极管。
像素PX的操作将参照图4在下文描述。
图3是示出了根据本发明构思的示例性实施例的沿着图2的线I-I’截取的像素的剖视图。图3示出了在图2的像素PX中包括的第一晶体管T1和第五晶体管T5。
参照图3，像素PX可以包括基底SUB、缓冲层BUF、绝缘层INS1、INS2、INS3、INS4和INS5、半导体图案SC1和SC2以及导电图案GAT1、GAT2、BML、BRP1、BRP2和PL1。
基底SUB可以形成像素PX(或显示装置100)的基体构件。基底SUB可以是刚性基底或柔性基底，并且基底SUB的材料或性质不受具体限制。例如，基底SUB可以是由玻璃或强化玻璃制成的刚性基底，或者由塑料或金属制成的薄膜形成的柔性基底。此外，基底SUB可以是透明基底，但基底SUB不限于此。例如，基底SUB可以是半透明基底、不透明基底或反射基底。
缓冲层BUF可以设置在基底SUB上，并且缓冲层BUF可以防止杂质扩散到电路装置中。缓冲层BUF可以由单层形成，或者可以由具有至少两层或更多层的多层形成。如果缓冲层BUF具有多层结构，则这些层可以由相同的材料或不同的材料形成。在本发明构思的示例性实施例中，可以省略缓冲层BUF。
绝缘层INS1、INS2、INS3、INS4和INS5可以依次设置在基底SUB(或缓冲层BUF)上，并且可以包括第一绝缘层INS1(或第一栅极绝缘层)、第二绝缘层INS2(或第一层间绝缘层)、第三绝缘层INS3(或第二栅极绝缘层)、第四绝缘层INS4(或第二层间绝缘层)和第五绝缘层INS5(或钝化层)。
绝缘层INS1、INS2、INS3、INS4和INS5中的每一个可以由单层或多层形成，并且可以包含至少一种无机绝缘材料和/或有机绝缘材料。例如，绝缘层INS1、INS2、INS3、INS4和INS5中的每一个可以包括本领域技术人员目前已知的各种有机/无机绝缘材料，诸如氮化硅(SiNx)，并且绝缘层INS1、INS2、INS3、INS4和INS5中的每一个不限于特定材料。此外，绝缘层INS1、INS2、INS3、INS4和INS5可以包括不同的绝缘材料，或者绝缘层INS1、INS2、INS3、INS4和INS5中的至少一些可以包括相同的绝缘材料。
半导体图案SC1和SC2可以包括第一半导体图案SC1和第二半导体图案SC2，并且导电图案GAT1、GAT2、BML、BRP1、BRP2和PL1可以包括第一栅电极GAT1(或第一栅电极图案)、背栅电极BML(或背栅电极图案)、第二栅电极GAT2(或第二栅电极图案)、第一桥接图案BRP1、第二桥接图案BRP2和第一电源线PL1(或第一导电图案)。
第一栅电极GAT1、背栅电极BML、第二栅电极GAT2、第一桥接图案BRP1、第二桥接图案BRP2和第一电源线PL1中的每一个可以包括至少一种导电材料，诸如Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr、Ti或它们的合金，但不限于此。
第一半导体图案SC1可以设置在缓冲层BUF上。例如，第一半导体图案SC1可以介于缓冲层BUF与第一绝缘层INS1之间。第一半导体图案SC1可以包括与第五晶体管T5的第一晶体管电极ET1接触的第一区域、与第五晶体管T5的第二晶体管电极ET2接触的第二区域以及设置在第一区域与第二区域之间的沟道区域。第一区域和第二区域中的一个可以是源极区域，并且另一个可以是漏极区域。
第一半导体图案SC1可以是由多晶硅、非晶硅、LTPS等形成的半导体图案。第一半导体图案SC1的沟道区域可以是作为未掺杂有杂质的半导体图案的本征半导体。第一半导体图案SC1的第一区域和第二区域中的每一个可以是掺杂有预定的杂质的半导体图案。
第一栅电极GAT1可以设置在第一绝缘层INS1上。例如，第一栅电极GAT1可以设置在第一绝缘层INS1与第二绝缘层INS2之间。第一栅电极GAT1可以与第一半导体图案SC1的至少一个区域重叠。
第一栅电极GAT1、第一半导体图案SC1以及第一晶体管电极ET1和第二晶体管电极ET2(例如，第一晶体管电极ET1和第二晶体管电极ET2与第一半导体图案SC1接触)可以构成第五晶体管T5。
背栅电极BML可以设置在第一绝缘层INS1上。换言之，背栅电极BML可以设置在与第一栅电极GAT1相同的层上。
第二半导体图案SC2可以设置在第二绝缘层INS2上。例如，第二半导体图案SC2可以设置在第二绝缘层INS2与第三绝缘层INS3之间。第二半导体图案SC2可以包括与第一晶体管T1的第一晶体管电极ET1接触的第一区域、与第一晶体管T1的第二晶体管电极ET2接触的第二区域以及设置在第一区域与第二区域之间的沟道区域。第一区域和第二区域中的一个可以是源极区域，并且另一个可以是漏极区域。
第二半导体图案SC2可以是由氧化物半导体等制成的半导体图案。第二半导体图案SC2的沟道区域可以是作为未掺杂有杂质的半导体图案的本征半导体。第二半导体图案SC2的第一区域和第二区域中的每一个可以是掺杂有预定的杂质的半导体图案。
第二半导体图案SC2可以设置为与背栅电极BML重叠，并且背栅电极BML可以与第二半导体图案SC2的至少一个区域重叠。
第二栅电极GAT2可以设置在第三绝缘层INS3上。例如，第二栅电极GAT2可以设置在第三绝缘层INS3与第四绝缘层INS4之间。第二栅电极GAT2可以与第二半导体图案SC2的至少一个区域重叠。
第二栅电极GAT2、第二半导体图案SC2以及第一晶体管电极ET1和第二晶体管电极ET2(例如，第一晶体管电极ET1和第二晶体管电极ET2与第二半导体图案SC2接触)以及背栅电极BML可以构成第一晶体管T1。
第一桥接图案BRP1、第二桥接图案BRP2和第一电源线PL1可以设置在第四绝缘层INS4上。
第一桥接图案BRP1可以通过穿过第三绝缘层INS3和第四绝缘层INS4的接触孔与第二半导体图案SC2的一个区域接触，并且可以构成第一晶体管T1的第二晶体管电极ET2。此外，第一桥接图案BRP1可以通过穿过第一绝缘层INS1至第四绝缘层INS4的接触孔与第一半导体图案SC1的一个区域接触，并且可以构成第五晶体管T5的第一晶体管电极ET1。如参照图2所描述的，第一桥接图案BRP1可以将第一晶体管T1的第一电极与第五晶体管T5的第二电极耦接。
第二桥接图案BRP2可以通过穿过第三绝缘层INS3和第四绝缘层INS4的接触孔与第二半导体图案SC2的一个区域接触，并且可以构成第一晶体管T1的第一晶体管电极ET1。此外，第二桥接图案BRP2可以通过穿过第二绝缘层INS2至第四绝缘层INS4的接触孔与背栅电极BML接触。背栅电极BML可以通过第二桥接图案BRP2耦接到第一晶体管T1的第一晶体管电极ET1。
第二桥接图案BRP2可以与形成在第五绝缘层INS5上的发光元件LD(参见图2)耦接，并且可以构成参照图2描述的第二节点N2。
第一电源线PL1可以通过穿过第一绝缘层INS1至第四绝缘层INS4的接触孔与第一半导体图案SC1的一个区域接触，并且可以构成第五晶体管T5的第二晶体管电极ET2。
尽管图3示出了将第三绝缘层INS3完全设置在第二绝缘层INS2上，但是本发明构思不限于此。例如，第三绝缘层INS3可以仅设置在第二半导体图案SC2的一个区域(例如，沟道区域)上。
此外，尽管图3示出了第一晶体管T1和第五晶体管T5中的每一个具有顶栅结构(例如，其中栅电极设置在半导体层上的结构)，但是本发明构思不限于此。例如，第一晶体管T1和第五晶体管T5中的至少一个可以具有底栅结构。
图4是示出了根据本发明构思的示例性实施例的在图2的像素中测量的信号的波形图。图4示出了在图2的第一扫描线GL1中测量的第一栅极信号GW[N]、在第二扫描线GL2中测量的先前栅极信号GI[N]、在基准扫描线GRL中测量的第二栅极信号GR[N]以及在发光控制线EL中测量的第三栅极信号EM[N]。图5A至图5D是示出了根据本发明构思的示例性实施例的根据图4的波形图的像素的操作的电路图。图5A至图5D示意性地示出了根据图4的波形图的像素的操作。
首先，参照图2至图4，在第一时间t1(或在第一时间点)，第三栅极信号EM[N]可以从导通电压电平转换为截止电压电平。此处，导通电压电平可以是使像素PX中的晶体管T1至T5导通所在的电压电平，而截止电压电平可以是使像素PX中的晶体管T1至T5截止所在的电压电平。例如，由于将第五晶体管T5实现为P型晶体管，因此第三栅极信号EM[N]的导通电压电平可以具有逻辑低电平(或低电压电平)，并且第三栅极信号EM[N]的截止电压电平可以具有逻辑高电平(或高电压电平)。例如，由于将第一晶体管T1至第四晶体管T4中的每一个实现为N型晶体管，因此第一栅极信号GW[N]、先前栅极信号GI[N]和第二栅极信号GR[N]的导通电压电平可以具有逻辑高电平(或高电压电平)，并且第一栅极信号GW[N]、先前栅极信号GI[N]和第二栅极信号GR[N]的截止电压电平可以具有逻辑低电平(或低电压电平)。
第五晶体管T5可以响应于具有截止电压电平的第三栅极信号EM[N]而截止。
先前栅极信号GI[N]、第二栅极信号GR[N]和第一栅极信号GW[N]中的每一个都可以具有截止电压电平。响应于具有截止电压电平的先前栅极信号GI[N]、第二栅极信号GR[N]以及第一栅极信号GW[N]，第二晶体管T2、第三晶体管T3和第四晶体管T4中的每一个可以保持截止状态。因此，像素PX可以不发光或进入不发光区间。
接下来，在第二时间t2，第二栅极信号GR[N]可以被转换为导通电压电平。第二时间t2可以是从第一时间t1开始已流逝了一个水平时间(1H)的时间。在这种情况下，如图5A中所示，响应于导通电压电平的第二栅极信号GR[N]，第三晶体管T3可以导通，并且第一节点N1(或者第一晶体管T1的栅电极)可以被第三电源电压Vref初始化。
紧接在第二时间t2之后，先前栅极信号GI[N]可以被转换为导通电压电平。在这种情况下，如图5A中所示，响应于具有导通电压电平的先前栅极信号GI[N]，第四晶体管T4可以导通，并且第二节点N2(例如，第一晶体管T1的第二电极或电容器Cst)可以被第四电源电压Vint初始化。第三电源电压Vref与第四电源电压Vint之间的电压差可以大于第一晶体管T1的阈值电压。
接下来，在第三时间t3或者紧接在第三时间t3之前，先前栅极信号GI[N]可以被转换为截止电压电平。换言之，先前栅极信号GI[N]可以具有大约一个水平时间(1H)的导通电压电平。在第二时间t2与第三时间t3之间的第一区间P1(例如，其中先前栅极信号GI[N]具有导通电压电平的区间或第一时段)可以被称为初始化区间。
在第四时间t4，第三栅极信号EM[N]可以被转换为导通电压电平。在这种情况下，如图5B中所示，响应于导通电压电平的第三栅极信号EM[N]，第五晶体管T5可以导通，并且第一晶体管T1的第一电极(例如，漏电极)可以耦接到第一电源线PL1。因为将第三电源电压Vref施加到第一节点N1，所以在第一晶体管T1中，电流可以流向第一电源线PL1。因此，第一晶体管T1的第二电极(源电极或第二节点N2)的电压电平可以被降低，并且与第一晶体管T1的阈值电压Vth对应的电压可以被存储在电容器Cst中。第一晶体管T1的第二电极(源电极或第二节点N2)可以具有与第三电源电压Vref和阈值电压Vth之间的电压差Vref-Vth基本相同的电平。
在第五时间t5，第三栅极信号EM[N]可以被转换为截止电压电平。第五时间t5可以是从第四时间t4开始已流逝了三个水平时间(3H)的时间。在这种情况下，像素PX可以在三个水平时间(3H)期间补偿第一晶体管T1的阈值电压Vth。第四时间t4和第五时间t5之间的第二区间P2可以被称为补偿区间。
在第六时间t6，第二栅极信号GR[N]可以被转换为截止电压电平。紧接在第六时间t6之后，第一栅极信号GW[N]可以被转换为导通电压电平。在这种情况下，如图5C中所示，响应于具有导通电压电平的第一栅极信号GW[N]，第二晶体管T2可以导通，并且数据信号Vdata(或数据电压)可以从数据线DL传输到第一节点N1(或第一晶体管T1的栅电极)。通过电容器Cst的耦接操作，第二节点N2的电压可以具有与数据信号Vdata和阈值电压Vth之间的电压差Vdata-Vth对应的电压电平。
在第七时间t7或者紧接在第七时间t7之前，第一栅极信号GW[N]可以被转换为截止电压电平。换言之，第六时间t6和第七时间t7之间的第三区间P3(或者其中第一栅极信号GW[N]具有导通电压电平的区间)可以被称为数据写入区间。
接下来，在第八时间t8，第三栅极信号EM[N]可以被转换为导通电压电平。在这种情况下，如图5D中所示，第五晶体管T5可以响应于导通电压电平的第三栅极信号EM[N]而导通。根据通过第五晶体管T5施加到第一晶体管T1的第一电极的第一电源电压VDD，第一晶体管T1的第二电极(例如，第二节点N2)的电压电平可以上升到特定电压电平VEL。此外，第一晶体管T1的栅电极(例如，第一节点N1)的电压电平可以通过电容器Cst上升到特定电压电平VEL和阈值电压Vth的总和VEL+Vth。
随着第一晶体管T1的第二电极(例如，第二节点N2)的电压电平上升，发光元件LD的阳极电极与阴极电极之间的电压差可以增大，并且发光元件LD可以发光。换言之，像素PX可以进入发光区间并且可以发光，直到第三栅极信号EM[N]例如在第四区间P4中被转换为导通电压电平为止。
可以通过第一晶体管T1和第五晶体管T5在第一电源线PL1与第二电源线PL2之间创建电流路径。根据流过第一晶体管T1的电流，第一晶体管T1的第二电极(例如，第二节点N2)的电位可以上升到特定电压电平VEL。第一晶体管T1的栅电极的电位也可以通过电容器Cst提高。
如参照图4至图5D所描述的，像素PX可以在第二区间P2中补偿第一晶体管T1的阈值电压Vth，并且可以在不同于第二区间P2(或者独立于第二区间P2)的第三区间P3中写入数据信号Vdata。此外，第二区间P2(例如，补偿区间)的大小可以通过改变第二栅极信号GR[N]的脉冲宽度来调整。因此，像素PX可以具有更充足的补偿时间。
图6是示出了根据本发明构思的示例性实施例的在图2的像素中测量的信号的波形图。
显示装置100可以在正常模式下或者在低功率模式下操作。例如，显示装置100可以在正常模式下以基准频率(例如，60Hz)被驱动的同时在一秒钟内显示多帧图像(例如，60帧图像)。此外，显示装置100可以在低功率模式下以低频率(例如，1Hz)被驱动的同时在一秒钟内显示几帧图像(例如，一帧图像)。图6示出了当在低功率模式下驱动显示装置100时在一秒钟内在像素中测量的信号。
在图6中，示出了在图2的第一扫描线GL1中测量的第一栅极信号GW[N]、在发光控制线EL中测量的第三栅极信号EM[N]以及在第一晶体管T1(或发光元件LD)中流动的电流Id。
参照图6，第一帧区间FRAME1中的第一栅极信号GW[N]和第三栅极信号EM[N]可以分别基本上等于参照图4描述的第一栅极信号GW[N]和第三栅极信号EM[N]。因此，本文中将不再重复地进行重复描述。
根据第三栅极信号EM[N]，在第八时间t8与第九时间t9之间的第四区间P4期间，将与数据信号(例如，响应于第一栅极信号GW[N]先前供应的数据信号)对应的电流Id供应到发光元件LD。发光元件LD可以以与电流Id对应的亮度发光。
换言之，在第一帧区间FRAME1中，像素PX可以从外部装置(例如，参照图1描述的数据驱动器130)接收数据信号，并且可以在第四区间P4中以与数据信号对应的亮度发光。
在第九时间t9，像素PX的操作可以基本上等于在第一时间t1的像素PX的操作。
在第九时间t9，第三栅极信号EM[N]可以被转换为截止电压电平。在第十时间t10，第三栅极信号EM[N]可以被转换为导通电压电平。此处，第九时间t9与第十时间t10之间的间隔(或第六区间P6的大小)可以等于第一时间t1与第八时间t8之间的间隔(或第五区间P5的大小)。例如，第十时间t10可以是从第九时间t9开始已流逝了九个水平时间(9H)的时间。因此，在第六区间P6中，像素PX可以响应于截止电压电平的第三栅极信号EM[N]而不发光。
在第六区间P6中，第一栅极信号GW[N]可以保持在截止电压电平，使得可以不将数据信号进一步供应到像素PX。由于将第一栅极信号GW[N]保持在截止电压电平，因此先前时间处的诸如第一栅极信号GW[N]的先前栅极信号(例如，参照图4描述的先前栅极信号GI[N])可以保持在截止电压电平。第二栅极信号GR[N]可以保持在截止电压电平。换言之，第二晶体管T2至第四晶体管T4可以保持截止状态。因此，在第六区间P6中，不执行对于像素PX的初始化操作和补偿操作，并且供应到先前帧区间(例如，第一帧区间FRAME1)的数据信号可以保持在像素PX(或第一晶体管T1的栅电极)中。
如参照图2所描述的，第一晶体管T1可以包括氧化物半导体，并且氧化物半导体的迟滞(或迟滞特性)可以比多晶硅半导体的迟滞小得多(例如，约1/100)。因此，可以使数据信号保持得更恒定。
在第十时间t10，根据导通电压电平的第三栅极信号EM[N]，可以将与数据信号对应的电流Id供应到发光元件LD。发光元件LD可以以与电流Id对应的亮度发光。
在第二帧区间FRAME2的结束时间(或第三帧区间FRAME3的开始时间)，第三栅极信号EM[N]可以被截止。因此，在第二帧区间FRAME2的第四区间P4中，像素PX可以以与数据信号对应的亮度发光。换言之，在第二帧区间FRAME2内的当像素PX发光时的时段可以基本上等于在第一帧区间FRAME1内的当像素PX发光时的时段。
为了参考，在第二帧区间FRAME2中，当第三栅极信号EM[N]具有与第一帧区间FRAME1中的波形相同的波形时，像素PX还可以在与第一帧区间FRAME1的第二区间P2对应的时间内发光(参见图4)。换言之，在第二帧区间FRAME2内的当像素PX发光时的时段可以比在第一帧区间FRAME1内的当像素PX发光时的时段长，并且第二帧区间FRAME2中的亮度可以比第一帧区间FRAME1中的亮度高，这会被用户视为闪烁。
因此，在第二帧区间FRAME2中，第三栅极信号EM[N]可以具有与第一帧区间FRAME1的波形不同的波形，使得在第二帧区间FRAME2内的当像素PX发光时的时段可以等于在第一帧区间FRAME1内的当像素PX发光时的时段。换言之，与第一帧区间FRAME1相比，第五晶体管T5在第二帧区间FRAME2中被截止更长的时段。
图7A至图7C是示出了根据本发明构思的示例性实施例的在图1的显示装置中包括的像素的电路图。图7A至图7C中所示的像素PX可以包括一个背栅晶体管或者三个或更多个背栅晶体管。
参照图2和图7A，除了第二晶体管T2之外，图7A的像素PX可以基本上等于图2的像素PX。因此，本文中将不再重复地进行重复描述。
第二晶体管T2可以包括耦接到数据线DL的第一电极、耦接到第一节点N1的第二电极以及耦接到第一扫描线GL1的栅电极。换言之，第二晶体管T2可以不被实现为背栅晶体管，而是可以被实现为单栅(single-gate)晶体管。
参照图2和图7B，除了第三晶体管T3之外，图7B的像素PX可以基本上等于图2的像素PX。因此，本文中将不再重复地进行重复描述。
第三晶体管T3可以包括耦接到第三电源线PL3的第一电极、耦接到第一节点N1的第二电极、耦接到基准扫描线GRL的栅电极以及耦接到基准扫描线GRL(或栅电极)的背栅电极。换言之，第三晶体管T3可以被实现为背栅晶体管。
参照图7B和图7C，除了第四晶体管T4之外，图7C的像素PX可以基本上等于图7B的像素PX。因此，本文中将不再重复地进行重复描述。
第四晶体管T4(或初始化晶体管)可以包括耦接到第二节点N2的第一电极、耦接到第四电源线PL4的第二电极、耦接到第二扫描线GL2的栅电极以及耦接到第二扫描线GL2(或栅电极)的背栅电极。换言之，第四晶体管T4可以被实现为背栅晶体管。
根据本发明构思的示例性实施例的像素电路和显示装置基于不同的栅极信号独立地执行数据信号的写入和阈值电压的补偿。因此，无论显示装置的分辨率或高频驱动如何，均可以自由地调整阈值电压的补偿时间，并且可以更充分地确保阈值电压的补偿时间。
尽管已经参照本发明构思的示例性实施例示出和描述了本发明构思，但是本领域普通技术人员应当理解，在不脱离如由本公开阐述的本发明构思的精神和范围的情况下，可以对其进行形式和细节上的各种改变、替换和修改。

Claims (20)

1.一种像素电路，其中，所述像素电路包括：
第一晶体管，包括第一电极、耦接到第二节点的第二电极、耦接到第一节点的第一栅电极和直接耦接到所述第二节点的第二栅电极；
第二晶体管，包括耦接到数据线的第一电极、耦接到所述第一节点的第二电极和耦接到第一扫描线的第一栅电极；
第三晶体管，包括耦接到第三电源线的第一电极、耦接到所述第一节点的第二电极和耦接到基准扫描线的第一栅电极；
存储电容器，耦接在所述第二节点与所述第一节点之间；以及
发光元件，耦接到所述第二节点。
2.根据权利要求1所述的像素电路，其中，所述第一晶体管的所述第二栅电极设置为与所述第一晶体管的所述第一栅电极重叠，绝缘层介于所述第一晶体管的所述第二栅电极与所述第一晶体管的所述第一栅电极之间。
3.根据权利要求2所述的像素电路，其中，所述第一晶体管至所述第三晶体管中的每一个包括氧化物半导体。
4.根据权利要求1所述的像素电路，其中，所述第一晶体管至所述第三晶体管中的每一个的所述第一栅电极设置在其半导体上。
5.根据权利要求1所述的像素电路，其中，所述像素电路还包括：
第四晶体管，包括耦接到所述发光元件的一个电极的第一电极、耦接到第四电源线的第二电极和耦接到第二扫描线的栅电极。
6.根据权利要求1所述的像素电路，其中，所述像素电路还包括：
第五晶体管，包括耦接到第一电源线的第一电极、耦接到所述第一晶体管的所述第一电极的第二电极和耦接到发光控制线的栅电极。
7.根据权利要求1所述的像素电路，其中，所述第一晶体管的所述第二栅电极通过电容器耦接到第二电源线。
8.根据权利要求1所述的像素电路，其中，所述第二晶体管还包括耦接到所述第二晶体管的所述第一栅电极的第二栅电极。
9.根据权利要求8所述的像素电路，其中，所述第三晶体管还包括耦接到所述第三晶体管的所述第一栅电极的第二栅电极。
10.一种显示装置，其中，所述显示装置包括：
显示器，包括数据线、第一扫描线、基准扫描线和像素；
数据驱动器，配置为将数据信号供应到所述数据线；以及
栅极驱动器，配置为将第一栅极信号供应到所述第一扫描线，并且将第二栅极信号供应到所述基准扫描线，
其中，所述像素包括：
第一晶体管，包括第一电极、耦接到第二节点的第二电极、耦接到第一节点的第一栅电极和直接耦接到所述第二节点的第二栅电极；
第二晶体管，包括耦接到所述数据线的第一电极、耦接到所述第一节点的第二电极和耦接到所述第一扫描线的第一栅电极；
第三晶体管，包括耦接到第三电源线的第一电极、耦接到所述第一节点的第二电极和耦接到所述基准扫描线的第一栅电极；
存储电容器，耦接在所述第二节点与所述第一节点之间；以及
发光元件，耦接到所述第二节点。
11.根据权利要求10所述的显示装置，其中，所述第二晶体管还包括耦接到所述第二晶体管的所述第一栅电极的第二栅电极。
12.根据权利要求11所述的显示装置，其中，所述第三晶体管还包括耦接到所述第三晶体管的所述第一栅电极的第二栅电极。
13.根据权利要求10所述的显示装置，其中，所述第一晶体管的所述第二栅电极通过电容器耦接到第二电源线。
14.根据权利要求10所述的显示装置，其中，所述显示装置还包括：
第四晶体管，包括耦接到所述发光元件的一个电极的第一电极、耦接到第四电源线的第二电极和耦接到第二扫描线的栅电极；以及
第五晶体管，包括耦接到第一电源线的第一电极、耦接到所述第一晶体管的所述第一电极的第二电极和耦接到发光控制线的栅电极。
15.根据权利要求14所述的显示装置，其中，在第一区间中，所述栅极驱动器将具有导通电压电平的所述第二栅极信号供应到所述基准扫描线，并且将具有导通电压电平的所述第一栅极信号供应到所述第二扫描线。
16.根据权利要求15所述的显示装置，其中，在第二区间中，所述栅极驱动器将具有导通电压电平的第三栅极信号供应到所述发光控制线，并且将具有截止电压电平的所述第一栅极信号供应到所述第二扫描线，并且
其中，所述第二区间与所述第一区间不同，并且所述第二区间比所述第一区间长。
17.根据权利要求16所述的显示装置，其中，在第三区间中，所述栅极驱动器将具有所述导通电压电平的所述第一栅极信号供应到所述第一扫描线，并且
其中，所述第三区间与所述第一区间和所述第二区间不同，并且所述第三区间具有与所述第一区间的宽度相同的宽度。
18.根据权利要求17所述的显示装置，其中，在第四区间中，所述栅极驱动器将具有所述导通电压电平的所述第三栅极信号供应到所述发光控制线，并且所述发光元件以与所述数据信号对应的亮度发光。
19.根据权利要求18所述的显示装置，其中，所述第一区间至所述第四区间被包括在第一帧中，
其中，所述第二晶体管和所述第三晶体管在继所述第一帧之后的第二帧中保持截止状态，并且
其中，所述第二帧中的当所述第五晶体管截止时的第一时段比所述第一帧中的当所述第五晶体管截止时的第二时段长。
20.根据权利要求19所述的显示装置，其中，所述第二帧中的当所述发光元件发光时的时段与所述第一帧中的当所述发光元件发光时的时段相同。
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