CN118053828A - 电子装置 - Google Patents
电子装置 Download PDFInfo
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- CN118053828A CN118053828A CN202211434036.1A CN202211434036A CN118053828A CN 118053828 A CN118053828 A CN 118053828A CN 202211434036 A CN202211434036 A CN 202211434036A CN 118053828 A CN118053828 A CN 118053828A
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- conductive pad
- electronic device
- conductive
- bonding
- bonding element
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- 229910000679 solder Inorganic materials 0.000 claims description 9
- 230000007423 decrease Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 71
- 239000000463 material Substances 0.000 description 21
- 238000000034 method Methods 0.000 description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000010408 film Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 229910052718 tin Inorganic materials 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000011135 tin Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000011133 lead Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- -1 PSPI) Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 210000001503 joint Anatomy 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract
本发明公开了一种电子装置,电子装置包括电路结构、接合元件以及电子单元。电路结构包括导电垫,其中导电垫具有容置槽。至少部分的接合元件设置在容置槽中。电子单元通过接合元件电性连接导电垫。其中,容置槽具有底面以及与底面相对的开口,且底面的宽度大于开口的宽度。
Description
技术领域
本发明涉及一种电子装置,特别是涉及一种包括具有容置槽的导电垫的电子装置。
背景技术
近年来,电子装置中的电子元件逐渐趋向小型化与高密集化,为此发展出多样化的电子元件封装技术。然而,在现有技术中,电子装置中的元件彼此对位相接时,可能会造成位移或公差,而使得接合后装置的电性与可靠度表现不佳。
发明内容
本发明的目的之一在于提供一种电子装置,以解决现有电子装置所遭遇的问题,通过导电垫的结构设计,可提升元件之间的对位精准度,进而提升电子装置的可靠度。
本发明的一实施例提供一种电子装置,电子装置包括电路结构、接合元件以及电子单元。电路结构包括导电垫,其中导电垫具有容置槽。至少部分的接合元件设置在容置槽中。电子单元通过接合元件电性连接导电垫。其中,容置槽具有底面以及与底面相对的开口,且底面的宽度大于开口的宽度。
附图说明
图1为本发明一实施例的电子装置的剖面示意图。
图2为图1所示导电垫与接合元件的局部放大示意图。
图3为本发明另一实施例的电子装置的剖面示意图。
图4为本发明导电垫与接合元件的变化实施例的局部剖面示意图。
图5为本发明又一实施例的电子装置的剖面示意图。
图6至图8为本发明电子装置的另一实施例的导电垫的部分制程示意图。
图9为图8所示导电垫与接合元件相接的局部剖面示意图。
附图标记说明:100-电路结构;110、140-导电垫;110a、146a、148a-上表面;110b-下表面;110e-边缘;112、112a、112b-导电层;114、114a、114b-绝缘层;114G-凹槽;120、141-容置槽;122、142-底面;124、144-开口;126-侧壁;130-中介层;140M1、140M2-金属层;140S-种子层;146-突起部;146S-弧形表面;148-延伸部;200、200’、500-接合元件;210-接合部;220-导电柱;300、600-电子单元;400、410-保护层;610-接合垫;ED-电子装置;H1-第一距离;H2-第二距离;I、I1-界面;P-端部;PR-光阻;S-段差;T1-深度;T2、T3-厚度;W1、W2、W3、W4、W5-宽度;X、Y-方向;θ-夹角。
具体实施方式
下文结合具体实施例和附图对本发明的内容进行详细描述,须注意的是,为了使读者能容易了解及图式的简洁,本发明中的多张图式只绘出装置的一部分,且图式中的特定元件并非依照实际比例绘图。此外,图中各元件的数量及尺寸仅作为示意,并非用来限制本发明的范围。
本发明通篇说明书与权利要求中会使用某些词汇来指称特定元件。本领域技术人员应理解,电子设备制造商可能会以不同的名称来指称相同的元件。本文并不意在区分那些功能相同但名称不同的元件。在下文说明书与权利要求书中,“含有”与“包括”等词为开放式词语,因此其应被解释为“含有但不限定为…”之意。当在本说明书中使用术语“包含”、“包括”和/或“具有”时,其指定了所述特征、区域、步骤、操作和/或元件的存在,但并不排除一个或多个其他特征、区域、步骤、操作、元件和/或其组合的存在或增加。
当元件或膜层被称为在另一个元件或膜层“上”或“连接到”另一个元件或膜层时,它可以直接在此另一元件或膜层上或直接连接到此另一元件或膜层,或者两者之间存在有插入的元件或膜层。相反地,当元件被称为“直接”在另一个元件或膜层“上”或“直接连接到”另一个元件或膜层时,两者之间不存在有插入的元件或膜层。
本文中所提到的方向用语,例如:“上”、“下”、“前”、“后”、“左”、“右”等,仅是参考附图的方向。因此,使用的方向用语是用来说明,而并非用来限制本发明。
术语“大约”、“等于”、“相等”或“相同”、“实质上”或“大致上”一般解释为在所给定的值或范围的20%以内,或解释为在所给定的值或范围的10%、5%、3%、2%、1%或0.5%以内。
说明书与权利要求书中所使用的序数例如“第一”、“第二”等的用词用以修饰元件,其本身并不意含及代表该(或该些)元件有任何之前的序数,也不代表某一元件与另一元件的顺序、或是制造方法上的顺序,该些序数的使用仅用来使具有某命名的元件得以和另一具有相同命名的元件能作出清楚区分。权利要求书与说明书中可不使用相同用词,据此,说明书中的第一构件在权利要求中可能为第二构件。
本发明所述的电子装置可包括半导体装置、封装装置、显示装置、发光装置、背光装置、太阳能电池(solar cell)、感测装置、天线装置、车用装置或高频装置,但不以此为限。电子装置可为可弯折或可挠式电子装置。显示装置可为非自发光型显示装置或自发光型显示装置。天线装置可为液晶型态的天线装置或非液晶型态的天线装置,感测装置可为感测电容、光线、热能或超声波的感测装置,但不以此为限。电子装置可例如包括被动元件与主动元件等电子元件,例如电容、电阻、电感、二极管、晶体管等。需注意的是,电子装置可为前述的任意排列组合,但不以此为限。
须知悉的是,在不脱离本发明的精神下,可将数个不同实施例中的特征进行替换、重组、混合以完成其他实施例。
请参考图1与图2。图1为本发明一实施例的电子装置的剖面示意图。图2为图1所示导电垫与接合元件的局部放大示意图。如图1与图2所示,本发明一实施例的电子装置ED可包括电路结构100、接合元件200以及电子单元300。电路结构100包括导电垫110,其中导电垫110具有容置槽120。具体而言,电路结构100可包括在方向Y上堆叠的至少一层导电层112(例如导电层112a与导电层112b)、至少一层绝缘层114(例如绝缘层114a与绝缘层114b)以及一个或多个导电垫110。导电垫110可设置在最上层的绝缘层114上并电性连接电路结构100中最上层的导电层112,例如设置在绝缘层114b上并电性连接导电层112b,但不以此为限。电路结构100可为重布线层(redistribution layer,RDL),以使线路重布,例如可通过金属布线制程改变线路接点位置或提升线路扇出(fan out)面积,但不以此为限。在本发明中,方向Y可为电子装置ED的法线方向,亦即相反于电子装置ED的俯视方向,而方向X可平行于水平方向,亦即平行于电子单元300的一表面(例如上表面或下表面),而方向Y垂直于方向X,但不以此为限。
在一些实施例中,可在方向Y上依序交替形成图案化的导电层112a、绝缘层114a、导电层112b及绝缘层114b,再将导电垫110形成在绝缘层114b上或是绝缘层114b的凹槽114G中,以构成电路结构100。绝缘层114中可包括一个或多个连接孔,导电层112a、导电层112b及导电垫110可通过连接孔而电连接,但不以此为限。导电垫110可例如但不限于为凸块底层金属(under-bump metallization,UBM)。导电垫110可包括铜、镍、金、银、钛、其他合适的导电材料或上述材料的组合,例如为在导电垫110进行对接时的温度与压力(例如200-400℃与1-100MPa)下可产生机械形变的材料,但不以此为限。导电垫110与导电层112可分别为单层结构或多层堆叠结构。导电垫110的材料可相同或不同于导电层112的材料。导电层112可包括钛、铜、铝、锡、镍、金或银等金属材料或其他合适的导电材料。绝缘层114可包括有机材料或无机材料。有机材料例如包括聚酰亚胺(polyimide,PI)、感光型聚酰亚胺(photosensitive polyimide,PSPI)、环氧树脂(epoxy)、Ajinomoto增层膜(Ajinomotobuild-up film,ABF)材料或其他合适的材料,无机材料例如包括氧化硅(silicon oxide,SiOx)、氮化硅(silicon nitride,SiNx)或其他合适的材料,但不以此为限。电路结构100还可包括主动元件及/或被动元件,例如二极管、晶体管、电容、电阻、电感、天线单元,并可电性连接于导电层112形成的导线等。晶体管例如包括薄膜晶体管(thin film transistor,TFT),薄膜晶体管可包括闸极、源极、汲极及半导体层,但不以此为限。
至少部分的接合元件200设置在导电垫110的容置槽120中,且电子单元300通过接合元件200电性连接导电垫110,从而使电子单元300与电路结构100电性连接。具体而言,电子装置ED可包括一个或多个接合元件200,接合元件200的其中一个的至少一部分可对应设置在导电垫110的容置槽120中并与导电垫110相接,使得电子单元300可通过接合元件200电性连接导电垫110。接合元件200可例如为柱体(pillar)、凸块(bump)、焊球(solderball)或接垫(pad),接合元件200可包括铜、锡、镍、金、铅、铝、其他合适的导电材料或上述材料的组合,但不以此为限。电子单元300可例如为印刷电路板(printed circuit board,PCB)、晶粒(die)、芯片(chip)、集成电路(IC)、二极管、电容、电阻或其他合适的主动元件或被动元件,但不以此为限。
根据本发明实施例,导电垫110的容置槽120具有底面122以及与底面122相对的开口124,且底面122的宽度W1大于开口124的宽度W2。本发明中所指“容置槽的底面的宽度”可表示在方向X上由容置槽的底面的一端测量到另一端所得到的宽度,而所指“容置槽的开口的宽度”可表示在方向X上由容置槽的开口的一端测量到另一端所得到的最小宽度。举例而言,如图2所示,容置槽120是形成在导电垫110的上表面110a的凹槽,容置槽120可具有底面122、开口124及侧壁126,开口124与底面122相对,且侧壁126与底面122相接。其中,可在方向X上由容置槽120的底面122一端测量到另一端以得到宽度W1,且可在方向X上由容置槽120的开口124的一端测量到另一端以得到最小宽度W2。并且,底面122的宽度W1大于开口124的宽度W2(即W1>W2)。通过使接合元件200的至少一部分设置在具有下部宽度W1大于上部宽度W2的容置槽120中,可提升接合元件200与导电垫110之间的对位精准度,减少接合元件200位移,进而提升电子装置ED的可靠度。
在如图2所示的实施例中,容置槽120的深度T1可小于导电垫110的厚度T2(即T1<T2),在一些实施例中,容置槽120的深度T1可小于或等于导电垫110的厚度T2的三分之二,以使容置槽120可容置至少部分的接合元件200,进而提升对位精准度,但不以此为限。其中,可例如在方向Y上由开口124测量到底面122以得到容置槽120的深度T1,且可在方向Y上由导电垫110的上表面110a测量到与上表面相对的下表面110b以得到导电垫110的厚度T2,但不以此为限。
在一些实施例中,在如图2所示的剖视图中,导电垫110的边缘110e与容置槽120的底面122之间的最短距离为第一距离H1,导电垫100的边缘110e与容置槽120的开口124之间的最短距离为第二距离H2,且第一距离H1小于第二距离H2(即H1<H2)。也就是说,在方向X上,导电垫110的边缘110e与底面122邻近边缘110e的一端之间具有第一距离H1,且导电垫110的边缘110e与开口124邻近边缘110e的一端之间具有第二距离H2,其中第一距离H1小于第二距离H2。
在一些实施例中,如图2所示,容置槽120的侧壁126与底面122之间具有夹角θ,且夹角θ可小于90度。根据一些实施例,夹角θ为容置槽120的侧壁126延伸线与底面122延伸线所定义。在一些实施例中,容置槽120的宽度可由底面122往开口124渐减,即侧壁126可为斜壁,而底面122的宽度W1为容置槽120的最大宽度,开口124的宽度W2为容置槽120的最小宽度,使得容置槽120可例如具有梯形的剖视形状,亦即容置槽120的底面122面积大于开口124的面积,但不以此为限。
根据如图2所示导电垫110的结构设计,导电垫110可接触接合元件200,使得接合元件200可嵌入导电垫110的容置槽120中,即导电垫110的容置槽120的上部(例如开口124处边缘)可与接合元件200相接触,以固定接合元件200,从而可提升接合元件200与导电垫110之间的对位精准度。此外,由于导电垫110可接触接合元件200,使得导电垫110整体的尺寸不需要太大就足以与接合元件200相接,亦即可使导电垫110整体的尺寸减少,例如导电垫110整体的宽度W3可较小,从而可减少导电垫110在结构中所占空间,以使扇出线路的设计可具有更多弹性。另一方面,由于导电垫110的尺寸减少,能够节省其材料成本。
在一些实施例中,如图1与图2所示,接合元件200可包括接合部210及导电柱220,导电柱220位于电子单元300与接合部210之间,且容置槽120的深度T1可大于或等于接合部210的厚度T3。其中,可例如在方向Y上由接合部210的上表面(例如接合部210与导电柱220之间的界面I)测量到接合部210最靠近容置槽120的底面122的一端以得到接合部210的厚度T3。接合部210可包括焊料(solder),例如但不限于锡、镓、镍、金、铜、铝、银、在接合元件200进行对接时的温度(例如200-400℃)下可熔化的其他材料或上述材料的组合,使得接合部210可填充容置槽120的至少一部分,即一部分的容置槽120可被接合部210所填充(如图1所示),或者整个容置槽120可被接合部210所填充(如图3所示)。由于接合部210设置在容置槽120中,使得接合部210的尺寸不需要太大就足以使接合元件200与导电垫110充分相接,亦即可使接合部210的尺寸减少,能够节省其材料成本。
导电柱220可包括铜、镍、金、银、其他合适的导电材料或上述材料的组合,例如为在接合元件200进行对接时的温度下不会熔化的材料,但不以此为限。当容置槽120的深度T1大于接合部210的厚度T3时,接合部210与导电柱220之间的界面I可低于容置槽120的上表面110a,使得接合部210设置在容置槽120中,且导电垫110可接触部分的导电柱220,即容置槽120的上部(例如开口124处边缘)与导电柱220相接触,以固定接合元件200。
请参考图3,其为本发明另一实施例的电子装置的剖面示意图。如图3所示,在一些实施例中,接合元件200的接合部210可填充容置槽120至少90%以上的空间。举例而言,在经过制程(例如但不限于润湿制程(wetting process))的反应之后,接合元件200的接合部210可完全填满容置槽120,而使得接合元件200与容置槽120之间不具有空隙,但不以此为限。在如图3所示的剖面图中,导电垫110的容置槽120与接合元件200的接合部210的交界处(例如容置槽120与接合部210之间的界面I1)可例如呈弧形,但不以此为限。在一些实施例中,接合元件200的接合部210与导电垫110还可例如但不限于形成金属间化合物(intermetallic compound,IMC)结构。根据图3所示实施例,通过部分的接合元件200(例如接合部210)设置在容置槽120中,可增加接合元件200与导电垫110之间的接触面积,以减少反应后因两者接触面积不足而造成接触不良等风险,或者能够节省其材料成本,但不以此为限。
根据上述导电垫110的结构与接合元件200包括接合部210及导电柱220的结构,在一些实施例的电子装置ED的制程中,在将电子单元300通过接合元件200电性连接导电垫110时,即在接合元件200与导电垫110进行对接时,可同时对结构进行加热与施加压力,使得接合部210的焊料在制程温度(例如200-400℃)下由固态熔化为液态,且导电垫110在制程压力(例如1-100MPa)下产生形变而接触或箝制住导电柱220。由于在施压时接合部210呈液态,可提供缓冲的功能以减轻应力。在另一些实施例的电子装置ED的制程中,在接合元件200与导电垫110进行对接时,可先只对结构施加压力而不加热,由于此时接合元件200整体为固态,可对导电垫110施予更大的压力而使导电垫110产生更大的形变量,在制程管控不伤害结构的情况下,导电垫110可提供更大的箝制力以接触或箝制住导电柱220。接着,再对结构加热,使得接合部210的焊料在制程温度下熔化以填充容置槽120。然而,本发明实施例的电子装置ED的制程并不以上述为限。
请参考图4。图4为本发明导电垫与接合元件的变化实施例的局部剖面示意图。如图4所示,在一些实施例中,电子装置ED还可包括中介层130,其中至少部分的中介层130设置在导电垫110的容置槽120中且与接合元件200相接,例如中介层130可覆盖容置槽120的底面122及/或侧壁126,或者中介层130还可覆盖导电垫110的部分上表面110a。中介层130可例如为焊料或导电胶,焊料例如包括锡、镓、银、在接合元件200进行对接时的温度下可熔化的其他材料或上述材料的组合,导电胶例如包括异方性导电膜(anisotropicconductive film,ACF),但不以此为限。因此,导电垫110可通过中介层130与接合元件200相接,以进一步提升导电垫110与接合元件200之间的接合强度。
本发明中电子装置ED的制程可例如为面板级封装(panel-level package,FOPLP)制程,且可为先重布线层(RDL-first)或先芯片(chip-first)的制程,但不以此为限。请再参考图1,图1所示的电子装置ED可例如通过先重布线层的制程所制造,先形成包括重布线层的电路结构100,接着可例如通过覆晶接合(flip-chip bonding)将电子单元300设置在电路结构100上,但不以此为限。根据图1所示的实施例,电子装置ED还可包括保护层400,其中保护层400可围绕电子单元300及接合元件200,以隔绝水气、空气及/或减少电子单元300及接合元件200损伤。本发明中所指“围绕”可表示在电子装置ED的剖视图中,元件或膜层至少接触对应的被围绕元件或膜层的侧表面。举例而言,保护层400可至少接触电子单元300的侧表面及接合元件200的侧表面。如图1所示,保护层400可覆盖电子单元300的侧表面与上表面并覆盖接触一部分的电路结构100表面,但不以此为限。在另一些实施例中,电子单元300的上表面没有被保护层400所覆盖,例如可通过研磨(grinding)制程使保护层400暴露出电子单元300的上表面。保护层400可例如包括环氧树脂、陶瓷、环氧树脂封装材料(epoxy molding compound,EMC)、其他合适的材料或上述材料的组合,但不以此为限。
在一些实施例中,如图1所示,电子装置ED还可包括另一接合元件500,其中接合元件500与接合元件200分别设置在该电路结构100的相对两侧,即接合元件500可设置在电路结构100相对于电子单元300的一侧,且接合元件500电性连接电路结构100。接合元件500可例如为凸块底层金属、凸块、焊球或接垫,接合元件500可包括铜、锡、镍、金、铅、其他适合的导电材料或上述材料的组合,但不以此为限。在一些实施例中,电子装置ED还可包括另一电子单元(图1中未示出),此另一电子单元与电子单元300分别设置在电路结构100的相对两侧,且此另一电子单元可通过接合元件500电性连接电路结构100,但不以此为限。
下文将继续详述本发明电子装置与电子装置的制程的其他实施例,为了简化说明,下文中使用相同标号标注相同元件,以下主要针对不同实施例间的差异详加叙述,且不再赘述相同的特征。本发明的各实施例与实施例可以互相组合与变化。
请参考图5,图5为本发明又一实施例的电子装置的剖面示意图,其中图5所示的电子装置ED可例如通过先芯片的制程所制造,但不以此为限。根据图5所示的实施例,接合元件200’的态样可不同于图1所示实施例的接合元件200的态样,且至少部分的接合元件200’可设置在导电垫110的容置槽120中,而电子单元300可通过接合元件200’电性连接导电垫110,从而使电子单元300与电路结构100电性连接。但在其他实施例中,接合元件200’的态样也可相同于图1所示实施例的接合元件200的态样,并不以此为限。在一些实施例中,如图5所示,电子装置ED还可包括另一电子单元600,电子单元600与电子单元300分别设置在电路结构100的相对两侧,且电子单元600可电性连接电路结构100。电子单元600可例如为印刷电路板、晶粒、芯片、集成电路、二极管、电容、电阻或其他合适的主动元件或被动元件,但不以此为限。电子单元600还可例如包括接合垫610,且电路结构100中的导电层112可电性连接电子单元600的接合垫610,接合垫610可包括铝、铜、锡、镍、金、铅、其他适合的导电材料或上述材料的组合,但不以此为限。此外,如图5所示,电子装置ED还可包括保护层410,保护层410围绕电子单元600,例如保护层410可覆盖接触电子单元600的侧表面与下表面并覆盖接触一部分的电路结构100表面,但不以此为限。在另一些实施例中,电子单元600的下表面没有被保护层410所覆盖,例如可通过研磨制程使保护层410暴露出电子单元600的下表面。保护层410可例如包括环氧树脂、陶瓷、环氧树脂封装材料、其他合适的材料或上述材料的组合,但不以此为限。
请参考图6至图8。图6至图8为本发明电子装置的另一实施例的导电垫的部分制程示意图。为了简化说明,在图6至图8中省略了电路结构100中的导电层,且将电路结构100中的多层绝缘层的整体以绝缘层114表示,电路结构100中的多层绝缘层114与多层导电层112的配置例如可参考图1,但不以图1为限。如图6至图8所示,本发明另一实施例的导电垫140的制程可例如包括以下步骤。首先,如图6所示,可图案化最上层的绝缘层114以形成一个或多个凹槽114G,然后在绝缘层114上形成种子层(seed layer)140S,再在种子层140S上形成金属层140M1。例如但不限于可通过电镀制程形成金属层140M1,其中种子层140S可有助于金属层140M的形成或提升附着力。然后,可在金属层140M1上形成图案化的光阻PR,其中图案化的光阻PR例如形成在不对应凹槽114G所在区域的金属层140M1上,例如凹槽114G可位于相邻的光阻图案之间。
接着,可进行电镀制程以在图6所示的金属层140M1继续生长金属材料,形成如图7所示的金属层140M2。具体而言,可例如通过调控电镀液中的添加剂(additive agent),使添加剂更容易吸附在图6中虚线框所示的端部P且可增加端部P处金属的生长速率,从而形成如图7所示的金属层140M2。然后,如图8所示,可移除光阻PR,即可得到包括一个或多个导电垫140的电路结构100。根据图6至图8所示实施例,种子层140S的材料可例如包括钛、铜、钼、铝、镍、银、锡、其他合适的导电材料或上述材料的组合,但不以此为限。金属层140M1及/或金属层140M2的材料可例如包括铜、镍、金、银、其他合适的导电材料或上述材料的组合,例如为在所形成的导电垫140进行对接时的温度与压力(例如200-400℃与1-100MPa)下可产生机械形变的材料,但不以此为限。
请参考图9,图9为图8所示导电垫与接合元件相接的局部剖面示意图。如图9所示,导电垫140可具有容置槽141,容置槽141具有底面142以及与底面142相对的开口144,且底面142的宽度W4大于开口144的宽度W5(即W4>W5)。其中,可在方向X上由容置槽141的底面142的一端测量到另一端以得到宽度W4,且可在方向X上由容置槽141的开口144的一端测量到另一端以得到最小宽度W5。具体而言,导电垫140可包括突起部146,突起部146环绕开口144,其中突起部146之间的最小距离可为开口144的宽度W5。在一些实施例中,导电垫140的突起部146可接触接合元件200,使得接合元件200可嵌入导电垫140的容置槽141中,即突起部146可与接合元件200相接触,以固定接合元件200。举例而言,接合元件200的接合部210可设置在容置槽141中,且突起部146可接触接合元件200的导电柱220的一部分,但不以此为限,其中接合元件200的接合部210与导电柱220的细部结构及材料可例如参考前述实施例,于此不再赘述。突起部146接触接合元件200的一侧可具有弧形表面146S,其中弧形表面146S是例如通过如图6与图7所示的添加剂吸附在端部P并增加端部P处金属的生长速率所形成,但不以此为限。根据图9所示的实施例,导电垫140还可包括延伸部148,延伸部148由突起部146向相反于开口144的方向延伸,其中延伸部148的上表面148a与突起部146的上表面146a之间可具有段差S。即在方向Y上,延伸部148的上表面148a与突起部146的上表面146a之间的最短距离为段差S,其中延伸部148的上表面148a可大致上平行于方向X,但不以此为限。
综上所述,根据本发明实施例的电子装置,通过设置具有下部宽度大于上部宽度的容置槽的导电垫,并使至少部分的接合元件设置在容置槽中,可提升接合元件与导电垫之间的对位精准度,进而提升电子装置的可靠度。此外,通过导电垫接触接合元件,可使导电垫有效地电连接接合元件,因此相较于现有技术,本发明电子装置中的接合元件与导电垫可以具有较小的尺寸,从而可使扇出线路的设计具有更多弹性及/或能够节省成本。
以上所述仅为本发明的实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种电子装置,其特征在于,包括:
一电路结构,包括一导电垫,其中该导电垫具有一容置槽;
一接合元件,至少部分的该接合元件设置在该容置槽中;以及
一电子单元,该电子单元通过该接合元件电性连接该导电垫;
其中,该容置槽具有一底面以及与该底面相对的一开口,且该底面的宽度大于该开口的宽度。
2.如权利要求1所述的电子装置,其特征在于,该容置槽的深度小于该导电垫的厚度。
3.如权利要求1所述的电子装置,其特征在于,在该电子装置的剖视图中,该导电垫的一边缘与该底面之间的最短距离为一第一距离,该导电垫的该边缘与该开口之间的最短距离为一第二距离,且该第一距离小于该第二距离。
4.如权利要求1所述的电子装置,其特征在于,该容置槽具有一侧壁,该侧壁与该底面相接,其中该侧壁与该底面之间的夹角小于90度。
5.如权利要求1所述的电子装置,其特征在于,该接合元件包括一接合部及一导电柱,该导电柱位于该电子单元与该接合部之间,其中该容置槽的深度大于或等于该接合部的厚度。
6.如权利要求5所述的电子装置,其特征在于,该接合部设置在该容置槽中,且该导电垫接触部分的该导电柱。
7.如权利要求5所述的电子装置,其特征在于,该接合部包括焊料,且该接合部填充该容置槽的至少一部分。
8.如权利要求1所述的电子装置,其特征在于,该导电垫接触该接合元件。
9.如权利要求1所述的电子装置,其特征在于,还包括一中介层,至少部分的该中介层设置在该容置槽中且与该接合元件相连接。
10.如权利要求1所述的电子装置,其特征在于,该容置槽的宽度由该底面往该开口渐减。
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