CN117790461A - 制造电子装置的方法 - Google Patents

制造电子装置的方法 Download PDF

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Publication number
CN117790461A
CN117790461A CN202311731849.1A CN202311731849A CN117790461A CN 117790461 A CN117790461 A CN 117790461A CN 202311731849 A CN202311731849 A CN 202311731849A CN 117790461 A CN117790461 A CN 117790461A
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China
Prior art keywords
pin
redistribution structure
conductive
pins
electronic device
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CN202311731849.1A
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Inventor
巴拉罗门·德发拉郡
李彻特·丹尼尔
翰姆施·瑞格
策恩德·迪安
瑞讷·格兰
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Amkor Technology Inc
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Amkor Technology Inc
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Publication of CN117790461A publication Critical patent/CN117790461A/zh
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Abstract

本申请是申请号为：“201811169135.5”，申请日为：“2018年10月08日”，发明名称为：“制造电子装置的方法”的发明专利的分案申请。本发明提供一种制造电子装置的方法。尤其是关于一种用于制造电子装置的方法，方法包含：取得基板，基板包括多个焊垫；形成多个焊料构件，多个焊料构件中的每一个焊料构件被定位在多个焊垫中的各自的焊垫上；提供接脚模板，接脚模板包含多个孔洞；将接脚模板定位在基板上方，将多个孔洞中的每一个孔洞对准多个焊垫中的各自的焊垫；提供多个接脚，多个接脚中的每一个接脚被定位在多个孔洞中的各自的孔洞中；从接脚移除接脚模板；并且回焊焊料构件。

Description

制造电子装置的方法
本申请是申请号为：201811169135.5，申请日为：2018年10月08日，发明名称为：制造电子装置的方法的发明专利的分案申请。
技术领域
本发明关于一种制造电子装置的方法。
背景技术
目前的半导体封装和用于形成半导体封装的方法是不足的，例如导致成本过高、可靠性低或封装尺寸太大。透过将习知和传统的方法与本申请的其余部分中参考附图所阐述的本发明进行比较，习知和传统的方法的进一步限制和缺点对于本领域技术人员将变得显而易见。
发明内容
本发明的各种态样提供一种电子装置以及一种制造电子装置的方法。作为非限制性的范例，本发明的各种态样提供一种电子装置，该电子装置具有顶侧接脚阵列，例如其可被用于三维堆栈；以及一种用于制造此种电子装置的方法。
根据本发明的一态样，一种用于制造电子装置的方法，所述方法包含：取得基板，所述基板包括多个焊垫；形成多个焊料构件，所述多个焊料构件中的每一个焊料构件被定位在所述多个焊垫中的各自的焊垫上；提供接脚模板，所述接脚模板包含多个孔洞；将所述接脚模板定位在所述基板上方，将所述多个孔洞中的每一个孔洞对准所述多个焊垫中的各自的焊垫；提供多个接脚，所述多个接脚中的每一个接脚被定位在所述多个孔洞中的各自的孔洞中；从所述接脚移除所述接脚模板；并且回焊所述焊料构件。进一步而言，所述基板包含于暂时载体上的讯号分布结构；所述讯号分布结构没有包含主动半导体电路；并且所述方法包含移除所述暂时载体。进一步而言，所述基板包含半导体晶粒，所述半导体晶粒包含主动电路。进一步而言，所述提供所述多个接脚包含至少将所述多个接脚定位在所述接脚模板的顶侧上并且移动所述多个接脚中的每一个接脚进入所述多个孔洞中的各自的孔洞之中。进一步而言，所述移动所述多个接脚中的每一个接脚包含振动所述接脚模板。进一步而言，所述将所述接脚模板定位在所述基板上方是在所述提供所述多个接脚之前被执行。进一步而言，所述多个接脚中的每一个接脚是圆柱形状。进一步而言，所述多个接脚中的每一个接脚包含在末端表面和侧表面之间的曲线转变。进一步而言，所述多个孔洞中的每一个孔洞具有孔洞直径；并且所述多个接脚中的每一个接脚包含圆柱形状的主要本体以及头部，所述主要本体具有本体直径，所述本体直径小于所述孔洞直径，而所述头部具有头部直径，所述头部直径大于所述孔洞直径。进一步而言，所述提供多个接脚包含藉由黏着胶带将所述多个接脚中的每一个接脚保持在所述多个孔洞中的各自的孔洞之中；并且所述从所述接脚移除所述接脚模板包含移除所述黏着胶带。进一步而言，在所述回焊所述焊料构件之后，每个经回焊过的焊料构件将其各自的焊垫与其各自的接脚分隔开。进一步而言，所述方法进一步包含：将半导体晶粒耦合到所述基板并且所述半导体晶粒被直接侧向地定位在所述多个接脚中的至少两个接脚之间；以及将所述半导体晶粒和所述多个接脚囊封于囊封材料之中。
根据本发明的另一态样，一种制造电子装置的方法，所述方法包含：取得基板，所述基板包含多个焊垫；提供接脚模板和相邻于所述基板的所述焊垫的多个接脚，其中：所述接脚模板包含多个孔洞；以及所述多个接脚中的每一个接脚被定位在所述多个孔洞中的各自的孔洞之中并且与所述多个焊垫中的各自的焊垫对准；以及将所述多个接脚中的每一个接脚附接至所述每一个接脚的各自的焊垫。进一步而言，所述方法进一步包含在所述提供所述接脚模板和相邻于所述基板的所述焊垫的多个接脚之前形成各自的焊料构件于所述多个焊垫中的每个焊垫上。进一步而言，在提供所述接脚模板和将所述多个接脚定位于所述接脚模板的所述多个孔洞中之前将所述接脚模板定位在所述基板上方。进一步而言，在将所述接脚模板定位于所述基板上方之前，所述多个接脚中的每一个接脚被保持在每一个接脚的各自的孔洞中。进一步而言，在附接之后，所述多个接脚中的每一个接脚是藉由焊料层与每一个接脚的各自的焊垫分隔开。
根据本发明的又另一态样，一种制造电子装置的方法，所述方法包含：提供接脚模板，所述接脚模板包含多个孔洞；定位所述接脚模板于基板上方，其中所述基板包含多个焊垫；提供多个接脚，所述多个接脚中的每一个接脚被定位在所述多个孔洞中的各自的孔洞之中并且与所述多个焊垫的各自的焊垫对准；以及将所述多个接脚中的每一个接脚焊接到所述基板的各自的焊垫。进一步而言，所述基板包含在暂时载体上的讯号分布结构；以及所述方法进一步包含在焊接之后移除所述暂时载体。进一步而言，所述基板包含半导体晶粒，所述半导体晶粒包含主动半导体电路。
附图说明
图1显示根据本发明的各种态样的一种制造电子装置的范例性方法的流程图。
图2A到图2I-2显示根据本发明的各种态样的横截面图，其图标一种范例电子装置以及制造范例性电子装置的范例性方法。
图3显示根据本发明的各种态样的一种制造电子装置的范例性方法的流程图。
图4A到图4F-3显示根据本发明的各种态样的横截面图，其图标一种范例电子装置以及制造范例性电子装置的范例性方法。
图5A到图5C显示根据本发明的各种态样的横截面图，其图标一种范例电子装置以及制造范例性电子装置的范例性方法。
具体实施方式
以下的讨论是藉由提供本揭露内容的各种态样的范例来呈现该些特点。此种范例并非限制性的，并且因此本揭露内容的各种态样的范畴不应该是受限于所提供的例子的任何特定的特征。在以下的讨论中，该措辞“例如”、“譬如”以及“范例的”并非限制性的，并且大致与“举例且非限制性的”、“例如且非限制性的”及类似的为同义的。
如同在本文中所利用的，“及/或”是表示在表列中藉由“及/或”所加入的项目中的任一个或多个。举例而言，“x及/或y”是表示该三个元素的集合{(x)、(y)、(x,y)}中的任一元素。换言之，“x及/或y”是表示“x及y中的一或两个”。作为另一例子的是，“x、y及/或z”是表示该七个元素的集合{(x)、(y)、(z)、(x,y)、(x,z)、(y,z)、(x,y,z)}中的任一元素。换句话说，“x、y及/或z”是表示“x、y及z中的一或多个”。
在本文中所用的术语只是为了描述特定范例的目的而已，因而并不欲限制本揭露内容。如同在此所用的，单数形式欲亦包含复数形式，除非上下文另有清楚相反的指出。进一步将会理解到的是，当该些术语“包括”、“包含”、“具有”与类似的用在此说明书时，其是指明所述特点、整数、步骤、操作、组件及/或组件的存在，但是并不排除一或多个其它特点、整数、步骤、操作、组件、组件及/或其群组的存在或是添加。
将会了解到的是，尽管该些术语第一、第二等等可被使用在此以描述各种组件，但是这些组件不应该受限于这些术语。这些术语只是被用来区别一组件与另一组件而已。因此，例如在以下论述的一第一组件、一第一组件或是一第一区段可被称为一第二组件、一第二组件或是一第二区段，而不脱离本揭露内容的教示。类似地，各种例如是“上方”、“下方”、“侧边”与类似的空间的术语可以用一种相对的方式而被用在区别一组件与另一组件。然而，应该了解的是组件可以用不同的方式加以定向，例如一半导体装置或封装可被转向侧边，因而其“顶”表面是水平朝向的，并且其“侧”表面是垂直朝向的，而不脱离本揭露内容的教示。
本发明的各种态样提供一种电子装置(例如半导体装置等等)以及制造(或制作)半导体装置的方法，其可以减少成本、增加可靠性及/或增加所述电子装置的生产能力。
本发明的各种态样也提供一种制造电子装置的方法(以及以此方法制成的电子装置)，其包含取得基板，所述基板包括多个焊垫。多个焊料构件被形成，其中所述多个焊料构件中的每个焊料构件被定位在所述多个焊垫中的各自的焊垫上。包含多个孔洞的接脚模板被提供并且被定位在所述基板上方，其中所述多个孔洞中的每一个孔洞对准所述多个焊垫中的各自的焊垫。多个接脚被提供，其中所述多个接脚中的每一个接脚被定位在所述多个孔洞中的各自的孔洞中。可从所述接脚移除所述接脚模板并且回焊所述焊料构件。
本发明的各种态样另外提供一种制造电子装置的方法(以及以此方法制成的电子装置)，其包含取得基板，所述基板包含多个焊垫。接脚模板和多个接脚可被提供于所述基板上方，其中所述接脚模板包含多个孔洞并且所述多个接脚中的每一个接脚被定位在所述多个孔洞中的各自的孔洞之中并且与所述多个焊垫中的各自焊垫对准。所述多个接脚中的每一个接脚可被附接至所述每一个接脚的各自的焊垫。
本发明的各种态样进一步提供一种制造电子装置的方法(以及以此方法制成的电子装置)，其包含提供接脚模板，所述接脚板模包含多个孔洞。所述接脚模板被定位于基板上方，其中所述基板包含多个焊垫。提供多个接脚，其中所述多个接脚中的每一个接脚被定位在所述多个孔洞中的各自的孔洞之中并且与所述多个焊垫的各自的焊垫对准。所述多个接脚中的每一个接脚被焊接到所述基板的各自的焊垫。
本公开的上述和其他方面将在以下对各种范例性的执行的描述中被描述或者显而易见。本发明的各种态样将参考附图而呈现，使得本领域技术人员可以容易地实践各种态样。
根据本发明的各种态样，图1显示制造电子装置(例如，半导体封装…等等)的范例性方法100的流程图。所述范例性方法100可例如与任何其他于本文中所讨论的范例性方法(例如，图3的范例性方法300、图4A到4F-3的范例性方法、图5A到5C的范例性方法等等)或是所述范例性方法的任何部分共享任何或是所有的特征。根据本发明的各种态样，图2A到2I-2显示横截面视图，所述横截面视图图标一种范例性电子装置(例如，半导体封装等等)以及制造一种范例性电子装置的范例性方法。举例而言，图2A到2I-2可图示在图1的所述方法100中的各个方块图(步骤)处的范例性电子装置并且图2A到2I-2将被一起讨论。应注意的是，所述方法100的范例性方块图的顺序在不违背本发明所揭示的范畴下可以改变。
所述范例性方法100可开始执行于方块图105。所述方法100可响应于本发明所提供的任何各种原因或条件、非限制性实施例而开始被执行。举例而言，所述方法100可自动地响应从一个或多个上游及/或下游制造站所接收到的一个或多个讯号、响应来自于中央生产线控制器的讯号、当执行所述方法100过程中所要使用的组件及/或制造材料抵达时等等的情况而开始。又举例而言，所述方法100可响应于操作指令以开始执行。又举例而言，所述方法100可响应于从本发明所讨论的任何方法方块图(或步骤)所接收到的执行流程而开始执行。
在方块图110时，所述范例性方法100可包含取得、制造及/或备制基板。方块图110可包含以本发明中所提供的任何各种方式、非限制性的范例来取得、制造及/或备制基板。方块图110的各种范例性态样被呈现在图2A所显示的范例200A中。
所述经取得、经制造及/或经备制的基板可包含任何各种特性。举例而言，所述经取得、经制造及/或经备制的基板可包含呈现晶圆形式的多个基板(例如，像是硅或其他半导体晶圆或是在硅或其他半导体晶圆上、像是玻璃晶圆或面板或是在玻璃晶圆或平板上、像是金属晶圆或平板或是在金属晶圆或平板上等等)。虽然本文中所示图标且讨论的所述范例通常显示单一基板以用于清楚说明，然而在本文中所显示的任何或所有制程步骤处，所述基板可以是多个被连接的基板中的一个并且所述步骤可被同样地执行于所述多个被连接的基板中的每一个。
在本文所显示的范例中，举例而言，所述基板可仅包含电性布线电路(例如，不具有主动半导体组件及/或被动组件等等)。然而，应注意的是，本发明所揭示的范围不限于此。举例而言，所述基板可包含(或可以是)半导体晶粒，所述半导体晶粒具有主动半导体电路。又举例而言，所述基板可包含被动电子组件(例如，电阻器、电容器、电感器、整合被动组件(IPD)等等)及/或主动电子组件(例如，晶体管、逻辑电路、半导体制程组件、半导体内存组件等等)及/或光学组件等等。
图2A的范例200A显示基板210包含支撑层209(或载体)。举例而言，所述支撑层209可包含任何各种的材料(例如，硅或其他半导体材料、玻璃、金属、塑料等等)。举例而言，所述支撑层209可以是暂时性的或是可牺牲的(例如，暂时载体等等)。
所述范例性基板也可包含讯号分布结构201(或讯号重新分布结构)于所述支撑层209上。所述范例性讯号分布结构201包含多个介电层202和多个传导层203。所述讯号分布结构201可包含任何各种特性。举例而言，所述讯号分布结构可包含来自晶粒制造制程的后段(back-end-of-line，BEOL)讯号分布层，也可能或者是包含被形成在电子组件封装制程中的讯号分布层(例如，被直接地形成在半导体晶粒或晶粒焊垫上、被形成在一个或多个BEOL讯号分布层上等等)。
举例而言，所述范例性传导层203包含传导焊垫205。如本文中所示，举例而言，这样的传导焊垫205可被用来作为接脚附接、晶粒附接等等。
所述传导焊垫205可包含任何各种特性。举例而言，所述传导焊垫205可以大致上是圆形的(或是与本文中所讨论的接脚的上视图形状相匹配)。在范例性实施例中，所述传导焊垫205可包含各种金属的一层或多层(例如，钛层、钛钨层、铜层、镍层、金层等等)。举例而言，所述传导焊垫205可包含晶粒焊垫、讯号重新分布结构或层的焊垫、凸块下金属化层等等。
所述传导焊垫205可包含任何各种物理构造。举例而言，如本文一般所示，所述传导焊垫205可具有被定位在所述讯号分布结构201的所述顶部介电层202之上及/或上方的周边边界(或边缘)。举例而言，所述传导焊垫205也可具有最顶表面，所述最顶表面是垂直地低于所述讯号分布结构201的所述顶部介电层202的最顶表面。举例而言，所述讯号分布结构201的所述顶部介电层202可覆盖所述传导焊垫205的周边部分。
作为非限制性范例，所述基板210可使用无机介电层(及/或无机和有机介电层的组合)于所述讯号分布结构201中以及基于半导体材料的支撑层209。举例而言，所述基板210可利用艾马克科技公司(Amkor Technology,Inc.)的少硅整合模块(Silicon-LessIntegrated Module，SLIMTM)技术所制得。又举例而言，所述基板210可包含有机介电层(及/或无机和有机介电层的组合)于所述讯号分布结构201中以及基于半导体材料的支撑层209。举例而言，所述基板210可利用艾马克科技公司(Amkor Technology,Inc.)的硅晶圆整合扇出(Silicon Wafer Integrated Fan-out，SWIFTTM)技术所制得。所述基板210的非限制性实施例以及形成方式可在美国专利申请序号14/823,689(2015年8月11日提出)标题为“SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF”，现为美国第9,543,242号专利；以及美国专利申请序号15/707,646(2017年9月18日提出)标题为“SEMICONDUCTORPACKAGE AND FABRICATING METHOD THEREOF，代理人案件号码61420US01。而前述美国专利申请案其整体通过引用并入本文中。
举例而言，方块图110可包含从在同一设施或相同地理位置处的上游制程中取得所述基板。举例而言，方块图110也可包含从在地理位置偏远处的供货商(例如，制造厂等等)取得所述基板。
一般而言，方块图110可包含取得、制造及/或备制基板。因此，此揭示内容的范畴不应局限于任何特定种类基板的特性或是取得、制造及/或局限于备制基板的任何特定方法的特性。
在方块图115中，所述范例性方法100可包含形成焊料(或其它附接材料)。方块图115可包含以任何各种方法、本文中提供的非限制性的范例来形成焊料。方块图115的各种范例性态样被分别呈现在图2B-1和图2B-2的范例200B-1和200B-2中。
如图2B-1的范例200B-1中所示，方块图115可包含形成各自的焊料构件215于每一个所述传导焊垫205上。举例而言，方块图115可包含藉由透过施加到讯号分布结构201的可移动版模(stencil)将所述焊料构件215(例如，像是焊料膏等等)网板印刷到所述传导焊垫205上来形成焊料构件215，或是以其他方式形成焊料构件215。在所述范例200B-1中，所述焊料构件215可包含被整合于其中的助焊剂。举例而言，可以不用额外的助焊步骤。
如图2B-2的范例200B-2中所示，方块图115可包含藉由电镀焊料构件215于传导焊垫205上(或是其它形成所述焊料构件215的方法)来形成所述焊料构件215。举例而言，方块图115可接着包含形成各自的助焊构件216于每个所述焊料构件215上。
虽然本文中所显示的各种范例(例如，关于图2C和2D、关于图4C和4D等等)是基于显示于图2B-1的范例200B-1，然而显示于图2B-2中的范例200B-2可被使用。
还要注意的是，尽管在本文所显示的范例性实施方式中使用焊料，但是可以在不脱离本揭示的范围情况下使用其他形式的附接。举例而言，用来代替焊料，方块图115可印刷(或以其它方式)涂覆传导黏着剂。又举例而言，也可以使用直接无焊料金属对金属的结合(例如，铜对铜等等)。
一般而言，方块图115可包含形成焊料(或是其它附接材料)。因此，本揭示的范围不应受限于形成焊料(或其它附接材料)的任何特定方式的特性或受限于任何特定类型的焊料(或其它附接材料)的特性。
在方块图120中，所述范例性方法100可包含定位接脚模板和接脚。方块图120可包含以任何各种方法、本文中提供的非限制性的范例来定位所述接脚模板和接脚。方块图120的各种范例性态样被呈现在图2C所显示的范例200C中。
如图2C中的范例200C所示，方块图120可例如定位接脚模板221(例如，金属薄片版模等等)于所述基板210上方。举例而言，所述接脚模板221可包含多个孔洞222，每个孔洞222对应于所述传导焊垫205中的各自的一个。举例而言，方块图120可包含横向地定位所述孔洞222的每一个直接地在所述传导焊垫205中的各自的一个上方(例如，在所述传导焊垫205中的各自的一个上的各自的焊料构件215及/或助焊构件216上方)。
如图2C中所示，所述接脚模板221可充分的偏离(或高于)所述基板210使得所述接脚模板221不接触所述焊料构件215(及/或助焊构件216，如果有的话)。举例而言，所述接脚模板221可具有厚度，所述厚度小于所述接脚220的高度。在范例性实施例中，所述接脚模板221的所述厚度与所述接脚模板221的底部和所述焊料构件215(及/或助焊构件216)的顶侧之间的垂直距离的组合是小于或等于所述接脚220的高度。举例而言，这样的相对尺寸可能限制单个孔洞222对单个接脚220的占据。
举例而言，多个接脚220可被定位在所述接脚模板221上(例如，卸除、注入、挖掘、吹落等等)。在图2C的范例200C中，所述接脚220中的一些或全部可能不被定位在各自的孔洞中。应注意的是，虽然范例200C图标相同数量的接脚220和孔洞222，然而所述接脚220在数量上可能超过所述孔洞222。
所述接脚220可包含任何各种特性。举例而言，所述接脚220可以是圆柱形状，例如具有圆形的横截面以及平坦的顶部和底部表面。又举例而言，所述接脚220可具有椭圆形的横截面、多边形的横截面、非圆形的横截面等等。所述接脚220的非限制性范例被显示于图2I-1的范例200I-1中。此范例性接脚220是一般的圆柱形状，具有在侧边和顶端及/或底端之间的曲线(或平滑)转变223。举例而言，所述顶部及/或底部可能是斜面。显示于图2I-1中的范例200I-1中的接脚220具有150μm的直径以及300μm的纵向高度。然而，本揭示的范围不局限于任何特定的尺寸。举例而言，所述接脚220可能具有的直径范围在100μm到250μm。又举例而言，所述接脚220可能具有的高度范围在50μm到300μm。举例而言，所述接脚220可具有一高度，所述高度是大于所述接脚220的宽度(例如，直径、次轴宽度、主轴宽度等等)，但是本揭示的范围不局限于此。
在各种范例性实施例中，所述接脚220将具有直径，所述直径小于所述传导焊垫205的直径。举例而言，所述接脚220的直径可能在小于所述传导焊垫205的直径的10％到25％的范围中。又举例而言，所述接脚220的直径可能在小于所述传导焊垫的直径的25％到50％的范围中。
在各种范例性实施例中，所述接脚220可能实质上厚于打线接合导线，例如其直径可以是大约25μm(例如，至少两倍厚、至少五倍厚等等)。这样的厚度可提供各种益处。举例而言，低于特定的直径或尺寸，导线可能黏在一起并且实质上不利地影响所述制造过程，及/或这样的导线在处理过程中可能相对地更容易弯曲。又举例而言，这样的厚度可以提供在典型的打线接合导线中所没有的结构稳定性，例如在处理和/或囊封期间。
虽然所述范例性接脚220(以及所有本文中的接脚、接脚420、接脚520等等)显示具有一般平坦的末端，但是本揭示的范围不局限于此。举例而言，所述接脚的顶部端及/或底部端可包含沟槽、凹槽、锯齿状图案、粗糙度等等。举例而言，这样的特征可提升焊接稳定度及/或黏着稳定度(例如，藉由允许用于助焊蒸汽和气体的排气、藉由提供粗糙的黏合表面等等)。又举例而言，所述接脚的顶部端及/或底部端可包含凸或凹形状、n边多边形形状、非垂直侧边等等。
回到图2C，例如所述孔洞222通常形状像所述接脚220。举例而言，所述孔洞222可以是圆柱形状以匹配圆柱形状接脚220等等。在范例性实施例中，所述孔洞222的直径可能稍微大于所述接脚的直径并且尺寸设计成在保持置放精确度的同时提高接脚的定位时间效率。举例而言，所述孔洞222的直径可以在10μm到60μm的范围中(例如，大于40μm、大于50μm等等)，其大于所述接脚220的直径。又举例而言，所述孔洞222的直径范围在大于所述接脚220的直径的10％到50％的范围中(例如大于25％、大于33％等等)。又应注意的是，所述孔洞222(例如，在所述模板221的上侧处等等)可具有弯曲的、倾斜的、斜面的开口来增加以所述接脚220对所述孔洞222的填充。
所述接脚220可以任何各种方式被形成。举例而言，所述接脚220可藉由将导线切割成区段而形成。举例而言，所述接脚220也可以藉由电镀、模制、印刷、回焊、沉积等等方式而被形成。
一般而言，方块图120可包含定位接脚模板和接脚。因此，本揭示的范围不应局限于任何特定的定位接脚模板和接脚的特性或是局限于任何特定类型的接脚模板和接脚的特性。
在方块图125中，所述范例性方法100可包含定位接脚在接脚模板孔洞中。方块图125可包含以本揭示所提供的非限制性的范例的任何各种方式来定位接脚于接脚模板孔洞中。方块图125的各种范例性态样被呈现在图2D所示的范例200D中。
举例而言，方块图125可包含振动所述接脚模板221以推挤所述接脚220，直到每个孔洞222被各自的接脚220所填充为止。在范例性实施例中，方块图125包含以任何各种运动模式在横向方向上振动所述接脚模板221(例如，在与基板210的一般平面平行的平面中)。应注意的是，在各种实施例中，也可能有用于振动的垂直组件。举例而言，所述振动运动的范围可以是传导焊垫205(或是焊料215及/或其助焊剂216)的直径(或宽度)的一部分，例如所述焊垫直径的5-10％、所述焊垫直径的1-20％等等。可以使用各种振动频率中的任何一种。举例而言，可使用在1KHz到5KHz(例如，2KHz、3KHz等等)的范围的振动频率。
又举例而言，方块图125可包含扫或刷所述接脚220于所述孔洞222上方(例如，反复地)直到所述孔洞222的每一个被各自的接脚220所填充。举例而言，这样的扫或刷可被单独使用或是可与所述振动运动结合(例如，连续地或并行地)。
在范例性实施例中，当每个接脚填充到(或是被直接地取放到)其各自的孔洞222中时，所述接脚220可接触其各自焊料构件215(或助焊构件216)的顶侧。所述接脚220接着可被黏接到其各自的焊料构件215(或助焊构件216)，其可以例如是有黏性的(或黏的)。举例而言，所述接脚220也可沉入其各自的焊料构件215(或助焊构件216)的顶侧之中。
一般而言，方块图125可包含定位接脚到接脚模板孔洞中。因此，本揭示的范围不应局限于以任何特定的方式将接脚定位到接脚模板孔洞中的特性。
应注意的是，在各种范例性实施例中，例如，在定位接脚模板和接脚之前，在方块图120中定位所有接脚已经就位的接脚模板，则可以省略方块图125，并且方块图120可包含放置所述模板和接脚使得所述接脚被放置以接触所述焊料(或助焊剂)，例如降低所述模板使得每个所述接脚220接触其各自的焊料构件215(或助焊构件216，如果有的话)。
在方块图130中，所述范例性方法100可包含移除所述接脚模板并且回焊所述焊料。方块图130可包含以本揭示所提供的非限制性的范例的任何各种方式来移除所述接脚模板和回焊所述焊料。方块图130的各种范例性态样被呈现于图2E的范例200E中。
举例而言，在回焊所述焊料构件215之前(或在另外的实施例中，是在所述回焊之后)，方块图130可包含将所述接脚模板221向上抬升。当所述接脚模板221被向上抬升时，被黏接到所述焊料构件215(或助焊构件216，如果有的话)的所述接脚220留在原地。
应注意的是，在所述接脚模板221的移除之前，多余的接脚220(如果有的话)可从所述接脚模板221的顶侧被移除、可从具有孔洞222的所述接脚模板221的区域横向地被移除等等。举例而言，这样的移除可藉由扫、刷、吹、倾倒、吸等等的方法被执行。
在所述接脚模板221移除之后(或在另外的实施例中，是在所述移除之前)，方块图130可包含回焊焊料构件215(例如，利用质量回焊(mass reflow)等等)。应注意的是，在不违背本揭示的范围的情况下，可使用用来代替焊料的其它形式的接脚附接。举例而言，传导黏着剂可被施加及固化以取代施加及回焊焊料。又举例而言，可使用无焊料的直接金属对金属(例如，铜对铜等等)接合以附接所述接脚220到所述传导焊垫205。
在所述回焊(或是其它方式的附接)之后，所述接脚220中的每一个被固定地焊接到各自的一个传导焊垫205。这样经焊接的接脚的非限制性的范例已分别被揭示于图2I-1的范例200I-1和图2I-2的范例200I-2中。参照范例200I-1，经回焊的焊料215’可形成填料，所述填料上升到所述接脚220的侧边的至少一部分。如图2I-1所示，可以有经回焊的焊料215’的层，所述层被直接定位在所述接脚220和所述传导焊垫205之间而将彼此直接接触的所述接脚220和所述焊垫205彼此分隔开。然而，在另外的实施例中，所述接脚220的底侧可直接接触所述传导焊垫205的顶侧。举例而言，经回焊的焊料215’可覆盖所述焊垫205的整个顶侧，但是不一定。
参照范例200I-2，可使用较少量的焊料(相对于范例200I-1)。举例而言，使用较少量的焊料可减少所述焊料和所述接脚金属(例如，铜等等)之间随着时间增加而产生的电子漂移，使得焊料接合具有提高的传导性能和增加的使用寿命。在范例200I-2中，直接在所述接脚220的底端和所述传导焊垫205的周边之间的间隙208(或体积或凹痕)可以没有焊料。根据图2I-1中所示的范例200I-1，有经回焊的焊料215’的层，所述层被直接定位在所述接脚220和所述传导焊垫205之间、将所述接脚220和所述焊垫205从彼此直接接处而彼此分隔开。然而，在另外的实施例中，所述接脚220的底侧可直接接触所述传导焊垫205的顶侧。经回焊的焊料215’可覆盖整个传导焊垫205，但不一定。举例而言，经回焊的焊料215’的外部周边可在所述接脚220的侧周边外面侧向地延伸，但不一定。
一般而言，方块图130可包含移除所述接脚模板且回焊所述焊料。因此，本揭示的范围不应局限于任何移除接脚模板的特定方式的特征及/或局限于任何回焊焊料的特定方式的特征。
在方块图135中，所述范例性方法100可包含将电子组件安装到所述基板。方块图135可包含以本揭示所提供的非限制性的范例的任何各种方式来将电子组件安装到所述基板。方块图135的各种范例性态样被呈现在图2F所示的范例200F中，其呈现与图2A-2E的装置不同的横截面图。
举例而言，方块图135可包含安装半导体晶粒235到所述基板210的讯号分布结构201的晶粒安装焊垫。所述半导体晶粒235(或其它组件)可以任何各种方式被安装到所述讯号分布结构201。举例而言，传导凸块236(例如，柱或杆、C4凸块、传导球等等)可被连接到各自晶粒安装焊垫237，其使用各自的焊料接合238(例如，质量回焊接合、热压结合接合、雷射回焊接合等等)、使用传导黏着剂、使用无焊料直接金属对金属接合等等。
虽然仅显示单一半导体晶粒235于图2F中，然而本揭示的范围不局限于此。举例而言，一个或多个半导体晶粒及/或一个或多个被动电子组件(例如，电阻器、电容器、电感器等等)可被安装到所述讯号分布结构201。
所述经安装的电子组件可包含任何各种尺寸特性。举例而言，经安装的电子组件可具有厚度，所述厚度是整个在所述接脚220的高度之中。又举例而言，经安装的电子组件可具有在所述基板210上方的顶侧高度，所述顶侧高度是小于或等于所述接脚220的顶侧的高度。举例而言，在范例性实施例中，接脚220可以是高300μm，并且所述半导体晶粒235可以是高250μm。应注意的是，本揭示的范围不应局限于这些范例的尺寸大小。
如图2F中所示，经安装的电子组件235可被直接横向地定位在多个所述接脚220之间。举例而言，经安装的电子组件235也可以被所述接脚220侧向地围绕。
方块图135可包含以任何各种方式将所述电子组件235附接到所述讯号分布结构201。举例而言，方块图135可包含使用回焊附接、热压接合(例如，具有或不具有预先施加的非传导膏)、黏着接合、无焊料直接金属对金属接合等等。举例而言，方块图135可包含执行第二回焊，所述第二回焊不同于在方块图130处所执行的回焊。在范例性实施例中，除了形成用于所述接脚220的焊料215(及/或助焊剂216)之外，方块图115可包含形成焊料于晶粒焊垫及/或所述讯号分布结构201的其他电子组件焊垫上。在范例性实施例中，所述接脚220和所述电子组件235可全部使用单一回焊附接而被附接(例如，维持所述接脚220在固定位置直到所述电子组件235也被放置)。
一般而言，方块图135可包含安装电子组件到所述基板。因此，本揭示的范围不应局限于任何特定的安装电子组件到所述基板的方法的特征或是局限于任何类型的电子组件的特征。
在方块图140中，所述范例性方法100可包括囊封和薄化。方块图140可包含以本揭示所提供的非限制性的范例的任何各种方式来执行所述囊封和薄化。方块图140的各种范例性态样被呈现在图2G所示的范例200G中。
举例而言，方块图140可包含利用模制制程(例如，射出成形、加压成形等等)和模制材料来形成囊封材料240。又举例而言，方块图140可包含喷洒涂覆、旋转涂覆、其他沉积所述囊封材料240的方法等等。
举例而言，方块图140可包含最初地形成(例如，在任何薄化制程执行之前)囊封材料240以覆盖所述接脚220的顶端及/或任何或所有的所述电子组件235。又举例而言，方块图140可包含最初地形成囊封材料240至一高度，所述囊封材料240暴露所述接脚220的顶端及/或任何或所有的所述电子组件。
如图2G中所示，举例而言，方块图140可包含薄化(或最初地形成)所述囊封材料240以暴露所述接脚220的顶部末端表面。举例而言，所述接脚220的顶表面和所述囊封材料240的顶表面可共平面。
虽然所述范例性电子组件235(例如，半导体晶粒等等)的顶侧连同所述接脚220显示为被所述囊封材料240所覆盖，但是任一个或多个电子组件的顶侧也可以被所述囊封剂所暴露。举例而言，所述接脚220的顶表面、任何或全部的电子组件235的顶表面以及所述囊封材料240的顶表面可以是共平面。
应注意的是，在所述薄化过程中，方块图140也可以包含薄化所述接脚220及/或所述电子组件235。举例而言，所述接脚220的顶端(如同在最初就形成的)可被研磨或被磨掉、半导体晶粒235的背侧的块状半导体材料可被研磨或被磨掉等等。举例而言，如同显示于图2I-1的范例200I-1中的实施例，所述曲线(或平滑)转变223可被研磨或被磨掉以造成接脚220具有在底部端处的曲线(或平滑)转变223以及在所述侧边和所述顶端之间尖锐的转变。
应注意的是，在范例性实施方式中，方块图140包括最初就形成具有期望最终厚度的囊封材料240，并且其中任何接脚220或组件235的顶侧在最初就以所述期望的最终厚度被形成及安装，则薄化操作可以省略。
如图2G中所示，所述囊封材料240可侧向地围绕所述接脚220及所述电子组件235。所述囊封材料240也可以底部填充所述电子组件235，虽然所述电子组件235可替代而言使用与所述囊封材料240分开的材料来被底部填充。
一般而言，方块图140可包含囊封和薄化。因此，本揭示的范围不应局限于任何囊封及/或薄化的特定方式的特性。
在方块图145中，所述范例性方法100可包含执行进一步的制程。方块图145可包含以本揭示所提供的非限制性的范例的任何各种方式执行进一步的制程。方块图145的各种范例性态样被呈现于图2H所示的范例200H中。
举例而言，方块图145可包含形成顶侧讯号分布结构245(或重新分布结构)于所述接脚220、囊封材料240及/或电子组件235上方。方块图145可包含以任何各种方式形成顶侧讯号分布结构245，其中许多方式在本文中是相关于所述讯号分布结构201而被讨论。举例而言，顶侧讯号分布结构245可以是在范例200G的装置的顶上的层(介电层或传导层)的内建层或是可被放在那里以作为预内建单位。举例而言，方块图145也可以包含形成顶侧焊垫于所述接脚的顶端上(或是连接到所述接脚的顶端)。举例而言，这样的顶侧焊垫可包含凸块下金属化层等等。
又举例而言，方块图145可包含从所述基板210移除所述支撑层209(或载体)，留下被暴露的所述讯号分布结构201。举例而言，底侧传导焊垫可在所述讯号分布结构201的底侧被暴露。方块图145可包含以任何各种方式移除所述载体。举例而言，方块图145可包含藉由研磨、蚀刻、撕除、剪切、熔化、平坦化等等的方式移除所述支撑层209(或载体)。
举例而言，方块图145可接着包含在所述讯号分布结构201的底侧上内建讯号分布结构的额外的层。举例而言，方块图145也可包含形成互连结构246(例如，传导球或凸块、传导柱或杆等等)于所述讯号分布结构201的底侧上(或是于任何额外的讯号分布结构的底侧上、任何凸块下金属上等等，其可能已经被形成于最初的讯号分布结构201的底部上)。
如本文中所讨论的，到目前为止所讨论的任何或是所有制程步骤可被执行于单一基板上或是可被执行于多个连接的基板上(例如，在基板晶圆上、在基板平板上、在晶粒晶圆上等等)。在这种情况下，方块图145可包含执行单一化(或切割、或切断等等)操作，其中个别的电子装置(或封装)从其它连接的电子装置(或封装)分隔开来。举例而言，参照图2H，方块图145可包含藉由切割沿着晶圆或平板的单一化切割道来单一化范例200H的电子装置。举例而言，这样的切割造成所述讯号分布结构201、所述囊封材料240及/或所述顶侧讯号分布结构245的侧边共平面。
一般而言，方块图145可包含执行进一步的制程。因此，本揭示的范围不应局限于任何执行进一步制程的特定方法的特性。
在方块图190中，所述范例性方法100可包含接续所述方法100。这样的接续可包含任何提供于本文中的非限制性范例的各种特性。
举例而言，方块图190可包含将范例性方法100的执行流程返回到其任何方块图。又举例而言，方块图190可包含将范例性方法100的执行流程引导到任何本文中所讨论的其它方法方块图(或步骤)(例如，关于图3的范例性方法300、图4A到4F-3、图5A到5C等等)。
如本文中所讨论的关于所述接脚220，这样的接脚220可能包含任何各种的形状和尺寸。这样的接脚220的额外的范例形状被显示于图4F-1到4F-3。举例而言，所述接脚220可能包含的形状及/或尺寸是不允许所述接脚220滑动而完全地穿过接脚模板221的孔洞222。接下来将讨论适用于具有这种形状的接脚的范例性实施例。然而，应注意的是，所述范例性实施例也可被使用于当所述接脚220可以滑动而完全地穿过接脚模板221的孔洞222的情况中。
现在针对图3，根据本发明的各种态样，此图显示制造电子装置(例如，半导体封装等等)的范例性方法300的流程图。举例而言，所述范例性方法300可与任何其他于本文中所讨论的范例性方法(例如，图1的范例性方法100、图2A到2I-2的范例性方法、图5A到5C的范例性方法等等)或是所述范例性方法的任何部分共享任何或是所有的特征。根据本发明的各种态样，图4A到4F-3显示横截面视图图标范例性电子装置(例如，半导体封装等等)以及制造范例性电子装置的范例性方法。举例而言，图4A到4F-3图示在图3的所述方法300中的各个方块图(步骤)处的范例性电子装置。图3和图4A到4F-3将在下文中一起讨论。应注意的是，所述方法300的范例性方块图的顺序在不违背本发明所揭示的范畴之下可以改变。
所述范例性方法300可开始执行于方块图305。所述方法300可响应于本发明所提供的任何各种原因或条件、非限制性实施例而开始被执行。举例而言，所述方法300可自动地响应从一个或多个上游及/或下游制造站所接收到的一个或多个讯号、响应来自于中央生产线控制器的讯号、当执行所述方法300过程中所要使用的组件及/或制造材料抵达时等等的情况而开始。又举例而言，所述方法300可响应于操作指令以开始执行。又举例而言，所述方法300可响应于从本发明所讨论的任何方法方块图(或步骤)所接收到的执行流程而开始执行。
在方块图310时，所述范例性方法300可包含取得、制造及/或备制基板。方块图310可包含以本发明中所提供的任何各种方式、非限制性的范例来取得、制造及/或备制基板。举例而言，方块图310可以与本文中所讨论的并且显示于图1中的范例性方法100的方块图110共享任何或所有特性。方块图310的各种范例性态样被呈现在图2A所显示的范例200A中。
在方块图315中，所述范例性方法300可包含形成焊料(或其它附接材料)。方块图315可包含以任何各种方法、本文中提供的非限制性的范例来形成焊料。举例而言，方块图315可以与本文中所讨论的并且显示于图1中的范例性方法100的方块图115共享任何或所有特性。方块图315的各种范例性态样被分别呈现在图2B-1和图2B-2的范例200B-1和200B-2中。
在方块图317中，所述范例性方法300可包含提供接脚模板和接脚。方块图317以任何各种方法、本文中提供的非限制性的范例来提供所述接脚模板和接脚。举例而言，方块图317可以与本文中所讨论的并且显示于图1中的范例性方法100的方块图125共享任何或所有特性。方块图317的各种范例也被显示于图4A的范例400A中。
如图4A所显示的范例400A所示，例如方块图317可提供接脚模板421。举例而言，所述接脚模板421可以与本文中所讨论的图2A到2I-2的接脚模板221共享任何或所有特性。举例而言，所述接脚模板421(例如，金属薄片版模、不锈钢版模、电铸镍版模等等)可包含多个孔洞422，每个孔洞对应于各自的一个接脚420。
举例而言，所述接脚模板421可具有厚度，所述厚度是小于(或等于)所述接脚420的高度、是小于(或等于)所述接脚420的主要本体的高度等等。
在显示于图4A中的范例性实施例400A中，黏着层424(例如，黏着胶带或薄膜等等)是被黏接到接脚模板421的底侧。举例而言，所述黏着层424可被用来暂时性地维持所述接脚420(例如，当所述接脚420被定位在方块图318处)直到所述接脚420在方块图323中被释放。应注意的是，也可以使用其他维持所述接脚420在位置上的方法(例如，真空压力、电磁力、机械固持器、重力等等)。
举例而言，多个接脚420可被放置(例如，藉由卸除、注入、挖掘、吹落等等)在所述接脚模板421上。在图4A的范例400A中，所述接脚420中的一些或全部可能不被定位在各自的孔洞中。应注意的是，虽然范例400A图标相同数量的接脚420和孔洞422，然而所述接脚420在数量上可能超过所述孔洞422。
所述接脚420可包含任何各种特性。举例而言，所述接脚420可以与本文中所讨论的图2A到2I-2的接脚220共享任何或所有特性。举例而言，所述接脚420可以具有圆柱形状的本体和头部(例如，像是钉子的头部)。又例如，所述接脚420(例如，整个接脚、接脚的主要本体、接脚的头部等等)可以是圆柱形状，例如具有圆形的横截面以及平坦的顶部和底部表面。又举例而言，所述接脚420(例如，整个接脚、接脚的主要本体、接脚的头部等等)可具有椭圆形的横截面、多边形的横截面、非圆形的横截面等等。所述接脚420的非限制性范例被显示于图4F-1的范例400F-1中。此范例性接脚420具有主要本体部分420a，其一般是圆柱形状，具有在侧边和顶端及/或底端中的至少一者之间的曲线(或平滑)转变423。此范例性接脚420也具有头部部分420b，其一般是圆柱形状，具有在侧边和顶端及/或底端中的至少一个之间的曲线(或平滑)转变423。应注意的是，任何一个所述转变423可以是尖锐的(或包含不连续表面或尖锐的转角)。图4F-1的范例性接脚420的头部部分420b具有的尺寸大于所述主要本体部分420a的尺寸。
举例而言，所述顶端及/或底端可以是倾斜的。举例而言，如图4F-3的范例400F-3所示，相对于所述头部部分420b的所述主要本体部分420a的末端可具有斜面423’。所述主要本体部分420a及/或所述头部部分420b的任何末端可具有这样的斜面。
显示于图4F-1中的范例400I-F中的接脚420具有直径是180μm和纵向高度是210μm的主要本体部分420a以及直径是200μm和纵向高度是50μm的头部部分420b。然而，本揭示的范畴不局限于任何特定的尺寸。
回到图4A，例如所述孔洞422可通常塑形为相似于所述接脚420(例如，像是所述接脚420的所述主要本体部分420a)。举例而言，所述孔洞422可以是圆柱形状以匹配所述接脚的圆柱形状的主要本体部分420a等等。在范例性实施例中，所述孔洞422的直径可能稍微大于所述接脚420的所述主要本体部分420a的直径并且尺寸设计成在保持置放精确度的同时提高接脚的置放时间效率。举例而言，所述孔洞422的直径可以在大于10μm的范围中(例如，大于40μm、大于50μm等等)，其大于所述接脚420的直径。又举例而言，所述孔洞422的直径范围在大于所述接脚420的所述主要本体部分420a的直径的10％到50％的范围中(例如大于25％、大于33％等等)。又举例而言，所述孔洞422的直径可能小于所述接脚420的头部部分420b的直径，例如防止所述头部部分420b滑动穿过所述孔洞422。又应注意的是，所述孔洞422(例如，在图4A的指向中的所述模板421的上侧处等等)可具有弯曲的、倾斜的、斜面的开口来强化所述接脚420对所述孔洞422的填充。
所述接脚420可以任何各种方式被形成。举例而言，所述接脚420可藉由将导线切割成区段以及将头部部分冲压(或压缩)到每个段中而形成。举例而言，所述接脚420也可以藉由电镀、模制、印刷、回焊、沉积等等方式而被形成。
一般而言，方块图317可包含提供接脚模板和接脚。因此，本揭示的范围不应局限于任何特定的提供接脚模板和接脚的特性或是局限于任何特定类型的接脚模板和接脚的特性。
在方块图318中，所述范例性方法300可包含定位接脚于接脚模板孔洞中。方块图318可包含以本揭示所提供的非限制性的范例的任何各种方式来定位接脚于接脚模板孔洞中。举例而言，方块图318可以与本文中所讨论的图1的范例性方法100的方块图125共享任何或所有特性。方块图318的各种范例性态样被呈现在图2D所示的范例200D中。方块图318的各种范例性态样也被呈现在图4B所示的范例400B中。
举例而言，方块图318可包含振动所述接脚模板421以推挤所述接脚420，直到每个孔洞422被各自的接脚420(例如，各自的接脚420的主要本体部分420a等等)所填充为止。在范例性实施例中，方块图318可包含以任何各种运动模式在横向方向上振动所述接脚模板421(例如，在与模板421的一般平面平行的平面中)。应注意的是，在各种实施例中，也可能有用于振动的垂直组件。举例而言，所述振动运动的范围可以是传导焊垫405(或是焊料415及/或其助焊剂416)的直径(或宽度)的一部分，例如所述焊垫直径的5-10％、所述焊垫直径的1-20％等等。可以使用各种振动频率中的任何一种。举例而言，可使用在1KHz到5KHz(例如，2KHz、3KHz等等)的范围的振动频率。
又举例而言，方块图318可包含扫或刷所述接脚420于所述孔洞422上方(例如，反复地)直到所述孔洞422的每一个被各自的接脚420(或其主要本体部分420a)所填充。举例而言，这样的扫或刷可被单独使用或是可与所述振动运动结合(例如，连续地或并行地)。
在范例性实施例中，当每个接脚420填充到(或是被直接地取放到)其各自的孔洞422中时，所述接脚420可接触黏着层424的顶侧。所述接脚420接着可被黏接到黏着层424并且被固定在接脚模板421的各自孔洞422中。然而，应注意的是，在范例性实施例中，所述基板410藉由定位所述基板410于接脚模板421之上而被匹配于所述接脚420，所述黏着层424可被省略(例如，例如使用重力来维持所述接脚420在各自的孔洞422中等等方式)。
一般而言，方块图318可包含定位接脚到接脚模板孔洞中。因此，本揭示的范围不应局限于以任何特定的方式将接脚定位到接脚模板孔洞中的特性。
应注意的是，在各种范例性实施例中，例如，在方块图317中提供所有接脚已经就位的接脚模板，则可以省略方块图318。
在方块图320中，所述范例性方法300可包含定位所述接脚模板和接脚(例如，所述接脚在方块图318处被定位)。方块图320可包含以本揭示所提供的非限制性的范例的任何各种方式来定位所述接脚模板和接脚。举例而言，方块图320可以与本文中所讨论的图1的范例性方法100的方块图120及/或方块图125共享任何或所有特性。方块图320的各种范例性态样被呈现在图2C所示的范例200C中。方块图320的各种范例性态样也被呈现在图4C所示的范例400C中。
如图4C中的范例200C所示，方块图320可例如包含定位接脚模板421(例如，金属薄片版模等等)邻近于所述基板410(例如，上方、下方等等)，所述接脚模板421例如包括被定位在各自的孔洞422中的多个接脚420。所述基板410可以与本文中所讨论的图2A到2I-2的所述基板210共享任何或所有特性。举例而言，所述基板410可包含支撑层409(或载体)，其与所述支撑层209(或载体)共享任何或所有特性；以及讯号分布结构401，其与所述讯号分布结构201共享任何或所有特性。又举例而言，所述基板410可包含传导焊垫405，其与图2A到2I-2中的所述传导焊垫205共享任何或所有特性；焊料构件415，其与图2B-1到2I-2中的所述焊料构件215共享任何或所有特性；及/或助焊构件(未显示)其与图2B-2中的所述助焊构件216共享任何或所有特性。
举例而言，所述接脚模板421的每个孔洞422可对应于各自的接脚421并且对应于所述基板410的各自的一个传导焊垫405。举例而言，方块图320可包含横向地定位每一个孔洞422(或其各自的接脚420)直接地邻近(例如直接地在上方、直接地在下方等等)所述基板410的各自的传导焊垫405(例如在各自的焊料构件415及/或助焊构件上方)。如图4C的范例400C所示，每个接脚420的头部部分420b的末端表面接触并且被黏接到各自的传导焊垫405的各自的焊料构件415(及/或助焊构件，如果存在的话)。同时，每个接脚420的主要本体部分420a的末端表面黏接所述黏着层424。
如图4C中所示，接脚模板421可能被充分地抬高(或偏移)以使得所述接脚模板421不接触所述焊料构件415(及/或助焊构件，如果有的话)。在版模边缘处的此高度或偏移可藉由被连接到所述版模的底部的偏移构件、藉由被连接到所述版模的底部的连结构件等等来控制。举例而言，所述接脚模板421可具有厚度，所述厚度小于所述接脚420的高度。举例而言，在范例性实施例中，所述接脚模板421的厚度可能小于或等于接脚420的主要本体部分420a的纵向高度。
应该要理解是，虽然在图4C中所述接脚模板421被定位在所述基板410上方，然而，在其他的范例性实施例中，所述基板410可被定位在所述接脚模板上方(例如，通常倒置图4C中所示的图)。如本文中所提到的，在这样的范例性实施例中，所述黏着层424可被省略，但是不一定。
一般而言，方块图320可包含定位所述接脚模板和接脚。因此，本揭示的范围不应局限于任何特定的定位接脚模板和接脚的方法的特性或是局限于任何特定类型的接脚模板和接脚的特性。
在方块图323中，所述范例性方法300可包含从所述接脚模板释放所述接脚。方块图323可包含以本揭示所提供的非限制性的范例的任何各种方式来将所述接脚从所述接脚模板释放。举例而言，方块图323可以与图1中的范例性方法100的方块图130共享任何或所有特性。方块图323的各种范例性态样被呈现于图2E所示的范例200E中。方块图323的各种范例性态样也被呈现于图4D所示的范例400D中并且被讨论于本文中。
举例而言，如图4D所示，方块图323可包含将所述黏着层424(例如，黏着胶带或薄膜等等)从接脚模板421的顶侧和从接脚420的顶端(如图4D中的指向)撕除(或是其他移除方式)。举例而言，方块图323也可包含使用化学手段来移除所述黏着层424、施加温度来释放所述黏着层424、施加光能来释放所述黏着层424等等。举例而言，移除所述黏着层424可包含移除在所述接脚420和所述接脚模板421之间的机械耦合。
如本文中所讨论的，可使用任何维持所述接脚420在接脚模板421中的位置上的方法(例如，真空压力、电磁力、机械固持器、重力等等)。在这样的实施例中，方块图323可例如包含释放真空压力(及/或反转这样的真空)、移除任何保持所述接脚420在位置上的电磁力或机械固持器等等。
一般而言，方块图323可包含从所述接脚模板释放所述接脚。因此，本揭示的范围不应局限于任何特定的从所述接脚模板释放所述接脚的方法的特性。
在方块图330中，所述范例性方法300可包含移除接脚模板和回焊所述焊料。方块图330可包含以本揭示所提供的非限制性的范例的任何各种方式来移除接脚模板和回焊所述焊料。举例而言，方块图330可以与图1中的范例性方法100的方块图130共享任何或所有特性并且讨论于本文中。方块图330的各种范例性态样可被呈现于图2E所示的范例200E中。方块图330的各种范例性态样也可被呈现于图4E所示的范例400E中。
举例而言，方块图330可包含在回焊所述焊料构件415之前(或是在其他实施例中，回焊之后)，向上抬升所述接脚模板421。当所述接脚模板421被向上抬升时，被黏接到所述焊料构件415(或助焊构件，如果有的话)的所述接脚420留在原地。
在所述接脚模板421移除之后(或是在其他的实施例中，在移除之前)，方块图330可包含回焊所述焊料构件415(例如，使用质量回焊等等)。应注意的是，在不违背本发明所揭露的范围的情况下，可使用用来取代所述焊料的其他形式的接脚附接。举例而言，传导黏着剂可被施加及固化以取代施加及回焊焊料。又举例而言，可使用无焊料的直接金属对金属(例如，铜对铜等等)接合以附接所述接脚到所述传导焊垫。
在所述回焊之后，每个接脚421被固定地焊接到各自的一个传导焊垫405。非限制性实施例的这样的经焊接的接脚被分别提供于图4F-1所示的范例400F-1、图4F-2所示的范例400F-2以及图4F-3所示的范例400F-3。参照范例400F-1，所述经回焊的焊料415’可形成填料，所述填料上升到所述接脚420的侧边的至少一部分(例如，所述接脚420的头部部分420b的侧边的至少一部分等等)。如图4F-1所示，可以有经回焊的焊料415’的层，所述层被直接定位在所述接脚420和所述传导焊垫405之间、将所述接脚420和所述焊垫405从彼此直接接处而彼此分隔开。然而，在另外的实施例中，所述接脚420的底侧(例如，接脚420的头部部分420b的底侧等等)可直接接触所述传导焊垫405的顶侧。经回焊的焊料415’可覆盖所述焊垫405的整个顶侧，但是不一定。
参照范例400F-2，可使用较少量的焊料(相对于范例400F-1)。举例而言，使用较少量的焊料可减少所述焊料和所述接脚金属(例如，铜等等)之间随着时间增加而产生的电子漂移，使得焊料接合具有提高的传导性能和增加的使用寿命。在范例400F-2中，直接在所述接脚420的底端(例如，所述接脚420的头部部分420b的底端等等)的周边和所述传导焊垫405之间的间隙408(或体积或凹痕)可以没有焊料。根据图4F-1中所示的范例400F-1，有经回焊的焊料415’的层，所述层被直接定位在所述接脚420(例如，所述接脚420的头部部分420b等等)和所述传导焊垫405之间、将所述接脚420和所述焊垫405从彼此直接接处而彼此分隔开。然而，在另外的实施例中，所述接脚420的底侧(例如，所述接脚420的头部部分420b的底侧等等)可直接接触所述传导焊垫405的顶侧。经回焊的焊料415’可覆盖整个传导焊垫405，但不一定。举例而言，经回焊的焊料415’的外部周边在所述接脚420的侧周边外面(例如，所述接脚420的头部部分420b的侧周边外面等等)横向延伸，但不一定。
一般而言，方块图330可包含移除所述接脚模板和回焊所述焊料。因此，本揭示的范围不应局限于任何移除所述接脚模板的特定的方法的特征及/或局限于任何回焊所述焊料的特定的方法的特征。
在方块图335中，所述范例性方法300可包含安装电子组件到所述基板。方块图335可包含以本揭示所提供的非限制性的范例的任何各种方式来安装电子组件到所述基板。举例而言，方块图335可以与图1中的范例性方法100的方块图135共享任何或所有特性并且讨论于本文中。方块图335的各种范例性态样可被呈现于图2F所示的范例200F中(例如，具有图4E的经附接的接脚420等等)。
在方块图340中，所述范例性方法300可包含囊封和薄化。方块图340可包含以本揭示所提供的非限制性的范例的任何各种方式来执行囊封和薄化。举例而言，方块图340可以与图1中的范例性方法100的方块图140共享任何或所有特性并且讨论于本文中。方块图340的各种范例性态样可被呈现于图2G所示的范例200G中(例如，具有图4E的经附接的接脚420等等)。
在方块图345中，所述范例性方法300可包含执行进一步的制程。方块图345可包含以本揭示所提供的非限制性的范例的任何各种方式来执行进一步的制程。举例而言，方块图345可以与图1中的范例性方法100的方块图145共享任何或所有特性并且讨论于本文中。方块图345的各种范例性态样可被呈现于图2H所示的范例200H中(例如，具有图4E的经附接的接脚420等等)。
在方块图390中，所述范例性方法300可包含接续所述方法300。所述接续可包含本揭示所提供的非限制性的范例的任何各种特性。
举例而言，方块图390可包含将范例性方法300的流程返回到其任何方块图。又举例而言，方块图390可包含将范例性方法300的执行流程引导到任何本文中所讨论的其它方法方块图(或步骤)(例如，关于图1的范例性方法100、图2A到2I-2、图5A到5C等等)。
如本文中所讨论的，例如在本文中所讨论的范例方法100或300中，有安装接脚的所述基板可包含主动半导体晶粒(或其晶圆)，并且所述接脚可被安装在晶粒(或其晶圆)的主动表面上的焊垫。又举例而言，所述接脚可被安装到讯号分布层，所述讯号分布层已经被形成到所述晶粒的主动表面上方。应注意的是，在各种其他的实施例中，例如藉由结合硅通孔或是其它讯号路由技术，所述接脚可被安装到各种类型的半导体晶粒的背侧。
在此范例中，附接有接脚的半导体晶粒可接着被耦接到其它的基板(例如，主板、层叠基板、印刷电路板(PCB)、封装基板、另外的封装、另外的晶粒等等)。图5A到5C提供这样的操作的范例500A、500B和500C。举例而言，在图5A到5C中所显示的范例性方法和结构可以与图1、图2A到2I-2、图3、图4A到4F-3等等中所显示的范例性方法和结构共享任何或所有特性。
举例而言，图5A的范例500A可以与图2的范例200E和图4的范例400E共享任何或所有特性并且讨论于此。在此范例中，所述支撑层509(或载体)可包含块材半导体材料，所述块材半导体材料中的至少一些可以是所述成品电子装置的永久材料。范例500A也包含讯号分布结构501、传导焊垫505、焊料构件515以及接脚520，前述构件的许多范例已揭示于本文中。
图5B的范例500B显示提供基板590，此所述范例500A将被安装于所述基板590上。所述范例基板590包含基底599、含有各种介电层和传导层的讯号分布结构598以及传导焊垫575。举例而言，所述范例性基板590可以与讨论于本文中的任何其他基板(例如，基板210等等)共享任何或所有的特征。举例而言，所述范例性基板590可包含封装基板、主板、层叠基板、印刷电路板(PCB)、无核心(coreless)基板、另外的封装、另外的晶粒等等)。
范例500B也可包含形成在传导焊垫575上的焊料构件585。应注意的是，如本文中所讨论的，助焊构件可被加入。所述焊料构件585可包含任何各种的特性。举例而言，焊料构件585可与本文中所讨论的任何焊料构件(例如，焊料构件215等等)共享任何或所有的特征。又应注意的是，如本文中所讨论的，可以使用任何特种形式的附接(例如，传导环氧树脂、无焊料金属对金属接合等等)。
图5C的范例500C显示范例500A(如图5A中所示)被耦接到(如图5B中所示的范例500B的)所述基板590，举例而言，藉由定位所述接脚520与所述焊料构件585接触并且执行回焊制程。应注意的事，任何各种其它的操作可被执行(例如，所述基板510和基板590之间的底部填充、模制、形成额外的讯号分布结构、形成互连结构、单一化等等)。
综上所述，本发明的各种态样提供一种电子装置及其制造方法。作为非限制性的实施例，本揭露的各种态样提供一种具有顶侧接脚阵列的电子装置，例如可用于三维堆栈的顶侧接脚阵列；以及用于制造这种电子装置的方法。虽然已经参考某些态样和范例描述了前述内容，但是所属技术领域中具有通常知识者将理解，在不脱离本公开的范围的情况下，可以进行各种改变并且可以替换等同物。另外，在不脱离本公开的范围的情况下，可以进行许多修改以使特定情况或材料适应本公开的教示。因此，本公开企图不限于所揭示的特定范例，而是本公开将包含落入所附权利要求书的范畴内的所有范例。

Claims (20)

1.一种电子装置，其特征在于，所述电子装置包含：
第一重新分布结构，其包括第一重新分布结构第一侧和与所述第一重新分布结构第一侧相对的第一重新分布结构第二侧，其中所述第一重新分布结构第一侧包括第一传导焊垫的第一侧、第二传导焊垫的第一侧及介电层的第一侧，且其中所述第二传导焊垫的第二侧覆盖所述介电层的所述第一侧的一部分；
半导体晶粒，其包括晶粒第一侧和晶粒第二侧，其中所述晶粒第二侧面对所述第一重新分布结构第一侧，且其中所述晶粒第二侧电耦合至所述第一重新分布结构第一侧的所述第一传导焊垫；
传导接脚，其包括接脚第一末端、接脚第二末端及在所述接脚第一末端和所述接脚第二末端之间的接脚主要本体，其中在所述接脚第一末端处的所述传导接脚的直径以及在所述接脚第二末端处的所述传导接脚的直径不大于接脚主要本体的直径；以及
焊料，其将所述接脚第二末端耦合至所述第一重新分布结构第一侧的所述第二传导焊垫的所述第一侧。
2.根据权利要求1所述的电子装置，其特征在于，进一步包括：
第二重新分布结构，其包括第二重新分布结构第一侧和与所述第二重新分布结构第一侧相对的第二重新分布结构第二侧，
其中所述接脚第一末端耦合至所述第二重新分布结构第二侧。
3.根据权利要求2所述的电子装置，其特征在于，所述第二重新分布结构包括组装基板的一个或多个介电层及一个或多个传导层。
4.根据权利要求3所述的电子装置，其特征在于，所述组装基板被安装在所述接脚第一末端的顶部，使得所述接脚第一末端耦合至所述一个或多个传导层而没有焊料。
5.根据权利要求1所述的电子装置，其特征在于，包括：
传导凸块，其沿着所述晶粒第二侧，且
其中所述传导凸块将所述半导体晶粒耦合至所述第一重新分布结构第一侧的所述第一传导焊垫。
6.根据权利要求1所述的电子装置，其特征在于，包含所述接脚第一末端和所述接脚第二末端的所述传导接脚是圆柱形状。
7.根据权利要求1所述的电子装置，其特征在于，包括：
模制材料，其包括模制材料第一侧及与所述模制材料第一侧相对的模制材料第二侧，其中所述模制材料囊封所述接脚主要本，且
其中所述接脚第一末端与所述模制材料第一侧共面。
8.一种电子装置，其特征在于，包含：
第一重新分布结构，其包括第一重新分布结构第一侧及与所述第一重新分布结构第一侧相对的第一重新分布结构第二侧，其中所述第一重新分布结构第一侧包含传导部分和传导焊垫；
半导体晶粒，其包括晶粒第一侧及与所述晶粒第一侧相对的晶粒第二侧，其中所述晶粒第二侧面对所述第一重新分布结构第一侧，且其中所述晶粒第二侧电耦合至所述第一重新分布结构第一侧的所述传导焊垫；
接脚，其包括接脚第一末端、接脚第二末端以及邻接所述接脚第一末端和所述接脚第二末端的接脚侧壁；
传导材料，其将所述接脚第二末端耦合至所述第一重新分布结构第一侧的所述传导部分；
模制层，其囊封所述接脚侧壁，其中所述模制层包括模制层第一侧以及与所述模制层第一侧相对的模制层第二侧；以及
第二重新分布结构，其包括第二重新分布结构第一侧及与所述第二重新分布结构第一侧相对的第二重新分布结构第二侧，其中所述第二重新分布结构第二侧在所述模制层第一侧上且耦合到所述接脚第一末端，所述接脚第一末端与所述模制层第一侧共面。
9.根据权利要求8所述的电子装置，其特征在于，进一步包括：
传导凸块，其沿着所述晶粒第二侧，且
其中所述传导凸块将所述半导体晶粒耦合至所述第一重新分布结构第一侧的所述传导焊垫。
10.根据权利要求8所述的电子装置，其特征在于，所述接脚和所述传导材料是不同的材料；且
所述传导材料包括焊料。
11.根据权利要求8所述的电子装置，其特征在于，所述传导材料包括传导黏着剂。
12.根据权利要求8所述的电子装置，其特征在于，所述传导材料包括一部分是在所述接脚第二末端及所述第一重新分布结构第一侧的所述传导部分之间。
13.根据权利要求8所述的电子装置，其特征在于，所述传导材料包括填料，所述填料上升到所述接脚侧壁的一部分。
14.根据权利要求8所述的电子装置，其特征在于，包含所述接脚第一末端和所述接脚第二末端的所述接脚是圆柱形状。
15.根据权利要求8所述的电子装置，其特征在于，所述模制层第一侧接触所述第二重新分布结构第二侧。
16.根据权利要求8所述的电子装置，其特征在于，所述模制层囊封所述半导体晶粒的至少一部分。
17.一种用于制造电子装置的方法，其特征在于，所述方法包含：
提供第一重新分布结构，所述第一重新分布结构包括第一重新分布结构第一侧及与所述第一重新分布结构第一侧相对的第一重新分布结构第二侧，其中所述第一重新分布结构第一侧包括第一传导焊垫及第二传导焊垫；
提供包含接脚的部件，所述接脚穿透所述部件，其中每个接脚包括接脚第一末端、接脚第二末端以及接脚主要本体，所述接脚主要本体具有的直径至少与在所述接脚第一末端处的所述接脚的直径以及在所述接脚第二末端处的所述接脚的直径一样大；
定位所述部件，所述部件包括所述接脚在所述第一重新分布结构第一侧上方，使得穿透所述部件的所述接脚的每个接脚第二末端是定位在所述第一传导焊垫上方；
使用传导材料以将每个接脚第二末端附接至所述第一重新分布结构第一侧的所述第一传导焊垫；以及
将半导体晶粒附接至所述第一重新分布结构第一侧，其中所述半导体晶粒包括晶粒第一侧及与所述晶粒第一侧相对的晶粒第二侧，且其中前述附接包括将所述晶粒第二侧电耦合至所述第一重新分布结构第一侧的所述第二传导焊垫。
18.根据权利要求17所述的方法，其特征在于，进一步包括提供囊封材料，所述囊封材料包括囊封材料第一侧及囊封材料第二侧，其中所述囊封材料覆盖所述第一重新分布结构第一侧且延伸于所述半导体晶粒和所述接脚之间。
19.根据权利要求18所述的方法，其特征在于，进一步包括通过所述囊封材料第一侧薄化所述囊封材料，其中前述薄化暴露每个接脚第一末端且使得每个接脚第一末端与所述囊封材料第一侧共面。
20.根据权利要求18所述的方法，其特征在于，进一步包括建构组装基板的一个或多个传导层及一个或多个介电层于所述囊封材料第一侧上，使得所述一个或多个传导层耦合至每个接脚第二末端。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US11569159B2 (en) 2019-08-30 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of chip package with through vias
CN113056098B (zh) * 2021-02-10 2022-09-23 华为数字能源技术有限公司 电子元件封装体、电子元件组装结构及电子设备

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4526651A (en) * 1983-09-30 1985-07-02 Melamine Chemicals, Inc. Process for oxygen bleaching paper pulp using melamine as a viscosity stabilizer
JPH06177208A (ja) 1992-12-03 1994-06-24 Murata Mfg Co Ltd フリップチップ接合構造
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US20020106832A1 (en) * 1996-11-26 2002-08-08 Gregory B. Hotchkiss Method and apparatus for attaching solder members to a substrate
JP4526651B2 (ja) * 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP2002164369A (ja) * 2000-11-28 2002-06-07 Sony Corp 半導体装置およびその製造方法
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
TW557559B (en) * 2001-07-27 2003-10-11 Ngk Spark Plug Co Resin-made substrate on which there is installed with a vertically installed pin, manufacturing method thereof, and manufacturing method for pin
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US7656031B2 (en) * 2007-02-05 2010-02-02 Bridge Semiconductor Corporation Stackable semiconductor package having metal pin within through hole of package
CN101459152B (zh) * 2007-12-11 2012-05-23 钰桥半导体股份有限公司 具金属接点导孔的堆栈式半导体封装结构
US7994043B1 (en) * 2008-04-24 2011-08-09 Amkor Technology, Inc. Lead free alloy bump structure and fabrication method
US8270176B2 (en) * 2008-08-08 2012-09-18 Stats Chippac Ltd. Exposed interconnect for a package on package system
JP2010105021A (ja) * 2008-10-30 2010-05-13 Hitachi Metals Ltd 円柱形状はんだ片
KR100959866B1 (ko) * 2009-07-20 2010-05-27 삼성전기주식회사 패키지 기판용 리드핀
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
DE102010026178A1 (de) * 2010-07-06 2012-01-12 Tews Elektronik Gmbh & Co. Kg Vorrichtung zur Herstellung von Zigaretten in der tabakverarbeitenden Industrie sowie ein Verfahren hierzu
KR101801137B1 (ko) * 2011-02-21 2017-11-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9786622B2 (en) * 2011-10-20 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
KR20130076286A (ko) * 2011-12-28 2013-07-08 삼성전기주식회사 인쇄회로기판 및 그의 제조방법
US9502360B2 (en) * 2012-01-11 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Stress compensation layer for 3D packaging
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9159695B2 (en) * 2013-01-07 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structures in package structure
US8877554B2 (en) * 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9768142B2 (en) * 2013-07-17 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming bonding structures
KR20150033937A (ko) * 2013-09-25 2015-04-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제작 방법
KR101631934B1 (ko) * 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 그 제작 방법
KR20150060036A (ko) 2013-11-25 2015-06-03 삼성전기주식회사 전력 반도체 모듈 및 그 제조 방법
US9418953B2 (en) * 2014-01-13 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging through pre-formed metal pins
US20150282367A1 (en) * 2014-03-27 2015-10-01 Hans-Joachim Barth Electronic assembly that includes stacked electronic components
US9875980B2 (en) * 2014-05-23 2018-01-23 Amkor Technology, Inc. Copper pillar sidewall protection
KR101676916B1 (ko) * 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US9733304B2 (en) * 2014-09-24 2017-08-15 Micron Technology, Inc. Semiconductor device test apparatuses
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
US9847269B2 (en) * 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9806052B2 (en) * 2015-09-15 2017-10-31 Qualcomm Incorporated Semiconductor package interconnect
CN106548998A (zh) * 2015-09-17 2017-03-29 胡迪群 封装基材的制作方法
US10043779B2 (en) * 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9865565B2 (en) * 2015-12-08 2018-01-09 Amkor Technology, Inc. Transient interface gradient bonding for metal bonds
US9984992B2 (en) * 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10483211B2 (en) * 2016-02-22 2019-11-19 Mediatek Inc. Fan-out package structure and method for forming the same
US10002857B2 (en) * 2016-04-12 2018-06-19 Qualcomm Incorporated Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US9935024B2 (en) * 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US10297575B2 (en) * 2016-05-06 2019-05-21 Amkor Technology, Inc. Semiconductor device utilizing an adhesive to attach an upper package to a lower die
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9960328B2 (en) * 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10276548B2 (en) * 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US10304801B2 (en) * 2016-10-31 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10217712B2 (en) * 2016-12-16 2019-02-26 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor process for manufacturing the same
CN106783644A (zh) * 2017-01-13 2017-05-31 中芯长电半导体（江阴）有限公司 一种双面扇出型晶圆级封装方法及封装结构
US10256114B2 (en) * 2017-03-23 2019-04-09 Amkor Technology, Inc. Semiconductor device with tiered pillar and manufacturing method thereof
KR20180124256A (ko) * 2017-05-11 2018-11-21 에스케이하이닉스 주식회사 몰드비아를 갖는 적층 반도체 패키지 및 그의 제조방법
US10229892B2 (en) * 2017-06-28 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing a semiconductor package
US10283474B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10867924B2 (en) * 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10304805B2 (en) * 2017-08-24 2019-05-28 Micron Technology, Inc. Dual sided fan-out package having low warpage across all temperatures
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US10276543B1 (en) * 2017-10-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor device package and method of forming semicondcutor device package
US10515827B2 (en) * 2017-10-31 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package with recessed interposer substrate
JP6981234B2 (ja) * 2017-12-22 2021-12-15 住友電装株式会社 バッテリターミナルカバー
US10802825B2 (en) * 2019-02-25 2020-10-13 International Business Machines Corporation Cognitive software porting assistant system

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