CN117766524A - Manufacturing method of MIM capacitor structure - Google Patents
Manufacturing method of MIM capacitor structure Download PDFInfo
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- CN117766524A CN117766524A CN202410132330.XA CN202410132330A CN117766524A CN 117766524 A CN117766524 A CN 117766524A CN 202410132330 A CN202410132330 A CN 202410132330A CN 117766524 A CN117766524 A CN 117766524A
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- polymer
- mim capacitor
- dielectric layer
- manufacturing
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- 239000003990 capacitor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 59
- 229920000642 polymer Polymers 0.000 claims abstract description 43
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000004140 cleaning Methods 0.000 claims abstract description 16
- 238000004380 ashing Methods 0.000 claims abstract description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 239000007789 gas Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a manufacturing method of an MIM capacitor structure, which comprises the following steps: providing a semiconductor structure; forming a photoresist layer covering the upper polar plate metal layer; executing a main etching step, and etching to remove the exposed dielectric layer with the preset thickness; after the main etching is finished, polymer remains on the surface of the semiconductor structure; cleaning to remove the polymer; an over etching step is carried out to etch and remove the exposed dielectric layer with the residual thickness; and removing the photoresist layer by a low-temperature ashing process. The invention eliminates the polymer covered on the surface of the semiconductor structure, and the residual thickness of the dielectric layer in the main etching step can prevent excessive F-based gas from contacting the lower polar plate metal layer to generate more difficult-to-remove polymer containing F. And then etching the dielectric layer with the residual thickness by using an over-etching step. And removing the photoresist layer by adopting a low-temperature ashing process, so that the polymer is prevented from being hard to remove at high temperature. The method solves the problem that defects exist in the subsequent process due to the fact that excessive polymer is generated by etching.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a manufacturing method of an MIM capacitor structure.
Background
With the rapid growth of wireless communication application demands, RF LDMOS (radio frequency laterally diffused MOS) power devices are becoming increasingly important. The RF LDMOS power device not only has good electrical characteristics, but also can be completely compatible with the existing CMOS integrated circuit process, and is easy to realize a large-scale RF integrated circuit. The RF LDMOS device includes a MIM (Metal-insulator-Metal-dielectric-Metal) capacitor structure.
In the prior art, during the etching process of a dielectric layer in the MIM capacitor, heavy polymer is generated by etching the photoresist layer to cover the photoresist layer, so that the subsequent removal of the residual photoresist layer is affected, and finally, the heavy polymer is adhered to the MIM capacitor structure, so that defects are caused to the subsequent process.
Disclosure of Invention
The invention aims to provide a manufacturing method of an MIM capacitor structure, which is used for removing a polymer covered on the surface of a semiconductor structure, and a dielectric layer with the residual thickness in a main etching step can prevent excessive F-based gas from contacting a lower polar plate metal layer to generate an F-containing polymer which is more difficult to remove. And then etching the dielectric layer with the residual thickness by using an over-etching step. And removing the photoresist layer by adopting a low-temperature ashing process, so that the polymer is prevented from being hard to remove at high temperature. The method solves the problem that defects exist in the subsequent process due to the fact that excessive polymer is generated by etching.
The invention provides a manufacturing method of an MIM capacitor structure, which comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer from bottom to top;
forming a photoresist layer covering the upper polar plate metal layer; the photoresist layer exposes a part of the dielectric layer;
executing a main etching step, and etching to remove the exposed dielectric layer with the preset thickness by taking the photoresist layer as a mask; after the main etching is finished, polymer is remained on the surface of the semiconductor structure;
cleaning to remove the polymer;
an over etching step is carried out, and the dielectric layer with the exposed residual thickness is etched and removed;
and removing the photoresist layer by a low-temperature ashing process.
Further, after the photoresist layer is removed by the low-temperature ashing process, the method further comprises: and wet cleaning the semiconductor structure.
Further, the dry etching gas of the main etching step includes: CHF and CHF 3 、CH 2 F 2 And O 2 。
Further, in the main etching step, CH 2 F 2 The flow rate of (1) is 5sccm-100sccm, CHF 3 The flow rate of (2) is 10sccm-500sccm, O 2 The flow rate is 5sccm-100sccm, the temperature is 20 DEG-100 DEG, and the power of the RF radio frequency voltage is 100W-1000W.
Further, the step of cleaning and removing the polymer using a gas includes: CF (compact flash) 4 Ar and O 2 。
Further, in the step of cleaning and removing the polymer, CF 4 The flow rate of Ar is 5sccm-10sccm, the flow rate of Ar is 100sccm-500sccm, O 2 The flow rate is 5sccm-20sccm, the pressure is 20mT-50mT, and the power supply power is 300W-800W.
Further, the step of performing the over-etching using a gas includes: CH (CH) 2 F 2 And O 2 。
Further, the thickness of the dielectric layer remaining in the main etching step is 200-500 angstroms.
Further, the lower polar plate metal layer comprises an Al layer and a TiN layer or a TiAL layer which is positioned above the Al layer; the upper plate metal layer comprises a TiN layer or a TiAL layer.
Further, the dielectric layer comprises SiN and HFO 2 、ZrO、Al 2 O 3 Or ZrO.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a manufacturing method of an MIM capacitor structure, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer from bottom to top; forming a photoresist layer covering the upper polar plate metal layer; the photoresist layer exposes a part of the dielectric layer; executing a main etching step, and etching to remove the exposed dielectric layer with the preset thickness by taking the photoresist layer as a mask; after the main etching is finished, polymer is remained on the surface of the semiconductor structure; cleaning to remove the polymer; an over etching step is carried out, and the dielectric layer with the exposed residual thickness is etched and removed; and removing the photoresist layer by a low-temperature ashing process. The invention removes the polymer covered on the surface of the semiconductor structure, and the residual thickness of the dielectric layer in main etching can avoid excessive F-based gas contacting the lower polar plate metal layer to generate more difficult-to-remove polymer containing F (such as TiFx). And then etching the dielectric layer with the residual thickness by using an over-etching step. And removing the photoresist layer by adopting a low-temperature ashing process, so that the polymer is prevented from being hard to remove at high temperature. Solves the problem that the subsequent process has defects due to the generation of excessive polymer by etching.
Drawings
Fig. 1 is a flow chart of a method for fabricating a MIM capacitor according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a method for fabricating a MIM capacitor according to an embodiment of the invention after forming a photoresist layer.
Fig. 3 is a schematic diagram of a MIM capacitor structure according to an embodiment of the present invention after performing main etching.
Fig. 4 is a schematic diagram of a method for fabricating a MIM capacitor according to an embodiment of the present invention after cleaning and removing polymers.
Fig. 5 is a schematic diagram of a method for fabricating a MIM capacitor according to an embodiment of the present invention after performing an over-etching step.
Fig. 6 is a schematic diagram of a method for fabricating a MIM capacitor according to an embodiment of the invention after removing a photoresist layer.
Wherein, the reference numerals are as follows:
10-a lower polar plate metal layer; 11-Al layer; a 12-TiN layer; 20-a dielectric layer; 30-an upper polar plate metal layer; 40-a photoresist layer; 50-polymer.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the invention.
For ease of description, some embodiments of the present application may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the various figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
The embodiment of the invention provides a manufacturing method of an MIM capacitor structure, which is shown in figure 1 and comprises the following steps:
step S1, providing a semiconductor structure, wherein the semiconductor structure comprises a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer from bottom to top;
s2, forming a photoresist layer covering the upper polar plate metal layer; exposing part of the dielectric layer on the photoresist layer;
step S3, executing a main etching step, and etching to remove the exposed dielectric layer with the preset thickness by taking the photoresist layer as a mask; after the main etching is finished, polymer remains on the surface of the semiconductor structure;
s4, cleaning and removing the polymer;
step S5, an over-etching step is carried out, and the exposed dielectric layer with the residual thickness is etched and removed;
and S6, removing the photoresist layer by a low-temperature ashing process.
The following describes steps of a method for fabricating a MIM capacitor structure according to an embodiment of the present invention with reference to fig. 2 to 6.
In step S1, as shown in fig. 2, a semiconductor structure is provided, which includes a bottom-up bottom plate metal layer 10, a dielectric layer 20, and a top plate metal layer 30.
Illustratively, the lower plate metal layer 10 includes an Al layer 11 and a TiN layer 12 or TiAL layer over the Al layer 11; the upper plate metal layer 30 includes a TiN layer or a TiAL layer. Medium (D)The material of layer 20 includes SiN, HFO 2 、ZrO、Al 2 O 3 Or ZrO. The semiconductor structure may form a plurality of RF LDMOS devices, and two adjacent RF LDMOS devices may be isolated by shallow trench isolation (not shown).
Step S2, as shown in FIG. 2, forming a photoresist layer 40 covering the upper plate metal layer 30; photoresist layer 40 exposes a portion of dielectric layer 20. Dielectric layer 20 may be formed by PECVD, and dielectric layer 20 determines the size of the MIM capacitor and the breakdown voltage. The dielectric layer 20 is made of SiN or HFO 2 、ZrO、Al 2 O 3 Or ZrO.
Step S3, as shown in FIG. 3, a main etching step is performed, and the exposed dielectric layer 20 with a preset thickness is etched and removed by using the photoresist layer 40 as a mask; the thickness of the remaining dielectric layer of the main etching step is, for example, 200-500 a. The remaining thickness of dielectric layer 20 exposed by photoresist layer 40 during the main etch step prevents excessive F-based gas from contacting lower plate metal layer 10 to produce a more difficult to remove F-containing (e.g., tiFx-containing) polymer. After the main etch is completed, polymer 50 remains on the surface of the semiconductor structure. Specifically, after the main etching is completed, the polymer 50 remains on the upper surface, the side surface, and the side surface of the etched dielectric layer 20 of the photoresist layer 40.
The dry etching gas of the main etching step includes: CHF and CHF 3 、CH 2 F 2 And O 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein CH is 2 F 2 The flow rate of (1) is 5sccm-100sccm, CHF 3 The flow rate of (2) is 10sccm-500sccm, O 2 The flow rate is 5sccm-100sccm, the temperature is 20 DEG-100 DEG, and the power of the RF radio frequency voltage is 100W-1000W.
Step S4, as shown in fig. 3 and 4, the polymer 50 is washed away. The step of cleaning the polymer 50 from a gas includes: CF (compact flash) 4 Ar and O 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein CF is as follows 4 The flow rate of Ar is 5sccm-10sccm, the flow rate of Ar is 100sccm-500sccm, O 2 The flow rate is 5sccm-20sccm, the pressure is 20mT-50mT, and the power supply power is 300W-800W.
Step S5, as shown in FIGS. 4 and 5, an over-etching step is performed to etch the dielectric layer 20 with the remaining thickness exposed by the photoresist layer 40And (5) removing. In one example, the over-etch gas includes: CH (CH) 2 F 2 And O 2 . In another example, the over-etching gas includes C 4 F 8 、C 4 F 6 、CH 2 F 2 And O 2 Is a mixed gas of (a) and (b).
In step S6, as shown in fig. 5 and 6, the photoresist layer 40 is removed by a low temperature ashing process. Illustratively, the low temperature ashing temperature is greater than 100 degrees celsius and less than 250 degrees celsius. The low-temperature ashing gas can be mixed gas of oxygen and fluorine-containing gas, the oxygen and the fluorine-containing gas are changed into plasma by utilizing a radio frequency power source, the oxygen is used for removing unreacted photoresistance, and the fluorine-containing gas is used for removing polymers of titanium, nitrogen and carbon elements generated in the photoetching process.
Finally, cleaning the surface of the semiconductor structure by a wet method, and removing impurities, particles and the like on the surface of the semiconductor structure. In the wet cleaning or stripping process of the acid tank, the wet etching time is divided to form multiple wet sectional etches, and multiple times of flushing are performed after each time of wet sectional etching is completed, so that the acid liquor of the acid tank is kept fresh in each time of wet sectional etching, and the stripping effect on residual polymers, impurities and particles can be improved.
In summary, the present invention provides a method for fabricating a MIM capacitor structure, including: providing a semiconductor structure, wherein the semiconductor structure comprises a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer from bottom to top; forming a photoresist layer covering the upper polar plate metal layer; the photoresist layer exposes a part of the dielectric layer; executing a main etching step, and etching to remove the exposed dielectric layer with the preset thickness by taking the photoresist layer as a mask; after the main etching is finished, polymer is remained on the surface of the semiconductor structure; cleaning to remove the polymer; an over etching step is carried out, and the dielectric layer with the exposed residual thickness is etched and removed; and removing the photoresist layer by a low-temperature ashing process. The invention removes the polymer covered on the surface of the semiconductor structure, and the residual thickness of the dielectric layer in main etching can avoid excessive F-based gas contacting the lower polar plate metal layer to generate more difficult-to-remove polymer containing F (such as TiFx). And then etching the dielectric layer with the residual thickness by using an over-etching step. And removing the photoresist layer by adopting a low-temperature ashing process, so that the polymer is prevented from being hard to remove at high temperature. Solves the problem that the subsequent process has defects due to the generation of excessive polymer by etching.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
1. The manufacturing method of the MIM capacitor structure is characterized by comprising the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a lower polar plate metal layer, a dielectric layer and an upper polar plate metal layer from bottom to top;
forming a photoresist layer covering the upper polar plate metal layer; the photoresist layer exposes a part of the dielectric layer;
executing a main etching step, and etching to remove the exposed dielectric layer with the preset thickness by taking the photoresist layer as a mask; after the main etching is finished, polymer is remained on the surface of the semiconductor structure;
cleaning to remove the polymer;
an over etching step is carried out, and the dielectric layer with the exposed residual thickness is etched and removed;
and removing the photoresist layer by a low-temperature ashing process.
2. The method of manufacturing a MIM capacitor structure of claim 1, wherein,
after the photoresist layer is removed by the low-temperature ashing process, the method further comprises the following steps: and wet cleaning the semiconductor structure.
3. The method of fabricating a MIM capacitor structure according to claim 1 wherein the dry etching gas of the main etching step comprises: CHF and CHF 3 、CH 2 F 2 And O 2 。
4. The method of manufacturing a MIM capacitor structure according to claim 3, wherein,
in the main etching step, CH 2 F 2 The flow rate of (1) is 5sccm-100sccm, CHF 3 The flow rate of (2) is 10sccm-500sccm, O 2 The flow rate is 5sccm-100sccm, the temperature is 20 DEG-100 DEG, and the power of the RF radio frequency voltage is 100W-1000W.
5. The method of manufacturing a MIM capacitor structure of claim 1, wherein,
the step of cleaning and removing the polymer by using gas comprises the following steps: CF (compact flash) 4 Ar and O 2 。
6. The method of manufacturing a MIM capacitor structure of claim 5, wherein,
in the step of cleaning and removing the polymer, CF 4 The flow rate of Ar is 5sccm-10sccm, the flow rate of Ar is 100sccm-500sccm, O 2 The flow rate is 5sccm-20sccm, the pressure is 20mT-50mT, and the power supply power is 300W-800W.
7. The method of manufacturing a MIM capacitor structure of claim 1, wherein,
the step of performing the over-etch using a gas includes: CH (CH) 2 F 2 And O 2 。
8. The method of manufacturing a MIM capacitor structure of claim 1, wherein,
the thickness of the dielectric layer remaining in the main etching step is 200-500 angstroms.
9. The method of manufacturing a MIM capacitor structure of claim 1, wherein,
the lower polar plate metal layer comprises an Al layer and a TiN layer or a TiAL layer which is positioned above the Al layer; the upper plate metal layer comprises a TiN layer or a TiAL layer.
10. The method of manufacturing a MIM capacitor structure of claim 1, wherein,
the dielectric layer comprises SiN and HFO 2 、ZrO、Al 2 O 3 Or ZrO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410132330.XA CN117766524A (en) | 2024-01-30 | 2024-01-30 | Manufacturing method of MIM capacitor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410132330.XA CN117766524A (en) | 2024-01-30 | 2024-01-30 | Manufacturing method of MIM capacitor structure |
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| Publication Number | Publication Date |
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| CN117766524A true CN117766524A (en) | 2024-03-26 |
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| CN202410132330.XA Pending CN117766524A (en) | 2024-01-30 | 2024-01-30 | Manufacturing method of MIM capacitor structure |
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