CN115831863A - Power MOS device and preparation method thereof - Google Patents
Power MOS device and preparation method thereof Download PDFInfo
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- CN115831863A CN115831863A CN202211503926.3A CN202211503926A CN115831863A CN 115831863 A CN115831863 A CN 115831863A CN 202211503926 A CN202211503926 A CN 202211503926A CN 115831863 A CN115831863 A CN 115831863A
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Abstract
The application provides a power MOS device and a preparation method thereof. The method comprises the following steps: providing a substrate, and forming an interlayer dielectric layer on the substrate; forming a photoresist layer on the interlayer dielectric layer; patterning the photoresist layer to enable the interlayer dielectric layer to have an exposed area; etching to form a contact hole in the interlayer dielectric layer; carrying out a stripping process to remove the residual photoresist layer; carrying out back etching on the interlayer dielectric layer to obtain a pretreatment structure; cleaning the pretreatment structure to remove residual polymer; soaking and cleaning; and filling the contact hole with a conductive material. According to the method, after the interlayer dielectric layer is etched back in the process of preparing the power MOS device, the cleaning step of removing the polymer is added before immersion cleaning, so that polymer residue can be effectively avoided, RC delay increase of the device caused by interconnection of conductive materials of different contact holes by the polymer is avoided, defects of VFSD trailing, high height and the like of the device can be effectively avoided, and the performance of the device can be remarkably improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a power MOS device and a preparation method thereof.
Background
A power MOS (Metal-Oxide-Semiconductor) device has the advantages of fast switching speed, low loss, wide Safe Operating Area (SOA), no secondary breakdown, and the like, and thus is increasingly widely used in consumer and communication electronic products. With the rapid development of the integrated circuit industry, the device integration level is increasingly improved, and the number of structural layers of a single MOS device is increasing, so that a large number of contact holes (contacts) are required to be used for interlayer interconnection. The existing process for preparing the contact hole of the power MOS device is generally as follows: forming a dielectric layer on a substrate, carrying out photoetching and etching on the dielectric layer, then carrying out photoresist stripping, carrying out etching back (etch back) on the dielectric layer, then carrying out immersion cleaning (BAR DIP), and finally filling metal in a contact hole. Namely, in the process of preparing the contact hole, the dielectric layer is directly immersed and cleaned after back etching in the conventional power MOS device. This has the problem that the polymer generated after etching back (the previous stripping process may also cause the polymer to remain in the contact hole) is likely to be blown out to generate Peeling (Peeling) in the subsequent wet cleaning process and then remains in the contact hole, and after depositing the metal, the remaining polymer (polymer) 20 may connect the metals of different contact holes with each other, as shown in fig. 1, and the sem image of the defect distribution corresponding to fig. 1 is shown in fig. 2. This will increase the RC delay of the device, which causes problems such as VFSD (Forward Voltage of diode between S and D) tailing and high bias of the device, and thus, the switching speed of the device is decreased.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a power MOS device and a method for manufacturing the same, which are used to solve the problems that in the process of manufacturing a contact hole of a power MOS device in the prior art, immersion cleaning is directly performed after a dielectric layer is etched back, polymer residues are easily caused, metals of different contact holes are connected with each other by polymers, resistance and capacitance delay of the device is increased, the device has defects such as VFSD tailing and high level, and electrical performance of the device is reduced.
In order to achieve the above and other related objects, the present application provides a method for manufacturing a power MOS device, including the steps of:
providing a substrate, and forming an interlayer dielectric layer on the substrate;
forming a photoresist layer on the interlayer dielectric layer;
patterning the photoresist layer to enable the interlayer dielectric layer to be provided with an exposed area;
etching to form a contact hole in the interlayer dielectric layer;
carrying out a stripping process to remove the residual photoresist layer;
back-etching the interlayer dielectric layer to obtain a pretreatment structure;
the pre-treated structure is subjected to a cleaning treatment to remove residual polymer:
soaking and cleaning;
and filling a conductive material in the contact hole.
Optionally, the pre-processing structure is cleaned to remove residual polymer by plasma treatment and/or ashing followed by wet stripping.
Optionally, the plasma treatment comprises the steps of: firstly, the pretreatment structure is treated for 20s-50s under the conditions that the cavity pressure is 80mT-100mT, the radio frequency power is 1000W-2000W, the CF4 gas flow is 10sccm-30sccm, the CHF3 gas flow is 30sccm-90sccm, the argon gas flow is 450sccm-750sccm, and then the pretreatment structure is treated for 10s-30s under the conditions that the cavity pressure is 45mT-55mT, the radio frequency power is 300W-500W, the argon gas flow is 150sccm-300sccm, and the oxygen gas flow is 20sccm-80 sccm.
Optionally, the ashing process is to treat the pre-treatment structure with a gas containing oxygen and/or nitrogen, wherein the rf power during the treatment process is 200W-500W, and the treatment time is 10s-30s.
Optionally, in the wet stripping process to remove the residual polymer, the pre-treatment structure is treated with the SPM solution for 20 minutes, and then treated with the APM solution.
Optionally, in the process of back etching the interlayer dielectric layer, the pressure of the etching chamber is 100mT, the etching power is 2000W, and the etching gas includes 20sscm of CF4, 60sccm of CHF3, and 600sccm of argon.
Optionally, the method of immersion cleaning comprises RCA standard cleaning.
Optionally, the method for filling the contact hole with the conductive material includes a physical vapor deposition method, and the deposited conductive material includes copper and/or aluminum.
Optionally, the interlayer dielectric layer is made of borophosphosilicate glass, and the method for forming the interlayer dielectric layer includes a chemical vapor deposition method.
Optionally, the base includes a silicon substrate and a bottom metal layer formed on the silicon substrate, and the contact hole is connected to the bottom metal layer.
The application also provides a power MOS device which is prepared by adopting the preparation method in any scheme.
As described above, the power MOS device and the manufacturing method thereof of the present application have the following beneficial effects: according to the method, after the interlayer dielectric layer is etched back in the process of preparing the power MOS device, the cleaning step of removing the polymer is added before immersion cleaning, so that polymer residue can be effectively avoided, RC delay increase of the device caused by interconnection of conductive materials of different contact holes by the polymer is avoided, defects of VFSD trailing, high height and the like of the device can be effectively avoided, and the performance of the device can be remarkably improved.
Drawings
Fig. 1 shows a schematic electron microscope of a metal interconnection of different contact holes due to polymer residues in a process of manufacturing a power MOS device in the prior art.
FIG. 2 is a scanning electron micrograph of the defect distribution of FIG. 1.
Fig. 3 to 8 are schematic cross-sectional structures presented in a process of manufacturing a power MOS device by using the method for manufacturing a power MOS device provided in the present application.
Fig. 9 is a schematic diagram showing a comparison of rc delay of a power MOS device manufactured by the prior art and the present application, where a curve (1) shows the rc delay of the power MOS device manufactured by the prior art, and a curve (2) shows the rc delay of the power MOS device manufactured by the present application.
Fig. 10 is a VFSD comparison diagram of a power MOS device manufactured by the prior art and the present application, wherein curve (1) represents the VFSD diagram of the power MOS device manufactured by the prior art, and curve (2) represents the VFSD diagram of the power MOS device manufactured by the present application.
Description of the element reference numerals
11. Substrate
12. Interlayer dielectric layer
13. Photoresist layer
14. Contact hole
15. Conductive material
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. As in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for the convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, quantity and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.
Please refer to fig. 3 to 10.
The application provides a preparation method of a power MOS device, which comprises the following steps:
providing a substrate 11, and specifically, as shown in fig. 3, forming an inter-layer dielectric (ILD) layer 12 on the substrate 11; the base 11 is generally a substrate having a device structure formed on a surface thereof, for example, a silicon substrate having at least a bottom metal layer formed on a surface thereof, and the bottom metal layer is to be interconnected with the conductive material 15 in the contact hole 14 formed subsequently, but the base 11 is not limited thereto, and may be made of other materials or have other circuit structures formed on a surface thereof; the interlayer dielectric layer 12 is an insulating material layer, preferably boro-phospho-silicate Glass (BPSG), but may also be other materials such as zirconia or other dielectric materials, and may be a single material or multiple materials, for example, the interlayer dielectric layer 12 may be formed by material layers with different etching rates, for example, the etching rate of the lower material layer is greater than that of the upper material layer, which may ensure that the bottom of the contact hole 14 is fully opened in the subsequent etching process; the method for forming the interlayer dielectric layer 12 is preferably, but not limited to, a chemical vapor deposition method, and the chemical vapor deposition method is adopted to help ensure the deposition quality of the interlayer dielectric layer 12; the structure obtained after this step is shown in fig. 4;
forming a photoresist layer 13 on the interlayer dielectric layer 12 by using a spin coating process, wherein the thickness of the photoresist layer 13 is preferably 3000nm-5000nm;
patterning the photoresist layer 13 to enable the interlayer dielectric layer 12 to have an exposed area; specifically, in this step, the photoresist layer 13 is exposed and developed to define patterns of contact holes 14 in the photoresist layer 13, the patterns of the contact holes expose the interlayer dielectric layer 12, and the structure obtained after this step is as shown in fig. 5,
etching the interlayer dielectric layer 12 according to the patterned photoresist layer 13, for example, dry etching is used to form a plurality of contact holes 14 in the interlayer dielectric layer 12, that is, the pattern in the photoresist layer 13 is transferred to the interlayer dielectric layer (12; the number of the contact holes 14 is usually multiple, the plurality of contact holes 14 are arranged in an array, for example, and the structure obtained after the step is as shown in fig. 6;
performing a stripping process to remove the residual photoresist layer 13, for example, stripping the residual photoresist layer 13 with a stripping liquid (stripper), and the resulting structure is shown in fig. 7;
back etching (or etch back) is carried out on the interlayer dielectric layer 12 to obtain a pretreatment structure; by performing the etching back, the interlayer dielectric material layer can be prevented from flowing into the contact hole 14 due to its own fluidity, that is, the etching back ensures that no dielectric material exists in the contact hole 14, thereby preventing the occurrence of problems such as RC delay, etc., but a new polymer residue may also be generated during the etching back process, so that, next, in this embodiment, a step of performing an additional cleaning process on the pre-processed structure to remove the residual polymer is performed, for example, the pre-processed structure is subjected to a plasma process to remove the residual polymer (i.e., only a dry process is used in the processing method), or the pre-processed structure is subjected to an ashing process first, and then a wet strip (strip) is performed to remove the residual polymer (i.e., the dry process is performed first and then the wet process is performed in the processing method), or the two methods can be successively used to remove the residual polymer, and the conductive materials 15 subsequently filled in different contact holes 14 can be connected to each other by avoiding the polymer residue through the additional cleaning step on the pre-processed structure;
after the polymer removing step added after the etching back, the obtained semiconductor structure is subjected to immersion cleaning to completely remove the whole semiconductor structure, especially impurity particles on the surface of the substrate 11, so as to ensure that no polymer or other impurity particles remain in the contact hole 14;
the contact hole 14 is filled with a conductive material 15, for example, a physical vapor deposition process is first used to form a conductive material 15 layer on the surface of the contact hole 14 and the contact hole 14, and then a chemical mechanical polishing process is performed to remove the conductive material 15 outside the contact hole 14, so as to obtain the structure shown in fig. 8.
Referring to fig. 9 and 10, it can be seen that, in the power MOS device manufactured by the manufacturing method of the present application, compared with the power MOS device manufactured by the prior art, the resistance-capacitance delay and VFSD phenomena are greatly improved, and the surface has substantially no defects, which greatly improves the switching speed and the leakage phenomenon of the device, and improves the device performance.
According to the method, after the interlayer dielectric layer 12 is etched back in the process of preparing the power MOS device, the cleaning step of removing the polymer is added before immersion cleaning, so that polymer residue can be effectively avoided, RC delay increase of the device caused by interconnection of the conductive materials 15 of different contact holes 14 by the polymer is avoided, defects of VFSD trailing, high height and the like of the device can be effectively avoided, and the performance of the device can be remarkably improved.
In the preparation process, the step of removing the polymer is the key point of the application, and the setting of the process parameters is directly related to the removal effect of the polymer. The inventors have found through extensive experiments that the plasma treatment preferably comprises the following steps: firstly, the pressure of the cavity is 80mT-100mT (the numerical range is referred to in the specification, the numerical range includes the end point value if no special description exists), the radio frequency power is 1000W-2000W, and CF 4 The flow rate of the (carbon tetrafluoride) gas is 10sccm-30sccm 3 The substrate 11 is treated for 20s to 50s under the conditions that the gas flow of (trifluoromethane) is 30sccm to 90sccm, the argon gas flow is 450sccm to 750sccm, and then the pretreatment structure is treated for 10s to 30s under the conditions that the cavity pressure is 45mT to 55mT, the radio frequency power is 300W to 500W, the argon gas flow is 150sccm to 300sccm, the oxygen flow is 20sccm to 80sccm, and the argon gas is used for bombarding the polymerThe oxygen reacts with the bombarded polymer to remove the polymer.
If ashing (Asher) is used, the pre-processing structure is preferably treated with a gas comprising oxygen and/or nitrogen, with an rf power of 200W to 500W for a time of 10s to 30s, and with no argon typically used during ashing. The ashing process is mainly to modify the polymer to facilitate the removal in the subsequent wet stripping process, and if only ashing process is used without wet stripping, the residual polymer is difficult to remove.
In a preferred embodiment, the wet stripping process removes residual polymer by first using SPM solution (98% H by volume) 2 SO 4 And 30% of H 2 O 2 According to the following steps of 4:1 proportion) for 20 minutes at 120-150 deg.C, and then adopting APM solution (NH) 4 OH、H 2 O 2 And H 2 Mixed solution of O), the treatment temperature is preferably 30 to 80 ℃, and the treatment time is, for example, 5 to 30min (minutes).
By way of example, in the process of etching back the interlayer dielectric layer 12, the pressure of the etching chamber is 100mT, the etching power is 2000W, and the etching gas comprises 20sscm of CF 4 60sccm CHF 3 And 600sccm of argon gas. And it should be noted that if plasma treatment is used to remove the polymer, the plasma treatment process and etch-back process can be completed in the same etching apparatus, whereas if ashing treatment is used, the pretreatment structure is transferred to the ashing apparatus for ashing and stripping treatment, usually after the etch-back process is completed. The two modes show basically similar performance in the aspect of removing residual polymers, but the plasma treatment can be carried out in the same etching equipment with the back etching process, the transfer of a pretreatment structure is not needed, the damage of the pretreatment structure is avoided, the process steps are simpler, and the cost is lower.
The steps of plasma treatment and ashing + wet stripping for removing residual polymer may be performed in a single step or in multiple steps, depending on the requirements.
As an example, the method of immersion cleaning includes RCA standard cleaning method, for example, using SC1 solution (HCL: H) 2 O2:H 2 O = 1.
By way of example, the conductive material 15 filled in the contact hole 14 includes, but is not limited to, one or both of copper and aluminum, preferably copper, because copper has the advantages of good conductivity, difficulty in diffusion, and the like, and contributes to improving interface contact resistance and device performance. If the copper material is adopted, a copper seed layer can be formed by adopting a vapor deposition method, and then a copper main body layer is formed on the surface of the copper seed layer by adopting a physical vapor deposition method and/or an electroplating method. To enhance the adhesion of the conductive material 15, an adhesion layer, such as a titanium nitride and/or titanium layer, may be formed on the surface of the contact hole 14 before the conductive material 15 is filled.
Of course, after the filling of the contact hole 14 is completed, a process such as upper metal layer deposition is usually required, but since this part is not the focus of the present application, this will not be elaborated upon in detail.
The present application further provides a power MOS device, which is manufactured by the manufacturing method according to any of the above schemes, so that the foregoing contents can be incorporated herein in their entirety. As shown in fig. 8, the power MOS device includes a substrate, an interlayer dielectric layer on the substrate, and a contact hole formed in the interlayer dielectric layer and exposing the substrate, wherein the contact hole is filled with a conductive material. For more description of the power MOS device, please refer to the foregoing, and details are not repeated for the sake of brevity. Due to the adoption of the preparation method, compared with the prior art, the electrical performance of the power MOS device provided by the application is remarkably improved.
In summary, the present application provides a power MOS device and a method for manufacturing the same. The preparation method comprises the following steps: providing a substrate, and forming an interlayer dielectric layer on the substrate; forming a photoresist layer on the interlayer dielectric layer; patterning the photoresist layer to enable the interlayer dielectric layer to be provided with an exposed area; etching to form a contact hole in the interlayer dielectric layer; carrying out a stripping process to remove the residual photoresist layer; back-etching the interlayer dielectric layer to obtain a pretreatment structure; cleaning the pretreatment structure to remove residual polymer; soaking and cleaning; and filling a conductive material in the contact hole. According to the method, after the interlayer dielectric layer is etched back in the process of preparing the power MOS device, the cleaning step of removing the polymer is added before immersion cleaning, so that polymer residue can be effectively avoided, RC delay increase of the device caused by interconnection of conductive materials of different contact holes by the polymer is avoided, defects of VFSD trailing, high height and the like of the device can be effectively avoided, and the performance of the device can be remarkably improved. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.
Claims (10)
1. A preparation method of a power MOS device is characterized by comprising the following steps:
providing a substrate (11), and forming an interlayer dielectric layer (12) on the substrate (11);
forming a photoresist layer (13) on the interlayer dielectric layer (112);
patterning the photoresist layer (13) to enable the interlayer dielectric layer (12) to be provided with an exposed area;
etching to form a contact hole (14) in the interlayer dielectric layer (12);
performing a lift-off process to remove the residual photoresist layer (13);
back-etching the interlayer dielectric layer (12) to obtain a pretreatment structure;
the pre-treated structure is subjected to a cleaning treatment to remove residual polymer:
soaking and cleaning;
and filling the contact hole (14) with a conductive material (15).
2. The method for manufacturing a power MOS device according to claim 1, wherein the step of performing a cleaning process on the pre-processed structure to remove the residual polymer comprises performing a plasma process and/or performing an ashing process followed by a wet stripping process.
3. The method for manufacturing a power MOS device according to claim 2, wherein the plasma treatment comprises the steps of: firstly, the pressure of the cavity is 80mT-100mT, the radio frequency power is 1000W-2000W 4 The gas flow is 10sccm-30sccm 3 Processing the pretreatment structure for 20-50 s under the conditions that the gas flow is 30-90 sccm and the argon flow is 450-750 sccm; then, the pretreatment structure is treated for 10s to 30s under the conditions that the cavity pressure is 45mT to 55mT, the radio frequency power is 300W to 500W, the argon flow is 150sccm to 300sccm, and the oxygen flow is 20sccm to 80 sccm.
4. The method for manufacturing a power MOS device according to claim 2, wherein the ashing process is performed by using a gas containing oxygen and/or nitrogen to treat the pre-treatment structure, the RF power during the treatment is 200W-500W, and the treatment time is 10s-30s.
5. The method for manufacturing a power MOS device according to claim 2, wherein in the wet stripping process for removing the residual polymer, the pre-treatment structure is treated with an SPM solution for 20 minutes, and then treated with an APM solution.
6. The method for manufacturing a power MOS device according to claim 2, wherein the step of forming the MOS device is performed onIn the process of back etching the interlayer dielectric layer (12), the pressure of an etching cavity is 100mT, the etching power is 2000W, and the etching gas comprises 20sscm CF 4 60sccm CHF 3 And 600sccm of argon gas.
7. The method for manufacturing a power MOS device according to claim 2, wherein the method for immersion cleaning includes an RCA standard cleaning method.
8. Method for manufacturing a power MOS device according to claim 2, characterized in that the method for filling the contact hole (14) with the conductive material (15) comprises a physical vapor deposition method, and the deposited conductive material comprises copper and/or aluminum.
9. The method for manufacturing a power MOS device according to claim 2, wherein the material of the interlayer dielectric layer (12) comprises borophosphosilicate glass, and the method for forming the interlayer dielectric layer (12) comprises chemical vapor deposition; the base (11) comprises a silicon substrate and a bottom metal layer formed on the silicon substrate, and the contact hole (14) is connected with the bottom metal layer.
10. A power MOS device, characterized in that it is manufactured by the manufacturing method of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211503926.3A CN115831863A (en) | 2022-11-28 | 2022-11-28 | Power MOS device and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211503926.3A CN115831863A (en) | 2022-11-28 | 2022-11-28 | Power MOS device and preparation method thereof |
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| CN115831863A true CN115831863A (en) | 2023-03-21 |
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| CN202211503926.3A Pending CN115831863A (en) | 2022-11-28 | 2022-11-28 | Power MOS device and preparation method thereof |
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